JP6092737B2 - Uninterruptible power supply system - Google Patents

Description

  The present invention relates to an uninterruptible power supply system, and more particularly to an uninterruptible power supply system that outputs a high voltage.

  2. Description of the Related Art Conventionally, an uninterruptible power supply system that boosts an output voltage of an uninterruptible power supply device with a transformer and supplies the boosted voltage to a load is known (see, for example, Patent Document 1).

JP-A-5-38055

  However, the conventional uninterruptible power supply has a problem that the power loss in the transformer is large and the efficiency is low.

  Therefore, a main object of the present invention is to provide an uninterruptible power supply system capable of outputting a high voltage and having high efficiency.

  The uninterruptible power supply system according to the present invention corresponds to a transformer including a primary winding that receives AC power from a commercial AC power source and a plurality of secondary windings that are insulated from each other, and a plurality of secondary windings. And a plurality of uninterruptible power supply devices provided. Each uninterruptible power supply converts the AC power received from the corresponding secondary winding into DC power during normal times when AC power is normally supplied from the commercial AC power supply, and the DC power is used as a power storage device. It stores and converts into AC power, and converts the DC power of the power storage device into AC power during a power failure when the supply of AC power from the commercial AC power supply is stopped. Multiple uninterruptible power supply units are connected in series with the load.Each stage uninterruptible power supply unit adds its output voltage to the previous stage output voltage and outputs it to the next stage. An alternating voltage of the sum of output voltages of a plurality of uninterruptible power supply devices is applied to the load.

  In the uninterruptible power supply system according to the present invention, a high voltage is supplied to the load by connecting a plurality of uninterruptible power supply devices in series to the load. Therefore, since no output transformer is used, high efficiency can be obtained.

It is a circuit block diagram which shows the structure of the uninterruptible power supply system by Embodiment 1 of this invention. It is a circuit diagram which shows the structure of the input transformer shown in FIG. It is a circuit diagram which shows the structure of the high voltage uninterruptible power supply shown in FIG. It is a circuit diagram which shows the structure of the uninterruptible power supply device shown in FIG. FIG. 6 is a circuit diagram showing a modification of the first embodiment. It is a circuit diagram which shows the principal part of the uninterruptible power supply system by Embodiment 2 of this invention. FIG. 10 is a circuit diagram showing a modification of the second embodiment. It is a circuit diagram which shows the principal part of the uninterruptible power supply system by Embodiment 3 of this invention. FIG. 10 is a circuit diagram showing a modification of the third embodiment. It is a circuit block diagram which shows the structure of the uninterruptible power supply system by Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the high voltage uninterruptible power supply shown in FIG. It is a circuit diagram which shows the structure of the uninterruptible power supply shown in FIG. It is a time chart which shows the operation | movement of the part relevant to the U phase of the high voltage uninterruptible power supply shown in FIG. FIG. 10 is a circuit diagram showing a modification of the fourth embodiment. FIG. 20 is a circuit diagram showing another modification example of the fourth embodiment. FIG. 10 is a circuit diagram showing still another modification of the fourth embodiment. FIG. 10 is a circuit diagram showing still another modification of the fourth embodiment. FIG. 10 is a circuit diagram showing still another modification of the fourth embodiment.

[Embodiment 1]
As shown in FIG. 1, the uninterruptible power supply system according to Embodiment 1 of the present invention includes an input terminal T1, a bypass terminal T2, an output terminal T3, switches S1 to S7, an input transformer 1, a high-voltage uninterruptible power supply 2, And an uninterruptible switch 3. This uninterruptible power supply system receives three-phase three-wire commercial AC power from commercial AC power supplies 4 and 5 and outputs three-phase three-wire commercial frequency AC power to a load 6. For example, the line voltage of commercial AC power is 3300V, and the phase voltage is 1905V. However, for simplification of the drawings and description, FIG. 1 shows a circuit for one phase and one line.

  The input terminal T1 receives AC power from the commercial AC power source 4. The bypass terminal T <b> 2 receives AC power from the commercial AC power supply 5. The output terminal T3 is connected to the load 6. The switch S1 is a breaker, for example, and is connected between the input terminal T1 and the primary winding of the input transformer 1. The switch S1 is turned on during normal times when the AC power is normally supplied from the commercial AC power supply 4, and turned off during a power failure when the supply of AC power from the commercial AC power supply 4 is stopped.

  FIG. 2 is a circuit diagram showing the configuration of the input transformer 1. In FIG. 2, the input transformer 1 includes three primary windings CR, CS, and CT, and nine secondary windings CU1 to CU3, CV1 to CV3, and CW1 to CW3 that are insulated from each other. One terminals of the primary windings CR, CS, and CT receive R-phase, S-phase, and T-phase AC voltages VR, VS, and VT, respectively, and the other terminals are connected to each other. AC voltages VR, VS, and VT are all 1905 V, and their phases are shifted by 120 degrees.

  Secondary windings CU1-CU3 are electromagnetically coupled to primary winding CR. The secondary windings CV1 to CV3 are electromagnetically coupled to the primary winding CS. The secondary windings CW1 to CW3 are electromagnetically coupled to the primary winding CT. U-phase AC voltages VU1 to VU3 are output between terminals of secondary windings CU1 to CU3, respectively. Between the terminals of the secondary windings CV1 to CV3, V-phase AC voltages VV1 to VV3 are output, respectively. Between the terminals of the secondary windings CW1 to CW3, W-phase AC voltages VW1 to VW3 are output, respectively. AC voltages VU1 to VU3, VV1 to VV3, and VW1 to VW3 are all 635V. The phases of the U-phase AC voltages VU1 to VU3, the V-phase AC voltages VV1 to VV3, and the W-phase AC voltages VW1 to VW3 are shifted by 120 degrees.

  FIG. 3 is a circuit block diagram showing the configuration of the high-voltage uninterruptible power supply 2. In FIG. 3, the high-voltage uninterruptible power supply 2 includes a control circuit 7, nine uninterruptible power supplies UU1-UU3, UV1-UV3, UW1-UW3, nine batteries 8, and three output terminals TU. , TV, TW. The control circuit 7 controls the entire high voltage uninterruptible power supply 2. For example, the control circuit 7 controls the uninterruptible power supply devices UU1 to UU3, UV1 to UV3, UW1 to UW3 so that the output voltages VU, VV, and VW of the high-voltage uninterruptible power supply device 2 become target voltages.

  Uninterruptible power supply devices UU1 to UU3, UV1 to UV3, UW1 to UW3 are connected to secondary windings CU1 to CU3, CV1 to CV3, and CW1 to CW3, respectively, and to nine batteries 8 respectively.

  The uninterruptible power supply units UU1 to UU3 normally convert AC power received from the secondary windings CU1 to CU3 to DC power, respectively, store the DC power in the three batteries 8 and convert to AC power. In the event of a power failure, the DC power of each of the three batteries 8 is converted into AC power.

Between the output terminals Tc and Td of the uninterruptible power supply devices UU1 to UU3, AC voltages VU11 to VU13 having a constant voltage (635 V) are output at commercial frequencies, respectively. The output terminal Td of the uninterruptible power supply UU1 is connected to the neutral point NP, and the output terminals Tc of the uninterruptible power supply UU1 and UU2 are connected to the output terminals Td of the uninterruptible power supply UU2 and UU3, respectively. The output terminal Tc of UU3 is connected to the output terminal TU.

  That is, uninterruptible power supply devices UU1 to UU3 are connected in series between output terminal TU and neutral point NP. The uninterruptible power supply UU2 adds its own output voltage VU12 to the output voltage VU11 of the previous uninterruptible power supply UU1, and outputs it to the next stage. The uninterruptible power supply UU3 adds its own output voltage VU13 to the output voltage VU11 + VU12 of the previous uninterruptible power supply UU2, and outputs it to the output terminal TU. Eventually, the total AC voltage VU = VU11 + VU12 + VU13 of the output voltages VU11 to VU13 of the uninterruptible power supply devices UU1 to UU3 is output to the output terminal TU. The AC voltage VU, that is, the U-phase voltage VU is 635 × 3 = 1905V.

  Similarly, the uninterruptible power supply devices UV1 to UV3 normally convert AC power received from the secondary windings CV1 to CV3 to DC power, respectively, and store the DC power in the three batteries 8 and AC. In the case of a power failure, the direct current power of each of the three batteries 8 is converted into alternating current power.

Between the output terminals Tc and Td of the uninterruptible power supply devices UV1 to UV3, AC voltages VV11 to VV13 having a constant voltage (635 V) are output at commercial frequencies, respectively. The output terminal Td of the uninterruptible power supply UV1 is connected to the neutral point NP, and the output terminals Tc of the uninterruptible power supply UV1 and UV2 are connected to the output terminals Td of the uninterruptible power supply UV2 and UV3, respectively. The UV3 output terminal Tc is connected to the output terminal TV.

  That is, uninterruptible power supply devices UV1 to UV3 are connected in series between output terminal TV and neutral point NP. The uninterruptible power supply UV2 adds its own output voltage VV12 to the output voltage VV11 of the previous uninterruptible power supply UV1 and outputs it to the next stage. The uninterruptible power supply UV3 adds its own output voltage VV13 to the output voltage VV11 + VV12 of the previous uninterruptible power supply UV2 and outputs it to the output terminal TV. Eventually, the AC voltage VV = VV11 + VV12 + VV13, which is the sum of the output voltages VV11 to VV13 of the uninterruptible power supply devices UV1 to UV3, is output to the output terminal TV. The AC voltage VV, that is, the V-phase voltage VV is 635 × 3 = 1905V.

  Similarly, uninterruptible power supply devices UW1 to UW3 normally convert AC power received from secondary windings CW1 to CW3 into DC power, respectively, and store the DC power in three batteries 8 and AC. In the case of a power failure, the direct current power of each of the three batteries 8 is converted into alternating current power.

Between the output terminals Tc and Td of the uninterruptible power supply devices UW1 to UW3, AC voltages VW11 to VW13 having a constant voltage (635 V) are output at commercial frequencies, respectively. The output terminal Td of the uninterruptible power supply UW1 is connected to the neutral point NP, and the output terminals Tc of the uninterruptible power supply UW1 and UW2 are connected to the output terminals Td of the uninterruptible power supply UW2 and UW3, respectively. The output terminal Tc of UW3 is connected to the output terminal TW.

  That is, uninterruptible power supply devices UW1 to UW3 are connected in series between output terminal TW and neutral point NP. The uninterruptible power supply UW2 adds its own output voltage VW12 to the output voltage VW11 of the previous uninterruptible power supply UW1, and outputs it to the next stage. The uninterruptible power supply UW3 adds its own output voltage VW13 to the output voltage VW11 + VW12 of the previous uninterruptible power supply UW2, and outputs it to the output terminal TW. Eventually, the total AC voltage VW = VW11 + VW12 + VW13 of the output voltages VW11 to VW13 of the uninterruptible power supply devices UW1 to UW3 is output to the output terminal TW. The AC voltage VW, that is, the W-phase voltage VW is 635 × 3 = 1905V.

  The voltage VU−VV between the terminals TU and TV, that is, the line voltage VUV is 1905 × √3≈3300V. The voltage VV−VW between the terminals TV and TW, that is, the line voltage VVW is 1905 × √3≈3300V. The voltage VW−VU between the terminals TW and TU, that is, the line voltage VWU is 1905 × √3≈3300V. The phases of the line voltages VUV, VVW, VWU are shifted by 120 degrees.

  FIG. 4 is a circuit diagram showing a configuration of uninterruptible power supply UU1. In FIG. 4, the uninterruptible power supply UU1 includes input terminals Ta and Tb, capacitors C1 to C3, reactors L1 and L2, transistors Q1 to Q4, Q11 to Q14, diodes D1 to D4, D11 to D14, a direct current bus PL, DC negative bus NL and output terminals Tc and Td are included.

  The collectors of transistors Q1, Q2, Q11, and Q12 are all connected to DC positive bus PL, and their emitters are connected to the collectors of transistors Q3, Q4, Q13, and Q14, respectively. The emitters of transistors Q3, Q4, Q13, and Q14 are all connected to DC negative bus NL. Diodes D1-D4, D11-D14 are connected in antiparallel to transistors Q1-Q4, Q11-Q14, respectively.

  Transistors Q1-Q4 and diodes D1-D4 constitute a two-level converter 11. Transistors Q11 to Q14 and diodes D11 to D14 constitute a two-level inverter 12. The positive electrode and the negative electrode of battery 8 are connected to DC positive bus PL and DC negative bus NL, respectively. Capacitor C3 is connected between buses PL and NL.

  Reactor L1 is connected between input terminal Ta and the emitter of transistor Q1. One electrode of the capacitor C1 is connected to the input terminal Ta, and the other electrode is connected to the input terminal Tb and the emitter of the transistor Q2. Reactor L1 and capacitor C1 constitute input filter 10.

  Reactor L2 is connected between the emitter of transistor Q11 and output terminal Tc. One electrode of the capacitor C2 is connected to the output terminal Tc, and the other electrode is connected to the emitter of the transistor Q12 and the output terminal Td. Reactor L2 and capacitor C2 constitute output filter 13.

  The input filter 10 is a low-pass filter, and allows the commercial-frequency AC voltage VU1 to pass through the converter 11 and prohibits the switching frequency signal generated by the converter 11 from passing to the input terminals Ta and Tb.

  The converter 11 normally converts the AC power supplied from the corresponding secondary winding CU1 through the input filter 10 into DC power, stores the DC power in the battery 8 and supplies it to the inverter 12 for power failure. The time stops. In other words, converter 11 normally converts AC voltage VU1 supplied from corresponding secondary winding CU1 through input filter 10 into a DC voltage and supplies it between DC positive bus PL and DC negative bus NL. And it stops at the time of power failure.

  For example, when the voltage at the input terminal Ta is higher than the voltage at the input terminal Tb, the transistors Q1 and Q4 are turned on and the transistors Q2 and Q3 are turned off. As a result, a current flows in a path from the input terminal Ta to the input terminal Tb via the reactor L1, the transistor Q1, the capacitor C3, and the transistor Q4, and the capacitor C3 is charged.

  When the voltage at the input terminal Ta is lower than the voltage at the input terminal Tb, the transistors Q1 and Q4 are turned off and the transistors Q2 and Q3 are turned on. As a result, current flows in a path from the input terminal Tb to the input terminal Ta via the transistor Q2, the capacitor C3, and the transistor Q3, and the capacitor C3 is charged. In this way, the AC voltage VU1 between the input terminals Ta and Tb is converted into a DC voltage between the terminals of the capacitor C3.

  Inverter 12 normally converts the DC power generated by converter 11 into AC power, and converts the DC power of battery 8 into AC power during a power failure. In other words, inverter 12 generates a two-level AC voltage including a positive voltage and a negative voltage based on the DC voltage received from DC positive bus PL and DC negative bus NL.

  For example, when transistors Q11 and Q14 are turned on and transistors Q12 and Q13 are turned off, DC positive bus PL is connected to output terminal Tc through transistor Q11 and reactor L2, and DC negative bus NL is passed through transistor Q14. Are connected to the output terminal Td, and a positive voltage is supplied to the output filter 13.

  When transistors Q11 and Q14 are turned off and transistors Q12 and Q13 are turned on, DC positive bus PL is connected to output terminal Td via transistor Q12, and DC negative bus NL is connected to transistor Q13 and reactor L2. Are connected to the output terminal Tc, and a negative voltage is supplied to the output filter 13.

  Therefore, by controlling the transistors Q11 to Q14, a desired voltage of the positive voltage and the negative voltage can be supplied to the output filter 13, and an AC voltage that changes at two levels of the positive voltage and the negative voltage can be supplied to the output filter 13. Can be supplied to.

  The output filter 13 is a low-pass filter, and passes an AC voltage VU11 having a commercial frequency to the output terminals Tc and Td, and prohibits a signal having a switching frequency generated by the inverter 12 from passing to the output terminals Tc and Td. In other words, the output filter 13 converts the waveform of the two-level AC voltage generated by the inverter 12 into a sine wave, and outputs the sine wave AC voltage VU11 between the output terminals Tc and Td.

  Each of the other uninterruptible power supply devices UU2, UU3, UV1 to UV3, UW1 to UW3 is the same as uninterruptible power supply device UU1, and therefore description thereof will not be repeated.

  Returning to FIG. 1, the switches S2 and S3 are connected in series between the output terminal (for example, TU) of the high-voltage uninterruptible power supply 2 and the output terminal T3. The switch S2 is, for example, a contactor, and is turned on when the inverter 12 supplies AC power to the load 6 from the inverter 12, and is turned off when bypass power is supplied from the commercial AC power supply 5 to the load 6 via the bypass terminal T2. The Switch S3 is, for example, a breaker, and is normally turned on and turned off during maintenance of the uninterruptible power supply system. The switch S4 is, for example, a breaker, and is connected between the input terminal T1 and the bypass terminal T2, normally turned off, and when it is desired to short-circuit between the terminals T1 and T2, for example, the commercial AC power supply 4 has failed. 5 is turned on when it is desired to supply AC power to the input transformer 1.

  One terminal of the switch S5 is connected to the bypass terminal T2, and the other terminal is connected to the node N1 between the switches S2 and S3 via the switch S6. The switch S5 is a breaker, for example, and is normally turned on and turned off during maintenance. The switch S6 is a contactor, for example, and is turned on when bypass power is supplied and turned off when power is supplied to the inverter. The switch S7 is connected between the bypass terminal T2 and the output terminal T3, is normally turned off, and is turned on during maintenance. The uninterruptible switch 3 is connected in parallel to the switch S6, and is turned off when the high-voltage uninterruptible power supply 2 is normal, and is turned on instantaneously when the high-voltage uninterruptible power supply 2 fails.

  Next, the operation of this uninterruptible power supply system will be described. However, for simplification of description, only the operation of the portion related to the R phase and the U phase will be described. Normally, the switches S1 to S3 and S5 are turned on, and the switches S4, S6 and S7 are turned off. An AC voltage VR is supplied from the commercial AC power supply 4 to the primary winding CR of the input transformer 1 via the input terminal T1 and the switch S1. As a result, AC voltages VU1 to VU3 are output to the secondary windings CU1 to CU3 of the input transformer 1, respectively.

  Uninterruptible power supply devices UU1 to UU3 are driven by AC voltages VU1 to VU3, respectively, charge three batteries 8 and output sine waveform AC voltages VU11 to VU13, respectively. The AC voltages VU11 to VU13 are added to become a high-voltage AC voltage VU. The high-voltage AC voltage VU is supplied to the load 6 via the switches S2 and S3 and the output terminal T3. This state is called an inverter power supply mode because AC power is supplied from the inverter 12 of the uninterruptible power supply UU1 to UU3 to the load 6.

  When the supply of AC power from the commercial AC power supply 4 is stopped in the inverter power supply mode, that is, when a power failure occurs, the operation of the converter 11 of the uninterruptible power supply devices UU1 to UU3 is stopped and three batteries are used. 8 direct current powers are respectively supplied to the inverters 12 of the uninterruptible power supply units UU1 to UU3. The inverters 12 of the uninterruptible power supply devices UU1 to UU3 each convert DC power from the three batteries 8 into AC power.

  In other words, the uninterruptible power supply devices UU1 to UU3 are each driven by the voltage between the terminals of the three batteries 8 and output AC voltages VU11 to VU13 having sinusoidal waveforms, respectively. The AC voltages VU11 to VU13 are added to become a high-voltage AC voltage VU. The high-voltage AC voltage VU is supplied to the load 6 via the switches S2 and S3 and the output terminal T3. Therefore, even when a power failure occurs, the operation of the load 6 can be continued as long as DC power is stored in the battery 8.

  In the inverter power supply mode, when the high-voltage uninterruptible power supply 2 fails, the uninterruptible switch 3 is turned on instantaneously, and from the commercial AC power source 5, the bypass terminal T2, the switch S5, the uninterruptible switch 3, the switch S3, and AC power is supplied to the load 6 via the output terminal T3, and the operation of the load 6 is continued. When the switch S6 is turned on following the uninterruptible switch 3 and the switches S1 and S2 are turned off, the uninterruptible switch 3 is turned off. Thereby, AC power is supplied from the commercial AC power supply 5 to the load 6 via the bypass terminal T2, the switches S5, S6, S3, and the output terminal T3, and the operation of the load 6 is continued. This is to reduce power loss in the uninterruptible switch 3.

  During maintenance, only the switch S7 is turned on, the other switches S1 to S6 are turned off, and AC power is supplied from the commercial AC power supply 5 to the load 6 via the bypass terminal T2, the switch S7, and the output terminal T3. Is driven. When one of the commercial AC power supplies 4 and 5 fails, the switch S4 is turned on, and the other commercial AC power supply also functions as a commercial AC power supply.

  In the first embodiment, a high voltage is supplied to the load 6 by connecting a plurality of uninterruptible power supply apparatuses (for example, UU1 to UU3) in series to the load 6. Therefore, since no output transformer is used, high efficiency can be obtained.

  In addition, when the output transformer is driven by a low-voltage uninterruptible power supply, an uninterruptible power supply with a large rated current is required. It can consist of a small uninterruptible power supply.

  Further, a plurality of uninterruptible power supply devices (for example, UU1 to UU3) are connected by connecting a plurality of secondary windings (for example, CU1 to CU3) of the input transformer 1 to a plurality of uninterruptible power supply devices (for example, UU1 to UU3), respectively. Since they are insulated from each other, the low breakdown voltage transistor Q, the diode D, the battery 8 and the like can be used, and the cost of the apparatus can be reduced.

  FIG. 5 is a circuit diagram showing a modification of the first embodiment, and is a diagram to be compared with FIG. Referring to FIG. 5, in this modification, each battery 8 is replaced with an electric double layer capacitor 14. Each uninterruptible power supply unit normally stores the generated DC power in the corresponding electric double layer capacitor 14 and converts the DC power of the electric double layer capacitor 14 into AC power during a power failure. In this modified example, since the electric double layer capacitor 14 is used, the life of the device can be extended and the size can be reduced as compared with the case where the battery 8 is used.

  In the first embodiment, a 3.3 KV AC voltage from a commercial AC power source is stepped down to a 635 V AC voltage, a 1905 V phase voltage is generated by a three-stage uninterruptible power supply, and a 3.3 KV line is generated. Although the inter-voltage was regenerated, an even higher voltage uninterruptible power supply system can be constructed by increasing the number of stages of the uninterruptible power supply. For example, even if a 6.6 KV AC voltage from a commercial AC power supply is stepped down to a 635 V AC voltage, a phase voltage of 3810 V is generated by a 6-stage uninterruptible power supply, and a 6.6 KV line voltage is regenerated. Good.

[Embodiment 2]
FIG. 6 is a circuit diagram showing a main part of the uninterruptible power supply system according to Embodiment 2 of the present invention, and is a diagram compared with FIG. Referring to FIG. 6, this uninterruptible power supply system is different from the uninterruptible power supply system of Embodiment 1 in that nine uninterruptible power supply units UU1 to UU3 and UV1 to UV3 included in high-voltage uninterruptible power supply unit 2 are used. , UW1 to UW3 are replaced with uninterruptible power supply devices 20, and each uninterruptible power supply device 20 is provided with two batteries 8, 8A.

  In FIG. 6, the uninterruptible power supply 20 includes transistors Q5 to Q8, Q15 to Q18, diodes D5 to D8, D15 to D18, D21 to D24, D31 to D34, a capacitor C4, and a DC neutrality. A point bus NPL is added.

  Capacitor C3 is connected between DC positive bus PL and DC neutral point bus NPL, and capacitor C4 is connected between DC neutral point bus NPL and DC negative bus NL. The positive electrode and the negative electrode of battery 8 are connected to DC positive bus PL and DC neutral point bus NPL, respectively. The positive electrode and the negative electrode of battery 8A are connected to DC neutral point bus NPL and DC negative bus NL, respectively.

  Transistors Q1, Q5, Q7, and Q3 are connected in series between buses PL and NL, and transistors Q2, Q6, Q8, and Q4 are connected in series between buses PL and NL. The emitter of the transistor Q5 is connected to the input terminal Ta via the reactor L1, and the emitter of the transistor Q6 is connected to the input terminal Tb. Diodes D1-D8 are connected in antiparallel to transistors Q1-Q8, respectively. The anodes of diodes D21 and D22 are both connected to DC neutral point bus NPL, and their cathodes are connected to the collectors of transistors Q5 and Q6, respectively. The anodes of diodes D23 and D24 are connected to the emitters of transistors Q7 and Q8, respectively, and the cathodes thereof are both connected to DC neutral point bus NPL.

  Transistors Q1-Q8 and diodes D1-D8, D21-D24 constitute a three-level converter 11A. The converter 11A normally converts AC power supplied from the corresponding secondary winding via the input filter 10 into DC power, stores the DC power in the batteries 8 and 8A, and supplies the DC power to the inverter 12. Stops during a power failure. In other words, converter 11A normally converts the AC voltage supplied from the corresponding secondary winding via input filter 10 into a positive voltage, a neutral point voltage, and a negative voltage, and each DC positive bus PL Are applied to the DC neutral point bus NLP and the DC negative bus NL, and are stopped during a power failure.

  For example, when the voltage at the input terminal Ta is higher than the voltage at the input terminal Tb, the transistors Q5, Q1, and Q6 among the transistors Q1 to Q8 are turned on. As a result, a current flows from the input terminal Ta to the input terminal Tb through the reactor L1, the transistors Q5 and Q1, the capacitor C3, the diode D22, and the transistor Q6, and the capacitor C3 is charged. Also, transistors Q7, Q4, Q8 among transistors Q1-Q8 are turned on. As a result, a current flows from the input terminal Ta to the input terminal Tb through the reactor L1, the transistor Q7, the diode D23, the capacitor C4, and the transistors Q4 and Q8, and the capacitor C4 is charged.

  When the voltage at the input terminal Ta is lower than the voltage at the input terminal Tb, the transistors Q6, Q2, and Q5 among the transistors Q1 to Q8 are turned on. Thereby, a current flows from the input terminal Tb to the input terminal Ta through the transistors Q6 and Q2, the capacitor C3, the diode D21, the transistor Q5, and the reactor L1, and the capacitor C3 is charged. Also, transistors Q8, Q3, Q7 of transistors Q1-Q8 are turned on. As a result, a current flows from the input terminal Tb to the input terminal Ta through the transistor Q8, the diode D24, the capacitor C4, the transistors Q3 and Q7, and the reactor L1, and the capacitor C4 is charged.

  When the voltages at the input terminals Ta and Tb are substantially equal, only the transistors Q5 and Q8 or the transistors Q6 and Q7 are turned on. When only the transistors Q5 and Q8 are turned on, a current flows from the input terminal Tb to the input terminal Ta via the transistor Q8, the diodes D24 and D21, the transistor Q5, and the reactor L1. When only the transistors Q6 and Q7 are turned on, a current flows from the input terminal Ta to the input terminal Tb via the reactor L1, the transistor Q7, the diodes D23 and D22, and the transistor Q6. In this way, DC positive bus PL, DC neutral point bus NPL, and DC negative bus NL are set to a positive voltage, a neutral point voltage, and a negative voltage, respectively.

  Transistors Q11, Q15, Q17, Q13 are connected in series between buses PL, NL, and transistors Q12, Q16, Q18, Q14 are connected in series between buses PL, NL. The emitter of the transistor Q15 is connected to the output terminal Tc via the reactor L2, and the emitter of the transistor Q16 is connected to the output terminal Td. Diodes D11-D18 are connected in antiparallel to transistors Q11-Q18, respectively. The anodes of diodes D31 and D32 are both connected to DC neutral point bus NPL, and their cathodes are connected to the collectors of transistors Q15 and Q16, respectively. The anodes of diodes D33 and D34 are connected to the emitters of transistors Q17 and Q18, respectively, and the cathodes thereof are both connected to DC neutral point bus NPL.

  Transistors Q11-Q18 and diodes D11-D18, D31-D34 constitute a three-level inverter 12A. Inverter 12A normally converts the DC power generated by converter 11A into AC power, and converts the DC power of batteries 8 and 8A into AC power during a power failure. In other words, inverter 12A has positive voltage, 0V, and negative voltage based on the positive voltage, neutral point voltage, and negative voltage received from DC positive bus PL, DC neutral point bus NPL, and DC negative bus NL. 3 levels of alternating voltage are generated.

  For example, transistors Q11, Q15, Q18 among transistors Q11-Q18 are turned on. Thus, DC positive bus PL is connected to output terminal Tc via transistors Q11 and Q15 and reactor L2, and output terminal Td is connected to DC neutral point bus NPL via transistor Q18 and diode D34. A difference voltage (that is, a positive voltage) between the voltage and the neutral point voltage is supplied to the output filter 13.

  Further, transistors Q15, Q18, Q14 of transistors Q11-Q18 are turned on. Thereby, DC neutral point bus NPL is connected to output terminal Tc via diode D31, transistor Q15, and reactor L2, and output terminal Td is connected to DC negative bus NL via transistors Q18 and Q14. A differential voltage (that is, a positive voltage) between the neutral point voltage and the negative voltage is supplied to the output filter 13.

Of the transistors Q11 to Q18, the transistors Q12, Q16, and Q17 are turned on. Thus, the DC with the positive line PL is connected to the output terminal Td through the transistor Q12, Q16, are connected to a DC neutral point bus NPL via the output terminal Tc is the reactor L2, the transistor Q17 and the diode D 33, A voltage (that is, a negative voltage) between the neutral point voltage and the positive voltage is supplied to the output filter 13.

  Further, transistors Q16, Q17, Q13 among transistors Q11-Q18 are turned on. Thereby, DC neutral point bus NPL is supplied to output terminal Td via diode D32 and transistor Q16, and output terminal Tc is connected to DC negative bus NL via reactor L2 and transistors Q17 and Q13, and negative. A difference voltage (that is, a negative voltage) between the voltage and the neutral point voltage is supplied to the output filter 13.

  Further, only the transistors Q15 and Q18 or the transistors Q16 and Q17 are turned on. When only transistors Q15 and Q18 are turned on, DC neutral point bus NPL is connected to output terminal Tc via diode D31, transistor Q15, and reactor L2, and output terminal Td is connected to transistor Q18 and diode D34. To the DC neutral point bus NPL, and the voltage of the difference between the neutral point voltage and the neutral point voltage (that is, 0 V) is applied to the output filter 13.

  When only transistors Q16 and Q17 are turned on, DC neutral point bus NPL is connected to output terminal Td via diode D32 and transistor Q16, and output terminal Tc is connected to reactor L2, transistor Q17 and diode D33. Is connected to the DC neutral point bus NPL, and the voltage of the difference between the neutral point voltage and the neutral point voltage (that is, 0 V) is applied to the output filter 13.

  Therefore, by controlling the transistors Q11 to Q18, a desired voltage of positive voltage, 0V, and negative voltage can be supplied between the output terminals Tc and Td, and the positive voltage, 0V, and negative voltage 3 can be supplied. An alternating voltage that varies with the level can be generated.

  The output filter 13 is a low-pass filter, and passes an AC voltage having a commercial frequency to the output terminals Tc and Td, and prohibits a signal having a switching frequency generated by the inverter 12A from passing to the output terminals Tc and Td. In other words, the output filter 13 converts the waveform of the three-level AC voltage generated by the inverter 12A into a sine wave and outputs the sine wave AC voltage between the output terminals Tc and Td. Since other configurations and operations are the same as those in the first embodiment, description thereof will not be repeated.

  In the second embodiment, the same effect as in the first embodiment can be obtained, and each uninterruptible power supply generates a three-level AC voltage, so that an AC voltage closer to a sine wave can be output.

  FIG. 7 is a circuit diagram showing a modified example of the second embodiment, and is a diagram to be compared with FIG. Referring to FIG. 6, in this modification, batteries 8 and 8A are replaced with electric double layer capacitors 14 and 14A. Each uninterruptible power supply 20 stores the generated DC power in the corresponding electric double layer capacitors 14 and 14A during normal times, and converts the DC power of the electric double layer capacitors 14 and 14A into AC power during a power failure. In this modified example, since the electric double layer capacitors 14 and 14A are used, the life of the device can be extended and the size can be reduced as compared with the case where the batteries 8 and 8A are used.

[Embodiment 3]
FIG. 8 is a circuit diagram showing the main part of the uninterruptible power supply system according to Embodiment 3 of the present invention, which is compared with FIG. Referring to FIG. 8, this uninterruptible power supply system is different from the uninterruptible power supply system of Embodiment 1 in that nine uninterruptible power supply units UU1 to UU3 and UV1 to UV3 included in high-voltage uninterruptible power supply unit 2 are used. , UW1 to UW3 are each replaced with an uninterruptible power supply 21 and each uninterruptible power supply 21 is provided with two batteries 8 and 8A.

  In FIG. 8, uninterruptible power supply 21 is obtained by adding transistors Q5-Q8, Q15-Q18, diodes D5-D8, D15-D18, capacitor C4, and DC neutral point bus NPL to uninterruptible power supply UU1. is there.

  Capacitor C3 is connected between DC positive bus PL and DC neutral point bus NPL, and capacitor C4 is connected between DC neutral point bus NPL and DC negative bus NL. The positive electrode and the negative electrode of battery 8 are connected to DC positive bus PL and DC neutral point bus NPL, respectively. The positive electrode and the negative electrode of battery 8A are connected to DC neutral point bus NPL and DC negative bus NL, respectively.

  The emitter of transistor Q5 is connected to the emitter of transistor Q1, the collectors of transistors Q5 and Q6 are connected to each other, and the emitter of transistor Q6 is connected to DC neutral point bus NPL. The emitter of transistor Q7 is connected to the emitter of transistor Q2, the collectors of transistors Q7 and Q8 are connected to each other, and the emitter of transistor Q8 is connected to a DC neutral point bus NPL. Diodes D5-D8 are connected in antiparallel to transistors Q5-Q8, respectively.

  The emitter of transistor Q15 is connected to DC neutral point bus NPL, the collectors of transistors Q15 and Q16 are connected to each other, and the emitter of transistor Q16 is connected to the emitter of transistor Q11. The emitter of transistor Q17 is connected to DC neutral point bus NPL, the collectors of transistors Q17 and Q18 are connected to each other, and the emitter of transistor Q18 is connected to the emitter of transistor Q12. Diodes D15-D18 are connected in antiparallel to transistors Q15-Q18, respectively.

  Transistors Q1-Q8 and diodes D1-D8 constitute a three-level converter 11B. The converter 11B normally converts AC power supplied from the corresponding secondary winding via the input filter 10 into DC power, stores the DC power in the batteries 8 and 8A, and supplies the DC power to the inverter 12. Stops during a power failure. In other words, converter 11B normally converts the AC voltage supplied from the corresponding secondary winding through input filter 10 into a positive voltage, a neutral point voltage, and a negative voltage, and each DC positive bus PL Are applied to the DC neutral point bus NPL and the DC negative bus NL, and are stopped during a power failure.

  For example, when the voltage at the input terminal Ta is higher than the voltage at the input terminal Tb, the transistors Q1 and Q7 among the transistors Q1 to Q8 are turned on. As a result, a current flows from the input terminal Ta to the input terminal Tb through the reactor L1, the transistor Q1, the capacitor C3, the diode D8, and the transistor Q7, and the capacitor C3 is charged. Also, transistors Q6 and Q4 among transistors Q1 to Q8 are turned on. As a result, a current flows from the input terminal Ta to the input terminal Tb through the reactor L1, the diode D5, the transistor Q6, the capacitor C4, and the transistor Q4, and the capacitor C4 is charged.

  When the voltage at the input terminal Ta is lower than the voltage at the input terminal Tb, the transistors Q8 and Q3 among the transistors Q1 to Q8 are turned on. As a result, a current flows from the input terminal Tb to the input terminal Ta through the diode D7, the transistor Q8, the capacitor C4, the transistor Q3, and the reactor L1, and the capacitor C4 is charged. Further, the transistors Q2 and Q5 among the transistors Q1 to Q8 are turned on. As a result, a current flows from the input terminal Tb to the input terminal Ta via the transistor Q2, the capacitor C3, the diode D6, the transistor Q5, and the reactor L1, and the capacitor C3 is charged.

  When the voltages at the input terminals Ta and Tb are substantially equal, only the transistors Q5 and Q8 or the transistors Q6 and Q7 are turned on. When only the transistors Q5 and Q8 are turned on, a current flows from the input terminal Tb to the input terminal Ta via the diode D7, the transistor Q8, the diode D6, the transistor Q5, and the reactor L1. When only the transistors Q6 and Q7 are turned on, current flows from the input terminal Ta to the input terminal Tb via the reactor L1, the diode D5, the transistor Q6, the diode D8, and the transistor Q7. In this way, DC positive bus PL, DC neutral point bus NPL, and DC negative bus NL are set to a positive voltage, a neutral point voltage, and a negative voltage, respectively.

  Transistors Q11-Q18 and diodes D11-D18 constitute a three-level inverter 12B. Inverter 12B converts DC power generated by converter 11B into AC power during normal times, and converts DC power of batteries 8 and 8A into AC power during power outages. In other words, inverter 12B has positive voltage, 0V, and negative voltage based on the positive voltage, neutral point voltage, and negative voltage received from DC positive bus PL, DC neutral point bus NPL, and DC negative bus NL. 3 levels of alternating voltage are generated.

  For example, transistors Q11 and Q17 among transistors Q11 to Q18 are turned on. Thus, DC positive bus PL is connected to output terminal Tc via transistor Q11 and reactor L2, and output terminal Td is connected to DC neutral point bus NPL via diode D18 and transistor Q17. A difference voltage (that is, a positive voltage) of the neutral point voltage is supplied to the output filter 13.

  Further, the transistors Q12 and Q15 among the transistors Q11 to Q18 are turned on. As a result, DC positive bus PL is connected to output terminal Td via transistor Q12, and output terminal Tc is connected to DC neutral point bus NPL via diode D16 and transistor Q15. A voltage difference voltage (ie, negative voltage) is applied to the output filter 13.

  Further, the transistors Q16 and Q14 among the transistors Q11 to Q18 are turned on. Thereby, DC neutral point bus NPL is connected to output terminal Tc via diode D15, transistor Q16, and reactor L2, and output terminal Td is connected to DC negative bus NL via transistor Q14. A difference voltage (that is, a positive voltage) between the point voltage and the negative voltage is supplied to the output filter 13.

  Further, transistors Q18 and Q13 among transistors Q11 to Q18 are turned on. Thereby, DC neutral point bus NPL is connected to output terminal Td via diode D17 and transistor Q18, and output terminal Tc is connected to DC negative bus NL via reactor L2 and transistor Q13, and a negative voltage and A difference voltage (that is, a negative voltage) of the neutral point voltage is supplied to the output filter 13.

  Further, only the transistors Q15 and Q18 or the transistors Q16 and Q17 are turned on. When only transistors Q15 and Q18 are turned on, DC neutral point bus NPL is connected to output terminal Td via diode D17 and transistor Q18, and output terminal Tc is connected to reactor L2, diode D16, and transistor Q15. To the DC neutral point bus NPL, and the differential voltage between the neutral point voltage and the neutral point voltage (that is, 0 V) is applied to the output filter 13.

  When only transistors Q16 and Q17 are turned on, DC neutral point bus NPL is connected to output terminal Tc through diode D15, transistor Q16, and reactor L2, and output terminal Td is connected to diode D18 and transistor. Connected to the DC neutral point bus NPL via Q 17, the neutral point voltage and the differential voltage (ie, 0 V) between the neutral point voltage is applied to the output filter 13.

  Therefore, by controlling the transistors Q11 to Q18, a desired voltage of positive voltage, 0V, and negative voltage can be supplied to the output filter 13, and changes at three levels of positive voltage, 0V, and negative voltage. AC voltage can be generated.

  The output filter 13 is a low-pass filter, and passes an AC voltage having a commercial frequency to the output terminals Tc and Td, and prohibits a switching frequency signal generated by the inverter 12B from passing to the output terminals Tc and Td. In other words, the output filter 13 converts the waveform of the three-level AC voltage generated by the inverter 12B into a sine wave and outputs the AC voltage of the sine wave between the output terminals Tc and Td. Since other configurations and operations are the same as those in the first embodiment, description thereof will not be repeated.

  In the third embodiment, the same effect as in the first embodiment can be obtained, and each of the uninterruptible power supply devices generates a three-level AC voltage, so that an AC voltage closer to a sine wave can be output.

  FIG. 9 is a circuit diagram showing a modified example of the third embodiment, and is a diagram to be compared with FIG. Referring to FIG. 9, in this modification, batteries 8 and 8A are replaced with electric double layer capacitors 14 and 14A. Each uninterruptible power supply 21 normally stores the generated DC power in the corresponding electric double layer capacitors 14 and 14A, and converts the DC power of the electric double layer capacitors 14 and 14A into AC power during a power failure. In this modified example, since the electric double layer capacitors 14 and 14A are used, the life of the device can be extended and the size can be reduced as compared with the case where the batteries 8 and 8A are used.

[Embodiment 4]
FIG. 10 is a circuit block diagram showing a configuration of an uninterruptible power supply system according to Embodiment 4 of the present invention, which is compared with FIG. Referring to FIG. 10, this uninterruptible power supply system is different from the uninterruptible power supply system of FIG. 1 in that high voltage uninterruptible power supply 2 is replaced with high voltage uninterruptible power supply 30.

  FIG. 11 is a circuit block diagram showing the configuration of the high-voltage uninterruptible power supply 30, and is a diagram contrasted with FIG. 3. Referring to FIG. 11, this high voltage uninterruptible power supply 30 is different from high voltage uninterruptible power supply 2 in that uninterruptible power supplies UU1 to UU3, UV1 to UV3, UW1 to UW3 are uninterruptible power supplies UU1A to UU3A, It is replaced by UV1A to UV3A, UW1A to UW3A, and reactors LU, LV, and LW and capacitors CU, CV, and CW are added.

  FIG. 12 is a circuit block diagram showing a configuration of uninterruptible power supply UU1A, and is a diagram compared with FIG. Referring to FIG. 12, uninterruptible power supply UU1A is obtained by removing reactors L1, L2 and capacitors C1, C2, that is, input filter 10 and output filter 13, from uninterruptible power supply UU1. The emitter of the transistor Q1 is directly connected to the input terminal Ta, and the emitter of the transistor Q11 is directly connected to the output terminal Tc. For this reason, the output voltage VU11A of the uninterruptible power supply UU1A is not a sine wave but a pulse signal string. Each of other uninterruptible power supply devices UU2A, UU3A, UV1A to UV3A, UW1A to UW3A has the same configuration as uninterruptible power supply UU1A.

  Returning to FIG. 11, a pulse signal sequence obtained by adding the output pulse signal sequences of the uninterruptible power supply devices UU1A to UU3A is output between the output terminal Tc of the uninterruptible power supply device UU3A and the output terminal Td of the uninterruptible power supply device UU1A. Is done. The control circuit 7 controls the inverters 12 of the uninterruptible power supply devices UU1A to UU3A by shifting the phase by a predetermined angle in order to make the waveform of the added pulse signal sequence approach a sine wave. Reactor LU is connected between output terminal Tc and output terminal TU of uninterruptible power supply UU3A, and capacitor CU is connected between output terminal Tc and neutral point NP. Reactor LU and capacitor CU constitute an output filter.

  This output filter is a low-pass filter, which passes an AC voltage of commercial frequency between the output terminal TU and the neutral point NP, and a signal of the switching frequency generated by the inverter 12 passes between the output terminal TU and the neutral point NP. It is prohibited to do. In other words, the output filter including the reactor LU and the capacitor CU converts the output pulse signal sequence of the uninterruptible power supply devices UU1A to UU3A into a sine wave, and converts the sine wave AC voltage VU between the output terminal TU and the neutral point NP. Output.

  Similarly, a pulse signal sequence obtained by adding the output pulse signal sequences of the uninterruptible power supply devices UV1A to UV3A is output between the output terminal Tc of the uninterruptible power supply device UV3A and the output terminal Td of the uninterruptible power supply device UV1A. The control circuit 7 controls the inverter 12 of the uninterruptible power supply devices UV1A to UV3A by shifting the phase by a predetermined angle in order to make the waveform of the added pulse signal sequence approach a sine wave. Reactor LV is connected between output terminal Tc and output terminal TV of uninterruptible power supply UV3A, and capacitor CV is connected between output terminal Tc and neutral point NP. Reactor LV and capacitor CV constitute an output filter.

  This output filter is a low-pass filter, and passes an AC voltage of commercial frequency between the output terminal TV and the neutral point NP, and a signal of the switching frequency generated by the converter 11 passes between the output terminal TV and the neutral point NP. It is prohibited to do. In other words, the output filter including the reactor LV and the capacitor CV converts the output pulse signal sequence of the uninterruptible power supply devices UV1A to UV3A into a sine wave, and converts the AC voltage VV of the sine wave between the output terminal TV and the neutral point NP. Output.

  Similarly, a pulse signal sequence obtained by adding the output pulse signal sequences of the uninterruptible power supply devices UW1A to UW3A is output between the output terminal Tc of the uninterruptible power supply device UW3A and the output terminal Td of the uninterruptible power supply device UW1A. The control circuit 7 controls the inverters 12 of the uninterruptible power supply devices UW1A to UW3A by shifting their phases by a predetermined angle in order to make the waveform of the added pulse signal sequence approach a sine wave. Reactor LW is connected between output terminal Tc and output terminal TW of uninterruptible power supply UW3A, and capacitor CW is connected between output terminal Tc and neutral point NP. Reactor LW and capacitor CW constitute an output filter.

  This output filter is a low-pass filter, and passes an AC voltage of commercial frequency between the output terminal TW and the neutral point NP, and a signal of switching frequency generated by the converter 11 passes between the output terminal TW and the neutral point NP. It is prohibited to do. In other words, the output filter including the reactor LW and the capacitor CW converts the output pulse signal sequence of the uninterruptible power supply devices UW1A to UW3A into a sine wave, and converts the sine wave AC voltage VW between the output terminal TW and the neutral point NP. Output.

  FIGS. 13A to 13D are time charts showing the operation of the portion related to the U phase in the high voltage uninterruptible power supply 2 shown in FIGS. 11 and 12. 13A shows the waveform of the output voltage VU11A of the uninterruptible power supply UU1A, and FIG. 13B shows the waveform of the U-phase voltage VU obtained by adding the output voltages VU11A to VU13A of the uninterruptible power supply UU1A to UU3A. FIG. 13 (c) shows the waveform of the U-phase and V-phase line voltage VUV, and FIG. 13 (d) shows the waveform of the U-phase current IU.

  As shown in FIG. 13 (a), the output voltage VU11A of the uninterruptible power supply UU1A is a positive pulse signal sequence at 0 to 180 degrees and a negative pulse signal sequence at 180 to 360 degrees. The pulse width is maximum near 90 ° and 270 °, which are the peaks of the sine wave, and the pulse width is minimum near 0 ° and 180 °, which is the zero point of the sine wave.

  Further, as shown in FIG. 13B, the waveform of the U-phase voltage VU obtained by adding the output voltages VU11A to VU13A of the uninterruptible power supply devices UU1A to UU3A out of phase is the waveform of the output voltage VU11A of the uninterruptible power supply device UU1A. Is closer to a sine wave. Further, as shown in FIG. 13C, the waveform of the line voltage VUV becomes closer to a sine wave. Further, as shown in FIG. 13 (d), the waveform of the U-phase current IU flowing through the load 6 is substantially a sine wave. Since the operation of the portion related to the V phase and the W phase is the same as the operation of the portion related to the U phase, the description thereof will not be repeated. Other configurations and operations are the same as those in the first embodiment, and thus description thereof will not be repeated.

  In the fourth embodiment, since the output filter is provided in common for the three uninterruptible power supply devices in each phase and the input filter is removed, the circuit area can be reduced.

  FIG. 14 is a circuit diagram showing a modification of the fourth embodiment, and is a diagram contrasted with FIG. Referring to FIG. 14, in this modification, batteries 8 and 8A are replaced with electric double layer capacitors 14 and 14A. Each uninterruptible power supply normally stores the generated DC power in the corresponding electric double layer capacitors 14 and 14A, and converts the DC power of the electric double layer capacitors 14 and 14A into AC power during a power failure. In this modified example, since the electric double layer capacitors 14 and 14A are used, the life of the device can be extended and the size can be reduced as compared with the case where the batteries 8 and 8A are used.

  FIG. 15 is a circuit diagram showing another modification of the fourth embodiment, which is compared with FIG. Referring to FIG. 15, in this modification, each of uninterruptible power supply devices UU1A to UU3A, UV1A to UV3A, UW1A to UW3A is replaced with uninterruptible power supply 31, and battery 8A is added to each uninterruptible power supply 31. Is done. Uninterruptible power supply 31 is obtained by removing reactors L1 and L2 and capacitors C1 and C2, that is, input filter 10 and output filter 13, from uninterruptible power supply 20 of FIG. The emitter of the transistor Q5 is directly connected to the input terminal Ta, and the emitter of the transistor Q15 is directly connected to the output terminal Tc. For this reason, the output voltage of the uninterruptible power supply 31 is not a sine wave but a pulse signal string. The positive electrode and the negative electrode of battery 8 are connected to DC positive bus PL and DC neutral point bus NPL, respectively. The positive electrode and the negative electrode of battery 8A are connected to DC neutral point bus NPL and DC negative bus NL, respectively. Even in this modified example, the same effect as in the fourth embodiment can be obtained.

  FIG. 16 is a circuit diagram showing still another modified example of the fourth embodiment, which is compared with FIG. Referring to FIG. 16, in this modification, batteries 8 and 8A are replaced with electric double layer capacitors 14 and 14A. Each uninterruptible power supply 31 normally stores the generated DC power in the corresponding electric double layer capacitors 14 and 14A, and converts the DC power of the electric double layer capacitors 14 and 14A into AC power during a power failure. In this modified example, since the electric double layer capacitors 14 and 14A are used, the life of the device can be extended and the size can be reduced as compared with the case where the batteries 8 and 8A are used.

  FIG. 17 is a circuit diagram showing still another modification of the fourth embodiment, which is compared with FIG. Referring to FIG. 17, in this modification, each of uninterruptible power supply devices UU1A to UU3A, UV1A to UV3A, UW1A to UW3A is replaced with uninterruptible power supply 32, and battery 8A is added to each uninterruptible power supply 32 Is done. Uninterruptible power supply 32 is obtained by removing reactors L1 and L2 and capacitors C1 and C2, that is, input filter 10 and output filter 13, from uninterruptible power supply 21 in FIG. The emitter of the transistor Q1 is directly connected to the input terminal Ta, and the emitter of the transistor Q11 is directly connected to the output terminal Tc. For this reason, the output voltage of the uninterruptible power supply 32 is not a sine wave but a pulse signal string. The positive electrode and the negative electrode of battery 8 are connected to DC positive bus PL and DC neutral point bus NPL, respectively. The positive electrode and the negative electrode of battery 8A are connected to DC neutral point bus NPL and DC negative bus NL, respectively. Even in this modified example, the same effect as in the fourth embodiment can be obtained.

  FIG. 18 is a circuit diagram showing still another modified example of the fourth embodiment, and is a diagram to be compared with FIG. Referring to FIG. 18, in this modification, batteries 8 and 8A are replaced with electric double layer capacitors 14 and 14A. Each uninterruptible power supply 32 normally stores the generated DC power in the corresponding electric double layer capacitors 14 and 14A, and converts the DC power of the electric double layer capacitors 14 and 14A into AC power during a power failure. In this modified example, since the electric double layer capacitors 14 and 14A are used, the life of the device can be extended and the size can be reduced as compared with the case where the batteries 8 and 8A are used.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  T1, Ta, Tb input terminal, T2 bypass terminal, T3, Tc, Td, TU, TV, TW output terminal, S1 to S7 switch, 1 input transformer, 2,30 high voltage uninterruptible power supply, 3 uninterruptible switch , 4, 5 Commercial AC power supply, 6 loads, CR, CS, CT primary winding, CU1-CU3, CV1-CV3, CW1-CW3 secondary winding, UU1-UU3, UV1-UV3, UW1-UW3 uninterruptible power Power supply device, 7 control circuit, 8, 8A battery, L1, L2, LU, LV, LW reactor, C1-C4, CU, CV, CW capacitor, Q1-Q8, Q11-Q18 transistors, D1-D8, D11-D18 , D21 to D24, D31 to D34 Diode, 10 input filter, 11, 11A, 11B converter, 12, 12A, 12B Invar , 13 output filter, 14, 14A electric double layer capacitor, PL DC positive bus, NPL DC neutral point bus, NL DC negative bus.

Claims (9)

A transformer including a primary winding that receives AC power from a first commercial AC power source and a plurality of secondary windings that are insulated from each other;
A plurality of uninterruptible power supply devices each provided corresponding to the plurality of secondary windings,
Each uninterruptible power supply converts the AC power received from the corresponding secondary winding into DC power during normal times when AC power is normally supplied from the first commercial AC power supply, and the DC power is converted into power. When storing in the storage device and converting to AC power, and during the power failure when the supply of AC power from the first commercial AC power supply is stopped, the DC power of the power storage device is converted to AC power,
The plurality of uninterruptible power supply units are connected in series to a load, and the uninterruptible power supply units at each stage add their own output voltage to the output voltage of the previous stage and output to the next stage. Gives an alternating voltage of the sum of output voltages of the plurality of uninterruptible power supply devices to the load,
Furthermore, one terminal is connected to the second commercial AC power supply, the other terminal is connected to the load, and the plurality of uninterruptible power supply devices become non-conductive in a power supply mode in which an AC voltage is applied to the load. A first switch that conducts when the uninterruptible power supply is faulty ;
One terminal is connected to the first commercial AC power supply, the other terminal is connected to the second commercial AC power supply, and conducts when at least one of the first commercial AC power supply and the second commercial AC power supply fails, An uninterruptible power supply system comprising a second switch that is otherwise non-conductive . Each uninterruptible power supply includes a converter and an inverter,
The converter converts the AC power received from the corresponding secondary winding into DC power in the normal time, stores the DC power in the power storage device and supplies it to the inverter, and stops during the power failure. ,
2. The inverter according to claim 1, wherein the inverter converts the DC power generated by the converter into AC power during the normal time, and converts DC power of the power storage device into AC power during the power outage. Power outage system. The converter generates a DC voltage during the normal time, stops during the power failure,
The uninterruptible power supply system according to claim 2, wherein the inverter generates a two-level AC voltage including a positive voltage and a negative voltage during the normal time and the power failure. The converter generates a positive voltage, a neutral point voltage, and a negative voltage during the normal time, stops during the power failure,
The uninterruptible power supply system according to claim 2, wherein the inverter generates a three-level AC voltage including the positive voltage, 0V, and the negative voltage at the time of the normal time and the power failure.   The uninterruptible power supply system according to any one of claims 1 to 4, wherein the power storage device is a storage battery.   The uninterruptible power supply system according to any one of claims 1 to 4, wherein the power storage device is an electric double layer capacitor. Each uninterruptible power supply further includes a filter circuit that converts the waveform of the output voltage of the inverter into a sine wave,
The uninterruptible power supply system according to any one of claims 2 to 4, wherein output voltages of a plurality of the filter circuits included in the plurality of uninterruptible power supply devices are added and supplied to the load. The output voltages of the plurality of inverters included in the plurality of uninterruptible power supply devices are added,
5. The uninterruptible power supply system according to claim 2, further comprising a filter circuit that converts waveforms of the added output voltages of the plurality of inverters into a sine wave and supplies the sine wave to the load. 6. .   The uninterruptible power supply system according to claim 8, wherein phases of output voltages of the plurality of inverters included in the plurality of uninterruptible power supply apparatuses are sequentially shifted.

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