JP5998804B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion apparatus that performs power conversion by switching an input.

  In recent years, power semiconductor elements such as MOSFETs using wide band gap semiconductors such as SiC (silicon carbide) and GaN (gallium nitride) have been developed, and these are used in inverter circuits for driving motors of compressors such as air conditioners. (For example, refer to Patent Document 1). In an inverter circuit using a wide bandgap semiconductor, a switching frequency exceeding the switching frequency (about 5 kHz) in an inverter circuit using a semiconductor (Si semiconductor) mainly made of Si (silicon) (for example, use limit of Si semiconductor) (Frequency significantly exceeding (about 20 kHz)) can be used. And if switching frequency can be raised in this way, effects, such as reduction of electromagnetic noise and improvement of motor efficiency, are expected.

JP 2011-036020 A

  However, in an inexpensive one-chip microcomputer used for controlling a conventional inverter circuit, it takes about 100 μs for arithmetic processing including PWM modulation (pulse width modulation) and other controls, and the carrier frequency is a maximum of 10 kHz. The degree is the limit. Therefore, expensive parts are required to drive the switching element by PWM modulation at high frequency. Even if expensive parts are used, there is a limit to increasing the switching frequency.

  The present invention has been made paying attention to the above-described problem, and an object of the present invention is to increase the frequency of switching in a power conversion device while suppressing an increase in cost.

In order to solve the above-mentioned problem, the first invention
An inverter circuit (4) for switching a plurality of switching elements (Su, Sv, Sw, Sx, Sy, Sz) on and off to convert direct current into alternating current;
The output voltage command value (Vdc *, Vqc *) of the inverter circuit (4) is obtained at a predetermined control cycle (T) and synchronized with the carrier signal (Ca) having a cycle (Tc) shorter than the control cycle (T). A control unit (5) for generating a pulse corresponding to the output voltage command value (Vdc *, Vqc *) and controlling the on / off;
Equipped with a,
The inverter circuit (4) is configured to output a three-phase alternating current,
The control unit (5) synchronizes the maximum phase and the minimum phase of the three-phase alternating current with a carrier signal (Ca1, Ca2) having a cycle (Tc) shorter than the control cycle (T). The on / off is controlled by dividing v0, v7), and the on / off is controlled in synchronization with the low-speed carrier signal (Ca0) of the control period (T) in the intermediate phase .

In this configuration, the output voltage command values (Vdc *, Vqc *) are obtained with a control cycle (T) longer than the carrier cycle (Tc). On the other hand, switching of each switching element (Su, Sv, Sw, Sx, Sy, Sz) is performed in a carrier cycle (Tc) .

Further, in this configuration, predetermined one-phase switching is performed at a high frequency using three carrier signals.

In addition, the second invention,
In the first power converter,
A shunt resistor (R) that outputs a voltage pulse according to the output current of the inverter circuit (4),
The control unit (5) detects a value of the output current by providing a period in which a width of a voltage pulse in the shunt resistor (R) is secured to a predetermined value or more.

  With this configuration, current detection can be performed in a period in which the width of the voltage pulse is ensured to be equal to or greater than a predetermined value, and switching frequency can be increased.

In addition, the third invention,
The power converter of the first or second aspect of the invention,
The switching element (Su, Sv, Sw, Sx, Sy, Sz) is a semiconductor element whose main material is a wide band gap semiconductor.

According to the first invention, since the output voltage command value (Vdc *, Vqc *) has only to be obtained with a control period (T) longer than the carrier period (Tc), an expensive component (for example, Even without using a microcomputer, it is possible to achieve higher switching frequency by setting the carrier frequency (fc) higher. That is, it is possible to increase the switching frequency while suppressing an increase in cost .

Also, according to the first invention, can be easily frequency by using a three-carrier signal, it is possible to achieve reduction and electromagnetic noise, the up motor efficiency.

Further, according to the second invention, both current detection using the shunt resistor (R) and high frequency switching can be achieved.

In addition, according to the third aspect of the invention, it is possible to easily realize high frequency switching and efficiency.

FIG. 1 is a block diagram showing a configuration of a power conversion device according to the related art of the present invention. FIG. 2 is a flowchart for explaining the operation of the control unit (phase voltage command value calculation flow). FIG. 3 is a flowchart for explaining the operation of the control unit (PWM signal creation flow). 4A is a diagram showing a carrier signal in the related art , FIGS. 4B to 4D are PWM signals to each switching element of the upper arm, and FIG. 4E is a diagram showing the calculation processing time of the phase voltage command calculation flow. is there. FIG. 5 is a flowchart for explaining the operation of the control unit in Modification 1 of the related art . FIG. 6 is a flowchart for explaining the operation of the control unit in Modification 1 of the related art . FIG. 7 is a flowchart for creating a PWM signal in the second modification of the related art . FIG. 8 is a diagram illustrating a carrier signal of the conventional power converter and an output voltage vector corresponding to the switching state of each phase. 9A is a carrier signal in the first embodiment, FIGS. 9B to 9D are PWM signals to the switching elements of the upper arm, and FIG. 9E is a calculation processing time of the phase voltage command value calculation flow. FIG. FIG. 10 is a timing chart for explaining the correction of the phase voltage command value. FIG. 11 is a timing chart for explaining switching of two high-speed carrier signals. 12A is a carrier signal in the second embodiment, FIGS. 12B to 12D are PWM signals to the switching elements of the upper arm, and FIG. 12E is a current waveform in the shunt resistor. FIG. 13 shows a power conversion device in which a shunt resistor is provided for each phase.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following embodiments are essentially preferable examples, and are not intended to limit the scope of the present invention, its application, or its use.

< Related Art of Invention>
<overall structure>
FIG. 1 is a block diagram showing a configuration of a power conversion device (1) according to the related art of the present invention. As shown in the figure, the power conversion device (1) includes a converter circuit (2), a DC link unit (3), an inverter circuit (4), and a control unit (5). From the single-phase AC power source (6) The supplied alternating current is converted into alternating current of a predetermined frequency and supplied to the motor (7). Note that a so-called IPM motor (Interior Permanent Magnet Motor) is adopted as the motor (7) of the related technology . The IPM motor is incorporated in, for example, an electric compressor provided in a refrigerant circuit (not shown) of the air conditioner, and drives a compression mechanism (for example, a scroll compressor).

<Converter circuit (2)>
The converter circuit (2) is connected to the single-phase AC power source (6) via the reactor (L), and full-wave rectifies the output of the single-phase AC power source (6). In this example, the converter circuit (2) is a diode bridge circuit in which four diodes (D1 to D4) are connected in a bridge shape.

<DC link (3)>
The DC link part (3) includes a capacitor (3a). The capacitor (3a) is connected between the output nodes of the converter circuit (2). The capacitor (3a) is connected between the input nodes of the inverter circuit (4), and the DC voltage (DC link voltage (Edc)) generated across the capacitor (3a) is input to the inverter circuit (4). Has been. The capacitor (3a) is constituted by, for example, an electrolytic capacitor or a film capacitor.

<Inverter circuit (4)>
The inverter circuit (4) switches the output of the DC link unit (3) to convert it into a three-phase AC and supplies it to the motor (7). The inverter circuit (4) is configured by a plurality of switching elements (Su, Sv, Sw, Sx, Sy, Sz) being bridge-connected. In this example, each switching element (Su, Sv, Sw, Sx, Sy, Sz) is a switching element whose main material is SiC (silicon carbide).

  Since the inverter circuit (4) outputs three-phase alternating current to the motor (7), the inverter circuit (4) includes six switching elements (Su, Sv, Sw, Sx, Sy, Sz). Specifically, the inverter circuit (4) includes three switching legs in which two switching elements are connected to each other in series. In each switching leg, the midpoint of the upper arm switching elements (Su, Sv, Sw) and the lower arm switching elements (Sx, Sy, Sz) is the coil of each phase of the motor (7) (not shown) It is connected to the. In addition, a free-wheeling diode (D) is connected in antiparallel to each switching element (Su, Sv, Sw, Sx, Sy, Sz).

  The inverter circuit (4) switches the direct current input from the direct current link (3) and converts it into a three-phase alternating current voltage by turning on and off these switching elements (Su, Sv, Sw, Sx, Sy, Sz). To do. The control unit (5) controls this on / off operation.

  A shunt resistor (R) is provided at a position where current from the load (motor (7)) of the inverter circuit (4) flows. In this example, the shunt resistor (R) is provided between the negative node of the DC link unit (3) and the negative node of the inverter circuit (4). When the current from the motor (7) flows through this shunt resistor (R), a voltage difference occurs between both ends of the shunt resistor (R), and the voltage (voltage pulse) between the two ends is detected, and their value and vector are detected. With the pattern, the output current (phase current (Iu, Iv, Iw)) of the inverter circuit (4) can be calculated (reference document: WO2003 / 030348).

<Control part (5)>
The controller (5) controls the switching by a PWM control method in synchronization with the carrier signal (Ca). Specifically, the controller (5) includes a DC voltage detector (51), a phase current detector (52), a coordinate converter (53), a position sensorless controller (54), a speed controller (55), A voltage command calculation unit (56), a phase voltage command calculation unit (57), a carrier generator (58), and a PWM signal generation unit (59) are provided. The main part of the control unit (5) is realized by a microcomputer and a program for operating the microcomputer.

  The DC voltage detection unit (51) detects the voltage of the DC link unit (3) (the voltage (Edc) across the capacitor (3a)).

  The phase current detection unit (52) performs a detection process of the load current (current flowing through the coil of the motor (7)). Specifically, the phase current detector (52) detects the phase current for two phases by detecting the voltage across the shunt resistor (R), and the phase current for three phases from these values and the vector pattern. (Iu, Iv, Iw) (hereinafter also referred to as drive current) is calculated.

  The coordinate conversion unit (53) converts the driving currents (Iu, Iv, Iw) for the three phases calculated by the phase current detection unit (52) into the excitation current component (idc) of the dq coordinate system and the torque current component ( iqc) and coordinate conversion processing to convert.

  The position sensorless control unit (54) performs coordinate conversion on the voltage equation of the motor (7) in the dq coordinate system, and the current rotational speed ω (estimated speed) of the motor (7) and d required for vector control. The axis phase (θdc) is obtained. That is, the position sensorless control unit (54) detects the position of the rotor of the motor (7) without a sensor.

  The speed control unit (55) performs speed control processing for obtaining parameters necessary for speed control. Specifically, the speed control unit (55) generates the torque current command value (iq *) so that the current rotation speed (ω) matches the speed command value (ω *).

  The voltage command calculation unit (56) performs voltage command calculation processing for obtaining a voltage to be applied to the motor (7). Specifically, the voltage command calculation unit (56) includes an external output current command value (id *), a torque current command value (iq *) generated by the speed control unit (55), and a coordinate conversion unit (53). The output voltage command value (Vdc *, Vqc *) in the dq coordinate is obtained on the basis of the dq coordinate current component (idc, iqc) generated by and is given to the phase voltage command calculation unit (57). The output voltage command value (Vdc *, Vqc *) is an example of the output voltage command value of the present invention.

  The phase voltage command calculation unit (57) performs a phase voltage command calculation process for obtaining a phase voltage (referred to as a phase voltage command value) to be output by the inverter circuit (4). Specifically, the phase voltage command calculation unit (57) calculates the phase voltage command value (Vu *, Vv) based on the DC link voltage (Edc), the d-axis phase (θdc), and the output voltage command value (Vdc *, Vqc *). *, Vw *) is obtained and output to the PWM signal generator (59).

  The carrier generator (58) generates a carrier signal (Ca) having a predetermined period. The carrier signal (Ca) is a triangular wave. In this example, the period of the carrier signal (Ca) (carrier period (Tc)) is 20 μs (that is, the carrier frequency (fc) is 50 kHz). The carrier period (Tc) is determined in consideration of the total efficiency of the switching elements (Su, Sv, Sw, Sx, Sy, Sz) and the motor, electromagnetic noise, and the like.

  When the PWM signal generator (59) receives an interrupt synchronized with the carrier signal (Ca) (hereinafter referred to as carrier interrupt), the phase voltage command value (Vu *, Vv *, Vw *) and the carrier signal (Ca) (Triangular wave) to compare on / off signals (Gu, Gv, Gw, Gx, Gy, etc.) for controlling on / off of each switching element (Su, Sv, Sw, Sx, Sy, Sz) of the inverter circuit (4) Gz) (hereinafter also referred to as PWM signal).

<Operation of power converter (1)>
2 and 3 are flowcharts for explaining the operation of the control unit (5). The flow shown in FIG. 3 (hereinafter referred to as PWM signal creation flow) is executed in the carrier cycle (Tc), and the flow shown in FIG. 2 (hereinafter referred to as phase voltage command calculation flow) is longer than the carrier cycle (Tc). It is executed in a cycle (hereinafter, control cycle (T)).

  In the control unit (5), the microcomputer mainly executes the phase voltage command calculation flow, triggered by an interrupt (referred to as a vector control interrupt) by the clock signal of the control cycle (T). On the other hand, the PWM signal creation flow is mainly executed by the microcomputer with the carrier interrupt as a trigger. Although details will be described later, the control cycle (T) is set to 200 μs in consideration of the processing time by the microcomputer.

-Phase voltage command calculation flow-
In the phase voltage command calculation flow, the processing from step S01 to step S06 is performed by the control unit (5), and phase voltage command values (Vu *, Vv *, Vw *) are obtained.

  First, in step S01, the phase current detector (52) detects the drive current (Iu, Iv, Iw), and the coordinate converter (53) reads it.

  In step S02, the coordinate conversion unit (53) performs the coordinate conversion process to obtain an excitation current component (idc) and a torque current component (iqc). The process in step S02 is a relatively heavy process for the microcomputer.

  In step S03, the voltage command calculation unit (56) reads the output current command value (id *) and the torque current command value (iq *). The torque current command value (iq *) is generated by the speed control unit (55) performing the speed control process. This speed control process is a process with a relatively large load for a general microcomputer.

  In step S04, the voltage command calculation unit (56) performs the voltage command calculation process. Specifically, the voltage command calculation unit (56) outputs the output current command value (id *) from the outside, the torque current command value (iq *) read in step S03, and the d generated by the coordinate conversion unit (53). Based on the -q coordinate current component (idc, iqc), the output voltage command value (Vdc *, Vqc *) is obtained. The voltage command calculation unit (56) outputs the output voltage command value (Vdc *, Vqc *) to the phase voltage command calculation unit (57).

  In step S05, the DC voltage (Edc) detected by the DC voltage detector (51) and the d-axis phase (θdc) obtained by the position sensorless controller (54) are read by the phase voltage command calculator (57).

In step S06, the phase voltage command calculation unit (57) determines the phase voltage command value (Vu) based on the DC link voltage (Edc), the d-axis phase (θdc), and the output voltage command value (Vdc *, Vqc *). *, Vv *, Vw *) is obtained and output to the PWM signal generator (59). As described above, in the related technique , in the control cycle (T), in the control unit (5), the position control process, the load current detection process, the coordinate conversion process, the speed control process, the voltage command calculation process, the phase voltage The command calculation process is executed.

-PWM signal creation flow-
In the PWM signal creation flow, the processing from step S11 to step S13 is performed by the control unit (5), and PWM signals (Gu, Gv, Gw, Gx, Gy, Gz) are generated. The process of the PWM signal creation flow is executed by the PWM signal generator (59).

  In step S11, the PWM signal generator (59) reads the phase voltage command values (Vu *, Vv *, Vw *). In step S12, the PWM signal generation unit (59) compares the phase voltage command value (Vu *, Vv *, Vw *) with the carrier signal (Ca) to determine the PWM signal (Gu, Gv, Gw). , Gx, Gy, Gz) pulse widths (tu, tv, tw, tx, ty, tz) are calculated.

4A shows a carrier signal (Ca) in the related art , FIGS. 4B to 4D show PWM signals (Gu, Gv, Gw) to the switching elements (Su, Sv, Sw) of the upper arm, (E) is a figure which shows the calculation processing time of a phase voltage command calculation flow. In FIG. 4A, the phase voltage command values (Vu *, Vv *, Vw *) for each phase are also displayed together with the carrier signal (Ca). FIG. 4E schematically shows the calculation processing time, and the signal width in FIG. 4 does not correspond to the actual processing time.

  For example, when the processing in step S12 is performed on the U-phase switching element (Su), the PWM signal generation unit (59) compares the magnitude of the phase voltage command value (Vu *) with the magnitude of the carrier signal (Ca). The PWM signal generator (59) turns on the switching element (Su) during a period when the phase voltage command value (Vu *) is higher than the carrier signal (Ca), and the phase voltage command value (Vu *) The pulse width (tu) in the carrier cycle (Tc) is calculated so that the switching element (Su) is turned off during the period when the level is lower than the carrier signal (Ca). Similarly, the PWM signal generator (59) calculates the pulse width (tv, tw) for the V phase and the W phase. During the period when the upper arm switching elements (Su, Sv, Sw) are on, the lower arm switching elements (Sx, Sy, Sz) are controlled to be off, so the upper arm switching elements (Su, Sv, If the pulse width (tu, tv, tw) for Sw) is determined, the pulse width (tx, ty, tz) for the lower arm switching elements (Sx, Sy, Sz) can also be determined. The pulse width (tu, tv, tw, tx, ty, tz) determined in this way becomes a pulse train having an equal width within one control cycle (T) (see FIG. 4).

In step S13, the PWM signal generator (59) outputs a PWM signal (Gu, Gv, Gw, Gx, Gy, Gz) corresponding to the obtained pulse width (tu, tv, tw, tx, ty, tz). Is output to the inverter circuit (4). In this related technology , the pulse width (tu, tv, tw, tx, ty, tz) is calculated for each carrier cycle (Tc), so the output voltage command value (Vdc *, Vqc *) is the voltage command. When updated by the calculation unit (56), it can be immediately reflected.

  As described above, the control unit (5) obtains the output voltage command value (Vdc *, Vqc *) of the inverter circuit (4) at a predetermined control cycle (T), and has a cycle shorter than the control cycle (T) ( In synchronization with the carrier signal (Ca) of Tc), a pulse (PWM signal (Gu, Gv, Gw), etc.) corresponding to the output voltage command value (Vdc *, Vqc *) is generated, and each switching element (Su, Sv, Sw, Sx, Sy, Sz) are controlled. Thereby, in the inverter circuit (4), the switching state of each switching element (Su, Sv, Sw, Sx, Sy, Sz) is controlled, and alternating current of a predetermined voltage and frequency is output from the inverter circuit (4). .

-Control cycle (T) setting-
In this related technique , the control cycle (T) is determined so that the output voltage vector calculation flow can be reliably processed while the PWM signal creation flow is performed in the carrier cycle (Tc).

  If the execution times of the output voltage vector calculation flow (steps S01 to S06) and the PWM signal generation flow (steps S11 to S13) by the microcomputer are t1 and t2 (where t2 <Tc), respectively, one carrier period In addition, the time that the microcomputer can be allocated for the output voltage vector calculation flow is Tc-t2. Therefore, the number of carrier cycles necessary to complete the output voltage vector calculation flow is t1 / (Tc−t2). For example, if t1 = 90 μs, t2 = 10 μs (that is, total calculation time 100 μs), and Tc = 20 μs, it is necessary to ensure 90 / (20−10) = 9 carrier periods or more as the control period (T). Therefore, as the control cycle (T), it is conceivable to provide a margin and secure, for example, 10 carrier cycles to 200 μs. Of course, the value of the control cycle (T) is an example, and may be changed as appropriate, such as providing a margin. If T = 200 μs and Tc = 20 μs, 10 carrier periods (Tc) are included in one control period. In FIG. 4, an example different from this calculation (carrier signal (Ca for 6 periods) ) Shows an example) included in the control cycle. Of course, depending on the specifications of the power conversion device (1), as shown in FIG. 4, the control cycle (T) may be six times the carrier cycle (Tc).

<Effects of this related technology >
In FIG. 4A, a carrier signal of a conventional power conversion device is also shown for reference. In a conventional power conversion device, processing corresponding to both processing of the output voltage vector calculation flow and the PWM signal creation flow is performed in one carrier cycle. Therefore, in the conventional power conversion device, if the control period and the carrier period coincide, for example, if a microcomputer that takes 100 μs for the total execution time of both the output voltage vector calculation flow and the PWM signal creation flow is used, In the power converter, it is difficult to increase the carrier frequency (fc) as in the related art .

On the other hand, in the power conversion device (1) of the related technology , the output voltage command value (Vdc *, Vqc *) may be obtained with a control cycle (T) longer than the carrier cycle (Tc). Specifically, the processing in the control unit (5) is performed every carrier cycle (Tc) (PWM signal creation flow), and control longer than the carrier cycle (Tc) over a plurality of carrier cycles (Tc) The inverter circuit (4) is controlled separately from the processing (output voltage vector calculation flow) performed in the cycle (T). As a result, this related technology achieves higher switching frequency by setting the carrier frequency (fc) higher than the carrier frequency of conventional power converters without using an expensive microcomputer for the control unit (5). It becomes possible to do. That is, according to the related technology , it is possible to increase the frequency of switching while suppressing an increase in cost.

  Further, the high frequency of switching enables precise waveform control of the output of the inverter circuit (4), thereby reducing electromagnetic noise and increasing motor efficiency.

In this related technique , once the output voltage command value (Vdc *, Vqc *) is determined, this value is not updated during the control cycle (T). Therefore, the pulse width (tu, tv, tw, tx, ty, tz) is calculated only once and the pulse width (calculated once) is calculated for a certain period (the same time as the control cycle (T)). The control unit (5) is configured to output PWM signals (Gu, Gv, Gw, Gx, Gy, Gz) at every carrier cycle (Tc) using tu, tv, tw, tx, ty, tz) May be.

<< Modification 1 of Related Technology >>
The classification of the process performed by the control unit (5) within one carrier cycle (Tc) and the process performed across a plurality of carrier cycles (Tc) is not limited to the related art example. 5 and 6 are flowcharts for explaining the operation of the control unit (5) in Modification 1 of the related art . Specifically, FIG. 5 is a flowchart illustrating another example of processing performed over a plurality of carrier periods (Tc). FIG. 6 is a flowchart showing another example of processing completed within one carrier cycle (Tc). These processes are also performed by the control unit (5).

The process shown in FIG. 5 (hereinafter referred to as an output voltage command calculation flow) is obtained by extracting the processes from step S01 to step S04 in the phase voltage command calculation flow shown in FIG. In the flow shown in FIG. 6 (hereinafter referred to as the PWM signal creation flow), the phase voltage command calculation unit (57) converts the output voltage command value (Vdc *, Vqc *) into the voltage command calculation unit (56) in step S21. ), The control unit (5) executes the above-described steps S05 to S06 (see FIG. 2) and the above-described steps S12 to S13 (see FIG. 3). That is, in this modification, the processes of steps S05 to S06 described in the related art are performed within the carrier cycle (Tc).

In this case as well, similar to the related art , the control period (T) may be determined by estimating in advance the time required to complete the output voltage command calculation flow. In addition, since the processing of steps S05 to S06 is performed within the carrier cycle (Tc), the execution time of the processing (output voltage command calculation flow in this related technology ) itself that spans a plurality of carrier cycles (Tc) Becomes shorter. Further, the time that can be allocated to the output voltage command calculation flow within one carrier period is shorter than that of the related art .

<< Modification 2 of Related Technology >>
The pulse train in the control period (T) does not need to be equal in width as described above. FIG. 7 is a flowchart for creating a PWM signal in the second modification of the related art . The PWM signal creation flow of this modification is obtained by adding steps S31 and S32 between steps S12 and S13 in the PWM signal creation flow of the related art . These processes are also performed by the control unit (5).

  In step S31, the PWM signal generator (59) reads the d-axis phase (θdc). The d-axis phase (θdc) is obtained by the position sensorless control unit (54). In step S32, the PWM signal generator (59) is configured so that the output current (phase current (Iu, Iv, Iw)) of the inverter circuit (4) becomes a sine wave based on the d-axis phase (θdc). Correction pulse widths (tu (n), tv (n), tw (n), tx (n), ty () obtained by correcting the pulse widths (tu, tv, tw, tx, ty, tz) calculated in step S12 n), tz (n)). Since this correction is performed in the carrier cycle (Tc), the pulse trains in the control cycle (T) have unequal widths.

The PWM signal generation unit (59) generates a PWM signal (Gu) according to the correction pulse width (tu (n), tv (n), tw (n), tx (n), ty (n), tz (n))). , Gv, Gw, Gx, Gy, Gz) are output to the inverter circuit (4). Thereby, in the inverter circuit (4), the switching state of each switching element (Su, Sv, Sw, Sx, Sy, Sz) is controlled, and alternating current of a predetermined voltage and frequency is output from the inverter circuit (4). . In this related technology , the phase current (Iu, Iv, Iw) is made close to a sine wave by the correction, so that electromagnetic noise can be reduced and motor efficiency can be improved more effectively.

Embodiment 1 of the Invention
Power conversion apparatus of Embodiment 1 of the present invention (1) performs power conversion by sequentially switching the phase for switching the high frequency. A predetermined one phase (the maximum phase or the minimum phase described later) is switched at a higher speed.

  For reference, FIG. 8 shows a carrier signal of a conventional power converter and an output voltage vector corresponding to the switching state of each phase. The switching state of each switching element (Su, Sv, Sw, Sx, Sy, Sz) is v0 (000), v1 (001), v2 (010), v3 (011), v4 (100), v5 (101). , V6 (110), and v7 (111). v0 and v7 are zero vectors. For example, v1 (001) indicates that the switching element (Su) for only the W phase is on in the upper arm. Similarly, v2 indicates that the V-phase upper arm switching element (Sv) is on, and v3 indicates that the W-phase and V-phase upper arm switching elements (Su, Sv) are on. ing. Further, v0 (000) indicates that all switching elements (Su, Sv, Sw) of the upper arm are off, and v7 (111) indicates all switching elements (Su, Sv, Sw) of the upper arm. Is on. In the example of FIG. 8, switching is performed in a pattern of v7 → v6 → v4 → v0 → v4 → v6 → v7. Note that the period of the carrier signal of the conventional power converter is 200 μs (that is, the carrier frequency = 5 kHz).

  In the conventional modulation system, a zero vector appears according to the comparison result of the command value and the carrier signal for the phase with the maximum output voltage (maximum phase) and the phase with the minimum output voltage (minimum phase). A region where the signal exceeds the maximum phase appears as v0, and a region where the signal is smaller than the minimum phase appears as v7 (see FIG. 8). In the output voltage vector control, only v7 appears if the maximum phase is the maximum value of the carrier signal, and only v0 appears if the minimum phase is the minimum value of the carrier signal.

  When considering the realization of the zero vector by high frequency switching, vectors other than the main and sub vectors (two vectors adjacent to the vector command in the space vector control) appear depending on how v0 and v7 are used. There is. If a vector other than the main sub-vector appears, the current waveform may be distorted and the motor loss may increase. Therefore, in this embodiment, two of the three phases output from the inverter circuit (4) are modulated with a high-speed carrier signal to perform zero vector switching, and the remaining one phase is modulated with a slower carrier signal. This prevents the occurrence of vectors other than the main and sub vectors.

  Specifically, v7 is used as the output voltage vector for a predetermined period before the intermediate phase (described later) switches from on to off, and v0 is used as the output voltage vector for a predetermined period after switching. In order to realize this, in the present embodiment, the command value for the maximum phase and the output voltage vector for the minimum phase are corrected. This control is realized by the control unit (5). Hereinafter, a specific configuration example of the control unit (5) will be described.

<Configuration of control unit and the like in this embodiment>
In this embodiment, the carrier generator (58) includes a carrier signal having the same cycle as the control cycle (T) (hereinafter referred to as a low-speed carrier signal (Ca0)) and two cycles shorter than the control cycle (T). A carrier signal (hereinafter referred to as a high-speed carrier signal (Ca1, Ca2)) is generated. Then, the control unit (5) corrects the phase voltage command value for the maximum phase to be the maximum value of the high-speed carrier signal (Ca1, Ca2), and the output voltage vector for the minimum phase is the high-speed carrier signal (Ca1, Ca2). Correct to the minimum value of Ca2). Note that which of the two high-speed carrier signals (Ca1, Ca2) is used will be described later.

9A shows carrier signals (Ca0, Ca1, Ca2) in the first embodiment, and FIGS. 9B to 9D show PWM signals (Gu,) to the switching elements (Su, Sv, Sw) of the upper arm. (Gv, Gw) and (E) are diagrams showing the calculation processing time of the phase voltage command calculation flow. The low-speed carrier signal (Ca0) is a triangular wave (with an amplitude of 1) as shown in FIG. In the present embodiment, the cycle of the low-speed carrier signal (Ca0), that is, the control cycle (T) is, for example, 200 μs, which is the same as the carrier cycle of the conventional power converter. On the other hand, each of the high-speed carrier signals (Ca1, Ca2) has a frequency six times that of the low-speed carrier signal (Ca0) and is a triangular wave (with an amplitude of 1), as shown in FIG. Also, one high-speed carrier signal (Ca1) and the other high-speed carrier signal (Ca2) are 180 degrees out of phase.

  Then, the control unit (5) obtains the PWM signal (Gu, Gv, Gw, Gx, Gy, Gz) by comparison with one high-speed carrier signal (Ca1, Ca2) for the maximum phase, and for the minimum phase The PWM signal (Gu, Gv, Gw, Gx, Gy, Gz) is obtained by comparison with the other high-speed carrier signal (Ca1, Ca2).

  Thus, in the period (A) shown in FIG. 9, the zero vector v7 when switching in synchronization with the conventional low-speed carrier signal (Ca0) is performed by comparing with the high-speed carrier signals (Ca1, Ca2). Can be switched in a pattern of v6 → v7 → v6 → v7 → v6 → v7 → v6 (in the example of FIG. 8, switching is performed in the pattern of v6 → v7 → v6). ).

  Further, in the period (B) shown in FIG. 9, the zero vector v0 when switching in synchronization with the conventional low-speed carrier signal (Ca0) is performed by comparing with the high-speed carrier signals (Ca1, Ca2). Switching can be performed in the pattern of v4.fwdarw.v0.fwdarw.v4.fwdarw.v4.fwdarw.v0.fwdarw.v4 divided into a plurality (in the example of FIG. 8, switching is performed in the pattern of v4.fwdarw.v0.fwdarw.v4). .

  For the phases other than the maximum phase and the minimum phase (intermediate phase), PWM signals (Gu, Gv, Gw, Gx, Gy, Gz) are obtained by comparison with the low-speed carrier signal (Ca0). That is, in this embodiment, the output of the inverter circuit (4) includes a phase in which switching is performed in synchronization with the low-speed carrier signal (Ca0) and switching (high-speed switching) in synchronization with the high-speed carrier signal (Ca1, Ca2). There is a phase to be done.

  FIG. 10 is a timing chart for explaining the correction of the output voltage vector. In FIG. 10, the phase voltage command values (Vu *, Vv *, Vw *) of each phase are displayed together with the three carrier signals (Ca0, Ca1, Ca2). The correction timing of the phase voltage command values (Vu *, Vv *, Vw *) is determined as follows.

  The period in which the maximum phase is the maximum value of the high-speed carrier signal (Ca1, Ca2) is T1, the period in which the minimum phase is the minimum value of the high-speed carrier signal (Ca1, Ca2) is T2, and 1/2 of the low-speed carrier signal (Ca0) When the period is T3 and the modulation factor (see FIG. 10) is δ, the correction amount (Δ) can be expressed by the following equation.

Δ = T1 (1-δ) / T3
The intermediate phase voltage (V ′) is V ′ = V + Δ ′, which is a value (Δ ′) deviated from a value determined from the phase voltage command value (Vu *, Vv *, Vw *). Also, T1 = V′T.

  Therefore, Δ = V′T3 (1-δ) / T3 = V ′ (1-δ). Since all three phases need to be shifted by the same amount, Δ ′ = Δ = V ′ (1−δ).

Therefore,
V '= V + Δ' = V + V '(1-δ)
V-V'δ = 0
∴ V '= V / δ
Therefore, the voltage of the intermediate phase is set to V / δ, and the timing for shifting the maximum phase and the minimum phase is set simultaneously with the switching timing of the intermediate phase.

  As shown in FIG. 10, the period before the intermediate phase (V phase in the example of FIG. 10) switches from on to off in one cycle of the low-speed carrier signal (Ca0) (for example, period (A) in FIG. 9) ) Increases the phase voltage command value (Vu *) for the maximum phase (U phase in the example of FIG. 10) by Δ (described above), and the period during which the intermediate phase is off (period (B) in FIG. 9) Decrease the phase voltage command value (Vu *) for the phase by Δ (described above). Similarly, even in the minimum phase (W phase in the example of FIG. 10), the period before the intermediate phase switches from on to off in one cycle of the low-speed carrier signal (Ca0) is the phase voltage command value (Vw * ) Is increased by Δ, and the phase voltage command value (Vw *) is decreased by Δ during the period in which the intermediate phase is off.

  In the present embodiment, the high-speed carrier signal (Ca1, Ca2) is a triangular wave whose phase is 180 degrees different from each other (or may be equivalent to it), and then the maximum-phase high-speed carrier signal and the minimum-phase carrier signal are used. The high-speed carrier signal is switched at the intermediate phase switching timing. As shown in FIG. 10, when the carrier signal (Ca0, Ca1, Ca2) is a triangular wave, v0 is output before and after the maximum value of the triangular wave, and v7 is output before and after the minimum value of the triangular wave. Therefore, in order to output zero vectors uniformly, it is preferable to use at least two triangular waves (phases that differ by 180 degrees) or equivalents.

  In the present embodiment, when correcting the phase voltage command values (Vu *, Vv *, Vw *) at the switching timing (t1, t2) of the intermediate phase, the zero phase vector is output correctly. The high-speed carrier signal and the high-speed carrier signal for the minimum phase are switched to those having a phase difference of 180 degrees. FIG. 11 is a timing chart for explaining switching of two high-speed carrier signals (Ca1, Ca2). In FIG. 11, the low-speed carrier signal (Ca0) is not shown.

  In FIG. 11, a high-speed carrier signal indicated by a thick line is a selected signal. For example, the high-speed carrier signal (Ca1) is selected before the switching timing (t1), and the high-speed carrier signal (Ca2) is selected between the switching timing (t1) and the switching timing (t2). As a result, the power conversion device (1) can output zero vectors equally without outputting vectors other than the main and sub vectors. Even if the output voltage command V ′ for the intermediate phase is switched to the maximum value or the minimum value of the high-speed carrier signal after the switching timing (t1, t2), the average value of the carrier signal can be made to match V ′. it can.

<Effect in this embodiment>
In the power conversion device (1) of the present embodiment, the processing in the control unit (5) is performed for each high-speed carrier signal (Ca1), and the control cycle (T) is longer than that of the high-speed carrier signals (Ca1, Ca2). It is divided into processing to be performed (output voltage vector calculation flow), and high-speed switching is performed in any one phase. Since the frequency is increased using the three carrier signals, the control is easy.

As described above, even in this embodiment, even if an expensive microcomputer is not used for the control unit (5), the carrier frequency (fc) is set to be higher than the carrier frequency of the conventional power converter and the switching frequency is increased. Can be realized. Therefore, the present embodiment can achieve the same effects as the related art . Further, since vectors other than the main / sub-vector can be prevented from appearing, the distortion of the current waveform can be suppressed and the motor loss can be reduced.

<< Embodiment 2 of the Invention >>
As in the related art and the first embodiment, when the switching frequency becomes higher, the width of the voltage pulse in the shunt resistor (R) becomes narrower, and current detection of the inverter circuit (4) becomes difficult. If a plurality of expensive current detection transformers (DC-CT) are employed in the alternating current output unit in order to reliably detect the current, the cost of the power converter increases.

Therefore, in this embodiment, by changing the control unit (5) of the power conversion apparatus of Embodiment 1 (1), about once the control period (T) in a certain or more pulse width (tu, tv, tw, A current detection period for securing tx, ty, tz) is provided. In FIG. 12, (A) is the carrier signal (Ca) in the second embodiment, and (B) to (D) are the PWM signals (Gu, Gv, Gw) to the switching elements (Su, Sv, Sw) of the upper arm. , (E) are current waveforms in the shunt resistor (R).

  In the example shown in FIG. 12, the carrier period (Tc) of the high-speed carrier signal (Ca1, Ca2) is extended by the carrier generator (58) only once in the control period (T). In the period in which the carrier cycle (Tc) is extended, as shown in FIG. 12, the on-time of the switching elements (Su, Sv, Sw, Sx, Sy, Sz) becomes long, and the current detection period can be secured. It becomes possible. Therefore, in this embodiment, it is possible to achieve both current detection using a shunt resistor (R) and high frequency switching.

  The shunt resistance (R) may be provided for each phase as shown in FIG. In this example, a detection unit (60) is provided corresponding to each shunt resistor (R), and each phase voltage (Vu, Vv, Vw) is detected by the detection unit (60) to the control unit (5). Output. In the control unit (5), the coordinate conversion unit (53) uses the output of each detection unit (60). Even in this configuration, by extending the carrier cycle (Tc) at a predetermined timing, the ON time of the switching elements (Su, Sv, Sw, Sx, Sy, Sz) can be lengthened, and a current detection period can be secured. Become.

  A plurality of current detection periods may be provided within the control cycle (T).

<< Other Embodiments >>
<1> The position control process and the speed control process are not necessarily executed in synchronization with the vector control interrupt. For example, it may be executed at a cycle longer than the control cycle (T).

  <2> Further, SiC employed as the switching element (Su, Sv, Sw, Sx, Sy, Sz) is an example, and in addition, for example, the switching element (Su, Sv, Sw, Sx, Sy, Sz) may be adopted.

  The present invention is useful as a power conversion device that performs power conversion by switching an input.

1 Power converter 4 Inverter circuit 5 Control unit

Claims (3)

An inverter circuit (4) for switching a plurality of switching elements (Su, Sv, Sw, Sx, Sy, Sz) on and off to convert direct current into alternating current;
The output voltage command value (Vdc *, Vqc *) of the inverter circuit (4) is obtained at a predetermined control cycle (T) and synchronized with the carrier signal (Ca) having a cycle (Tc) shorter than the control cycle (T). A control unit (5) for generating a pulse corresponding to the output voltage command value (Vdc *, Vqc *) and controlling the on / off;
Equipped with a,
The inverter circuit (4) is configured to output a three-phase alternating current,
The control unit (5) synchronizes the maximum phase and the minimum phase of the three-phase alternating current with a carrier signal (Ca1, Ca2) having a cycle (Tc) shorter than the control cycle (T). v0, v7) is divided to control the on / off, and the on / off is controlled in synchronization with the low-speed carrier signal (Ca0) of the control period (T) in the intermediate phase . In the power converter device of Claim 1 ,
A shunt resistor (R) that outputs a voltage pulse according to the output current of the inverter circuit (4),
The said control part (5) provides the period which ensured the width | variety of the voltage pulse in the said shunt resistance (R) more than predetermined, and detects the value of the said output current, The power converter device characterized by the above-mentioned. In the power converter of Claim 1 or Claim 2 ,
The switching element (Su, Sv, Sw, Sx, Sy, Sz) is a semiconductor element whose main material is a wide band gap semiconductor.

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