JP5813678B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5813678B2
JP5813678B2 JP2013027925A JP2013027925A JP5813678B2 JP 5813678 B2 JP5813678 B2 JP 5813678B2 JP 2013027925 A JP2013027925 A JP 2013027925A JP 2013027925 A JP2013027925 A JP 2013027925A JP 5813678 B2 JP5813678 B2 JP 5813678B2
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multilayer graphene
layer
wiring
graphene wiring
contact
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JP2014157923A (en
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和田　真
真 和田
久生 宮崎
久生 宮崎
明広 梶田
明広 梶田
厚伸 磯林
厚伸 磯林
達朗 斎藤
達朗 斎藤
酒井　忠司
忠司 酒井
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Toshiba Corp
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
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Description

本発明の実施形態は、多層グラフェン配線を用いた半導体装置に関する。   Embodiments described herein relate generally to a semiconductor device using multilayer graphene wiring.

近年、金属配線に替わるものとして、グラフェンを用いたグラフェン配線が注目されている。グラフェンは、グラファイトを極めて薄くした新規炭素材料であり、カーボンナノチューブと同様に量子化伝導特性（バリステック伝導特性）を有し量子化伝導をするので、長距離配線の電気伝導により有利である。さらに、グラフェンの構造自体が極薄膜であり、ＣＶＤ法にて成膜することが可能であることから、デバイス配線形成プロセスに対して優れた整合性を有している。   In recent years, graphene wiring using graphene has attracted attention as an alternative to metal wiring. Graphene is a novel carbon material in which graphite is extremely thin, and has quantized conduction characteristics (ballistic conduction characteristics) like carbon nanotubes and conducts quantized conduction, so it is more advantageous for electrical conduction of long-distance wiring. Furthermore, since the graphene structure itself is an extremely thin film and can be formed by a CVD method, it has excellent consistency with the device wiring formation process.

ＬＳＩ配線構造にグラフェンを適用する際に、グラフェン層を多層に積層した多層グラフェン構造として用いる。この多層グラフェン構造の更なる低抵抗化の方法として、グラフェン層間中への他元素添加技術が有力である。グラフェン層間に例えばＢｒなどの元素を添加することにより、グラフェンシート中のキャリア（電子又は正孔）の移動度を上昇させて、より低抵抗化をはかることができる。   When graphene is applied to an LSI wiring structure, it is used as a multilayer graphene structure in which graphene layers are stacked in multiple layers. As a method for further reducing the resistance of the multilayer graphene structure, a technique for adding other elements into the graphene layer is effective. By adding an element such as Br between the graphene layers, the mobility of carriers (electrons or holes) in the graphene sheet can be increased to further reduce the resistance.

しかしながら、添加元素の有力候補であるＢｒ等は、ＬＳＩ配線のビア材料として代表されるＷやＴｉの金属材料と反応し、金属材料をエッチング・腐食する可能性がある。特に、多層グラフェン配線に直接コンタクトされる、グラフェン配線の上層側コンタクトで問題が顕在となる。   However, Br or the like, which is a promising candidate for an additive element, may react with a metal material such as W or Ti typified as a via material for LSI wiring, and may etch and corrode the metal material. In particular, the problem becomes obvious in the upper layer side contact of the graphene wiring that is directly contacted with the multilayer graphene wiring.

特開２０１２−６４７８４号公報JP 2012-64784 A 特開２０１２−５４３０３号公報JP 2012-54303 A

発明が解決しようとする課題は、金属材料のエッチングや腐食を招くことなく、グラフェン配線の低抵抗化をはかることができ、素子特性の向上に寄与し得る半導体装置を提供することである。   The problem to be solved by the present invention is to provide a semiconductor device that can reduce the resistance of graphene wiring without causing etching or corrosion of a metal material and can contribute to improvement of element characteristics.

実施形態の半導体装置は、半導体素子が形成された基板と、前記基板の上方に形成され、所定の不純物がドーピングされた多層グラフェン層を含む第１の多層グラフェン配線と、前記基板の上方に前記第１の多層グラフェン配線と同一レイヤーに形成され、前記不純物がドーピングされていない多層グラフェン層を含む第２の多層グラフェン配線と、前記第１の多層グラフェン配線の下面に接続された下層コンタクトと、前記第２の多層グラフェン配線の上面に接続された上層コンタクトと、を具備した。   The semiconductor device according to the embodiment includes a substrate on which a semiconductor element is formed, a first multilayer graphene wiring including a multilayer graphene layer formed above the substrate and doped with a predetermined impurity, and the substrate above the substrate. A second multi-layer graphene wiring formed in the same layer as the first multi-layer graphene wiring and including a multi-layer graphene layer not doped with the impurities; a lower layer contact connected to a lower surface of the first multi-layer graphene wiring; And an upper layer contact connected to the upper surface of the second multilayer graphene wiring.

第１の実施形態に係わる半導体装置の概略構造を示す断面図。1 is a cross-sectional view illustrating a schematic structure of a semiconductor device according to a first embodiment. 第２の実施形態に係わる半導体装置の製造工程の前半を示す断面図。Sectional drawing which shows the first half of the manufacturing process of the semiconductor device concerning 2nd Embodiment. 第２の実施形態に係わる半導体装置の製造工程の後半を示す断面図。Sectional drawing which shows the second half of the manufacturing process of the semiconductor device concerning 2nd Embodiment. 第３の実施形態に係わる半導体装置の概略構造を示す断面図。Sectional drawing which shows schematic structure of the semiconductor device concerning 3rd Embodiment. 図４の半導体装置の製造工程を示す断面図。FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG. 4. 第４の実施形態に係わる半導体装置の製造工程を説明するための断面図。Sectional drawing for demonstrating the manufacturing process of the semiconductor device concerning 4th Embodiment.

以下、実施形態の半導体装置を、図面を参照して説明する。   Hereinafter, a semiconductor device of an embodiment will be described with reference to the drawings.

（第１の実施形態）
図１は、第１の実施形態に係わる半導体装置の概略構成を示す断面図である。なお、この図では特に、半導体記憶装置におけるメモリセル領域の配線部分と周辺回路領域の配線部分を示している。 (First embodiment)
FIG. 1 is a cross-sectional view showing a schematic configuration of the semiconductor device according to the first embodiment. In this figure, in particular, the wiring portion in the memory cell region and the wiring portion in the peripheral circuit region in the semiconductor memory device are shown.

トランジスタやキャパシタ等の半導体素子が形成された基板１０上に、層間絶縁膜１４及びコンタクトビア（下層コンタクト）１５が形成されている。基板１０は、例えばＳｉ基板１１内にメモリ素子や各種回路素子等の半導体素子が形成され、更にＳｉ基板１１上に層間絶縁膜１２及び配線層１３が形成されたものとする。そして、下層コンタクト１５は、配線層１３にコンタクトされ、配線層１３を介してＳｉ基板１１内の半導体素子に電気的に接続されている。   An interlayer insulating film 14 and a contact via (lower layer contact) 15 are formed on a substrate 10 on which semiconductor elements such as transistors and capacitors are formed. For example, the substrate 10 is formed by forming semiconductor elements such as memory elements and various circuit elements in an Si substrate 11 and further forming an interlayer insulating film 12 and a wiring layer 13 on the Si substrate 11. The lower layer contact 15 is in contact with the wiring layer 13 and is electrically connected to the semiconductor element in the Si substrate 11 via the wiring layer 13.

なお、基板１０は、Ｓｉ基板１１上に、磁気変態型のメモリ素子やイオン変化型のメモリ素子等の半導体素子を形成したものであっても良い。この場合、図１中の配線層１３の代わりにメモリ素子が設けられ、このメモリ素子が下層コンタクト１５に接続されることになる。   The substrate 10 may be formed by forming a semiconductor element such as a magnetic transformation type memory element or an ion change type memory element on the Si substrate 11. In this case, a memory element is provided instead of the wiring layer 13 in FIG. 1, and this memory element is connected to the lower layer contact 15.

層間絶縁膜１４及び下層コンタクト１５上に複数の多層グラフェン配線が形成され、多層グラフェン配線の一部は下層コンタクト１５に接続されている。即ち、メモリセル領域１００上の第１の多層グラフェン配線２０ａは下層コンタクト１５に接続され、周辺回路領域２００上の第２の多層グラフェン配線２０ｂは下層コンタクト１５とは接続されてない状態となっている。   A plurality of multilayer graphene wirings are formed on the interlayer insulating film 14 and the lower layer contact 15, and a part of the multilayer graphene wiring is connected to the lower layer contact 15. That is, the first multilayer graphene wiring 20 a on the memory cell region 100 is connected to the lower layer contact 15, and the second multilayer graphene wiring 20 b on the peripheral circuit region 200 is not connected to the lower layer contact 15. Yes.

多層グラフェン配線２０ａ，２０ｂは、グラフェン層の成長を促進するための触媒下地層２１と、グラフェン成長のための触媒金属層２２と、電気伝導を担う多層グラフェン層２３（２３ａ，２３ｂ）からなる。グラフェン下地層２１は、多層グラフェン層２３の均一成長を促進するための層であり、グラフェン層成長の助触媒としての機能も有する。   The multilayer graphene wirings 20a and 20b include a catalyst base layer 21 for promoting the growth of the graphene layer, a catalyst metal layer 22 for growing the graphene, and a multilayer graphene layer 23 (23a and 23b) for conducting electric conduction. The graphene underlayer 21 is a layer for promoting uniform growth of the multilayer graphene layer 23, and also has a function as a co-catalyst for graphene layer growth.

代表的な触媒下地層材料として、Ｔｉ，Ｔａ，Ｒｕ，Ｗ，及びこれらの窒化物がある。或いはこれら金属の酸化物でも良い。さらに、これらの膜を積層して用いることも可能である。触媒金属材料には、Ｃｏ，Ｎｉ，Ｆｅ、Ｒｕ、Ｃｕなどの単体金属、又は少なくともこれらの何れかを含む合金、或いはこれらの炭化物等が好ましい。   Typical catalyst underlayer materials include Ti, Ta, Ru, W, and nitrides thereof. Alternatively, oxides of these metals may be used. Further, these films can be used in a stacked manner. The catalytic metal material is preferably a single metal such as Co, Ni, Fe, Ru, or Cu, an alloy containing at least one of these, or a carbide thereof.

触媒金属層２２は、連続膜であることが望ましく、連続膜となるために少なくとも０．５ｎｍ以上の膜厚が必要である。触媒金属層２２が分散して微粒子化した状態では、グラフェン自体がうまく成長できない、或いはグラフェン層が不連続となって形成される可能性がある。このため、均一な連続したグラフェン層を形成するためには、触媒金属層２２が連続膜となるような膜厚に成膜することが必要である。   The catalytic metal layer 22 is preferably a continuous film, and needs a film thickness of at least 0.5 nm or more in order to become a continuous film. In a state where the catalytic metal layer 22 is dispersed and finely divided, the graphene itself may not grow well, or the graphene layer may be formed discontinuously. For this reason, in order to form a uniform continuous graphene layer, it is necessary to form the film so that the catalytic metal layer 22 is a continuous film.

触媒金属層２２の上方には、多層グラフェン層２３が形成されている。多層グラフェン層２３は、グラファイト膜が１層から数１０層程度積層された極薄膜の構造である。多層グラフェン層２３の形成は、４５０℃以上のプラズマＣＶＤ法或いは熱ＣＶＤ法により行われ、ＣＶＤのソースガスには例えばメタノールやエタノール、アセチレンなどが用いられる。グラフェンの成長温度は高温であるほど、グラフェンシート中に含まれる欠陥密度が低減されるので、高温成膜が好ましい。   A multilayer graphene layer 23 is formed above the catalytic metal layer 22. The multilayer graphene layer 23 has an extremely thin film structure in which about 1 to several tens of graphite films are stacked. The multilayer graphene layer 23 is formed by a plasma CVD method or a thermal CVD method at 450 ° C. or higher. For example, methanol, ethanol, acetylene, or the like is used as a CVD source gas. The higher the graphene growth temperature, the lower the density of defects contained in the graphene sheet.

但し、通常７００℃以上の高温成膜で行う場合には、下層の触媒金属層２２である例えばＣｏやＮｉの金属層は、グラフェン成膜の熱工程によって表面凝集を生じる場合がある。表面凝集が大きいと、触媒金属層２２が不連続となり、それに伴い、触媒金属層２２上に形成される多層グラフェン層２３も不連続となることがある。これを防ぐ目的でグラフェンを例えば８００℃以上の高温において成長させる場合には、触媒金属層２２中に高融点金属、例えばＷやＭｏやＩｒを添加した合金触媒層であっても良い。また、触媒金属層２２を例えば窒化処理して金属化合物として供給する方法も有効である。   However, when the film formation is usually performed at a high temperature of 700 ° C. or higher, the lower catalyst metal layer 22 such as a Co or Ni metal layer may cause surface aggregation due to the thermal process of graphene film formation. When the surface aggregation is large, the catalyst metal layer 22 becomes discontinuous, and accordingly, the multilayer graphene layer 23 formed on the catalyst metal layer 22 may also become discontinuous. When graphene is grown at a high temperature of, for example, 800 ° C. or more for the purpose of preventing this, an alloy catalyst layer in which a refractory metal such as W, Mo, or Ir is added to the catalyst metal layer 22 may be used. A method of supplying the catalyst metal layer 22 as a metal compound by nitriding, for example, is also effective.

多層グラフェン配線２０ａ，２０ｂの上には、該配線を被覆するように表面保護層３１が形成されている。表面保護層３１は、例えばＳｉＮやＳｉＯ2 膜であり、ＣＶＤ法などによって形成される。表面保護層３１は、多層グラフェン層２３及び触媒金属層２２、触媒下地膜２１を加工するための加工ハードマスクとして用いられる他に、多層グラフェンを含む配線層材料の酸化を防止する役割と、配線構造の上層にコンタクト層が形成される場合は、上層配線との層間絶縁膜或いは層間絶縁膜の一部として使用されても良い。 A surface protective layer 31 is formed on the multilayer graphene wirings 20a and 20b so as to cover the wirings. The surface protective layer 31 is, for example, a SiN or SiO 2 film, and is formed by a CVD method or the like. The surface protective layer 31 is used as a processing hard mask for processing the multilayer graphene layer 23, the catalyst metal layer 22, and the catalyst base film 21, and serves to prevent oxidation of the wiring layer material containing the multilayer graphene, When a contact layer is formed on the upper layer of the structure, it may be used as an interlayer insulating film with the upper layer wiring or as a part of the interlayer insulating film.

周辺回路領域２００上では、表面保護層３１内にコンタクトビア（上層コンタクト）３３が設けられている。そして、表面保護層３１上に、コンタクトビア３３に接続されるように配線層３４が設けられている。   On the peripheral circuit region 200, a contact via (upper layer contact) 33 is provided in the surface protective layer 31. A wiring layer 34 is provided on the surface protective layer 31 so as to be connected to the contact via 33.

触媒下地層２１並びに触媒金属層２２を介して下層コンタクト１５に接続されるメモリセル領域１００側の多層グラフェン層２３ａには、ハロゲン系元素として例えばＢｒが添加されている。ここで、添加元素は必ずしもＢｒに限らず、Ｉ，Ｆ，Ｃｌなどを用いることも可能である。ＦはＦ5Ａｓの形で添加すればよい。これらの添加元素はグラフェンと超格子構造を形成していても良く、超格子構造を有する場合には更にグラフェンシートのキャリア移動度が上昇する。ＮＡＮＤフラッシュメモリに代表させるメモリ構造では、素子領域に用いられる素子部配線は、デバイス高集積化のため特に微細に作製され、下層のメモリ素子を駆動するため、配線には下層コンタクトが形成される。この素子領域にドーピンググラフェン配線を用いることにより、特に微細に形成させる素子部配線の配線抵抗を低減することができる。 For example, Br is added as a halogen-based element to the multilayer graphene layer 23a on the memory cell region 100 side connected to the lower layer contact 15 via the catalyst base layer 21 and the catalyst metal layer 22. Here, the additive element is not necessarily limited to Br, and I, F, Cl, or the like can also be used. F may be added in the form of F 5 As. These additive elements may form a superlattice structure with graphene. When the additive element has a superlattice structure, the carrier mobility of the graphene sheet is further increased. In a memory structure typified by a NAND flash memory, an element portion wiring used in the element region is particularly finely manufactured for device integration, and a lower layer contact is formed in the wiring to drive a lower layer memory element. . By using the doping graphene wiring in this element region, it is possible to reduce the wiring resistance of the element portion wiring formed particularly finely.

これに対し、上層コンタクト３３に直接接続される周辺回路領域２００側の多層グラフェン層２３ｂには、上記Ｂｒ等の添加元素のドーピングを行わない。即ち、上層コンタクト３３が形成される配線にはドーピングを行わず、ドーピング領域を切り分ける。これにより、上層コンタクト側では、コンタクト金属を形成する際に、添加元素がないので、コンタクト金属と反応したり、腐食することがなく、グラフェン層とコンタクト金属が直接接する構造が形成されるので、良好な配線−コンタクト特性が確保される。   In contrast, the multilayer graphene layer 23b on the peripheral circuit region 200 side directly connected to the upper layer contact 33 is not doped with an additive element such as Br. That is, the doping region is separated without doping the wiring in which the upper contact 33 is formed. Thereby, on the upper layer contact side, since there is no additive element when forming the contact metal, there is no reaction with the contact metal or corrosion, and a structure in which the graphene layer and the contact metal are in direct contact is formed. Good wiring-contact characteristics are ensured.

ＮＡＮＤフラッシュメモリに代表されるメモリ構造では、メモリ素子を制御する周辺回路部に用いられる周辺回路配線に、上層側からコンタクトが取られる。上層コンタクトが形成される周辺回路配線にはドーピングを行わない。周辺回路配線は素子部配線より通常幅広く形成されるので、ドーピングを行わなくても低い配線抵抗を確保できる。   In a memory structure typified by a NAND flash memory, a contact is taken from the upper layer side to a peripheral circuit wiring used in a peripheral circuit unit that controls a memory element. Doping is not performed on the peripheral circuit wiring where the upper layer contact is formed. Since the peripheral circuit wiring is usually formed wider than the element portion wiring, a low wiring resistance can be ensured without doping.

なお、図１にも示すように、ドーピングを行った多層グラフェン配線２０ｂでは、その高さ方向に高さが増加している。   In addition, as shown also in FIG. 1, in the multilayer graphene wiring 20b which doped, the height is increasing in the height direction.

このように本実施形態によれば、メモリセル領域１００の第１の多層グラフェン配線２０ａの多層グラフェン層２３ａにＢｒをドープすることにより、配線２０ａの低抵抗化をはかることができる。そして、周辺回路領域２００の第２の多層グラフェン配線２０ｂの多層グラフェン層２３ｂにはＢｒをドープしないため、周辺部の配線２０ｂに上層コンタクト３３を接続しても、コンタクト３３のエッチングや腐食を防止することができる。従って、金属材料のエッチングや腐食を招くことなく、グラフェン配線構造の低抵抗化をはかることができ、素子特性の向上に寄与することが可能となる。   As described above, according to the present embodiment, the resistance of the wiring 20a can be reduced by doping Br into the multilayer graphene layer 23a of the first multilayer graphene wiring 20a in the memory cell region 100. Since the multilayer graphene layer 23b of the second multilayer graphene wiring 20b in the peripheral circuit region 200 is not doped with Br, even if the upper contact 33 is connected to the peripheral wiring 20b, etching and corrosion of the contact 33 are prevented. can do. Accordingly, the resistance of the graphene wiring structure can be reduced without causing etching or corrosion of the metal material, which can contribute to improvement of element characteristics.

（第２の実施形態）
次に、第１の実施形態の前記図１の構造を実現するための製造方法を、図２及び図３を参照して説明する。 (Second Embodiment)
Next, a manufacturing method for realizing the structure of FIG. 1 according to the first embodiment will be described with reference to FIGS.

まず、図２（ａ）に示すように、所望の半導体素子が形成された基板１０上に層間絶縁膜１４を形成し、この層間絶縁膜１４内の一部にコンタクトビア（下層コンタクト）１５を形成する。基板１０は、例えばＳｉ基板１１内にメモリ素子や各種回路素子等の半導体素子を形成し、これらの上に層間絶縁膜１２及び配線１３を形成したものである。下層コンタクト１５は、配線層１３に接続され、配線層１３を介してＳｉ基板１１内の半導体素子に電気的に接続されている。   First, as shown in FIG. 2A, an interlayer insulating film 14 is formed on a substrate 10 on which a desired semiconductor element is formed, and a contact via (lower contact) 15 is formed in a part of the interlayer insulating film 14. Form. The substrate 10 is formed by, for example, forming a semiconductor element such as a memory element or various circuit elements in an Si substrate 11 and forming an interlayer insulating film 12 and a wiring 13 thereon. The lower layer contact 15 is connected to the wiring layer 13 and is electrically connected to the semiconductor element in the Si substrate 11 via the wiring layer 13.

次いで、図２（ｂ）に示すように、層間絶縁膜１４上及びコンタクトビア１５上に、触媒下地層２１，触媒金属層２２，及び多層グラフェン層２３からなるグラフェン配線構造２０を形成し、さらにその上に保護絶縁膜３１を形成する。   Next, as shown in FIG. 2B, a graphene wiring structure 20 including a catalyst underlayer 21, a catalyst metal layer 22, and a multilayer graphene layer 23 is formed on the interlayer insulating film 14 and the contact via 15, A protective insulating film 31 is formed thereon.

具体的には、まず層間絶縁膜１４上及びコンタクトビア１５上に、例えばＴｉからなる触媒下地層２１を成膜し、その上に、例えばＣｏからなる０．５ｎｍ以上の触媒金属層２２を成膜する。続いて、触媒金属層２２上に、４５０℃以上のプラズマＣＶＤ法で、極薄のグラファイト膜を複数層積層した多層グラフェン層２３を成膜する。そして、多層グラフェン層２３の上に、例えばＳｉＯ2 からなる保護絶縁膜３１を形成する。 Specifically, first, a catalyst base layer 21 made of Ti, for example, is formed on the interlayer insulating film 14 and the contact via 15, and a catalyst metal layer 22 of 0.5 nm or more made of Co, for example, is formed thereon. Film. Subsequently, a multilayer graphene layer 23 in which a plurality of ultrathin graphite films are stacked is formed on the catalytic metal layer 22 by a plasma CVD method at 450 ° C. or higher. Then, a protective insulating film 31 made of, for example, SiO 2 is formed on the multilayer graphene layer 23.

次いで、図２（ｃ）に示すように、グラフェン保護層３１、多層グラフェン層２３、触媒金属層２２、触媒下地層２１をリソグラフィ、ＲＩＥ加工、Ｗｅｔ処理により、所望の配線形状に形成する。このときのＲＩＥ加工では、グラフェンと反応せずグラフェンにドープされないガス、例えばＣｏ，Ｈ2 等を用いる。メモリセル領域１００では下層コンタクト１５に接続された第１の多層グラフェン配線２０ａを形成し、周辺回路領域２００では下層コンタクト１５に接続されない第２の多層グラフェン配線２０ｂを形成する。 Next, as shown in FIG. 2C, the graphene protective layer 31, the multilayer graphene layer 23, the catalyst metal layer 22, and the catalyst underlayer 21 are formed into a desired wiring shape by lithography, RIE processing, and wet processing. In this RIE process, a gas that does not react with graphene and is not doped with graphene, for example, Co, H 2, or the like is used. In the memory cell region 100, the first multilayer graphene wiring 20a connected to the lower layer contact 15 is formed, and in the peripheral circuit region 200, the second multilayer graphene wiring 20b not connected to the lower layer contact 15 is formed.

次いで、図３（ｄ）に示すように、ドーピングを行わない上層コンタクトが形成される多層グラフェン配線２０ｂ上に、例えばフォトレジスト３２によるパターニングを行い、マスクを形成して、ドーピングを行う配線領域と、行わない配線領域の切り分けを行う。   Next, as shown in FIG. 3D, on the multilayer graphene wiring 20b where the upper layer contact without doping is formed, patterning is performed using, for example, a photoresist 32, a mask is formed, and a wiring region for doping is formed. Then, the wiring area which is not performed is separated.

次いで、図３（ｅ）に示すように、添加元素として例えばＢｒをガスフローする。温度を高くすると添加元素が触媒金属と反応し、触媒金属をエッチングする可能性があるので、ガスフローは室温で行う方が好ましい。さらに、バイアスも掛けない方が望ましい。室温で行うことにより触媒金属をエッチングすることなく、グラフェン層中にドーピングが行える。レジスト３２でマスクされた第２の多層グラフェン配線２０ｂ側には添加は行われない。最後にレジスト３２を除去することにより、ドーピンググラフェン配線とドーピングを行わないグラフェン配線をＬＳＩの同一層に形成することが可能となる。上層配線と接続される上層コンタクトを有する多層グラフェン配線２０ｂにはその後、上層コンタクト３３ならびに上層配線３４が形成される。   Next, as shown in FIG. 3E, for example, Br is gas-flowed as an additive element. When the temperature is increased, the additive element reacts with the catalyst metal and may cause the catalyst metal to be etched. Therefore, the gas flow is preferably performed at room temperature. Furthermore, it is desirable not to apply a bias. By performing at room temperature, the graphene layer can be doped without etching the catalyst metal. No addition is performed on the second multilayer graphene wiring 20b side masked with the resist 32. Finally, by removing the resist 32, the doped graphene wiring and the non-doped graphene wiring can be formed in the same layer of the LSI. Thereafter, the upper layer contact 33 and the upper layer wiring 34 are formed in the multilayer graphene wiring 20b having the upper layer contact connected to the upper layer wiring.

（第３の実施形態）
第２の実施形態ではマスクパターンを用いて不純物ドーピングの切り分けを行ったが、図４に示すように、ドーピングの濃度プロファイルをコントロールすることにより、切り分けを行っても良い。即ち、下層コンタクト１５と接続されるメモリセル領域１００の多層グラフェン配線２０ａには配線幅方向に全域にドーピングが行き渡るように行い、上層コンタクト３３と接続される周辺回路領域２００の配線２０ｂにはコンタクト３３と接する領域には添加元素が届かないように、エッジ領域のみにドーピングする。 (Third embodiment)
In the second embodiment, the impurity doping is separated using the mask pattern. However, as shown in FIG. 4, the doping may be performed by controlling the doping concentration profile. That is, the multi-layer graphene wiring 20a of the memory cell region 100 connected to the lower layer contact 15 is doped so as to cover the entire area in the wiring width direction, and the wiring 20b of the peripheral circuit region 200 connected to the upper layer contact 33 is contacted. Doping is performed only in the edge region so that the additive element does not reach the region in contact with 33.

上記のようなドーピング濃度差を形成するためには、添加元素Ｂｒのガスフローの流量や時間を制御することで実現される。具体的には、前記図２（ｃ）と同様にして図５（ａ）に示すように、配線パターンに加工した後に、ガスフローにより多層グラフェン層２３に不純物をドーピングする。このとき、第２の多層グラフェン配線２０ｂの幅が第１の多層グラフェン配線２０ａよりも広いため、ガスフローの流量や時間を制御することにより、図５（ｂ）に示すように、第１の多層グラフェン配線２０ａでは全体がドーピングされ、第２の多層グラフェン配線２０ｂではエッジ近傍のみがドーピングされた状態となる。   Formation of the doping concentration difference as described above is realized by controlling the flow rate and time of the gas flow of the additive element Br. Specifically, as shown in FIG. 5A, the multi-layer graphene layer 23 is doped with a gas flow after processing into a wiring pattern as shown in FIG. At this time, since the width of the second multilayer graphene wiring 20b is wider than that of the first multilayer graphene wiring 20a, by controlling the flow rate and time of the gas flow, as shown in FIG. The multilayer graphene wiring 20a is entirely doped, and the second multilayer graphene wiring 20b is doped only in the vicinity of the edge.

ここで、ドーピングをさせた部分のグラフェン層間の物理距離が広がるので、図４のようにエッジ側が膨らんだ構造になる。また、拡散現象であるため、ドーピング濃度は中心に向かって薄くなり、層間距離も中心に行くに従い減少するので、グラフェン層２３ｂの一部が傾斜することになる。   Here, since the physical distance between the graphene layers in the doped portion is widened, the edge side swells as shown in FIG. Further, because of the diffusion phenomenon, the doping concentration becomes thinner toward the center, and the interlayer distance also decreases as it goes to the center. Therefore, a part of the graphene layer 23b is inclined.

このように本実施形態では、第１の多層グラフェン配線２０ａは、第１の実施形態と同様に多層グラフェン層２３ａ全体がドーピング層となっており、配線抵抗の低抵抗化をはかることができる。第２の多層グラフェン配線２０ｂは、多層グラフェン層２３ｂのエッジのみがドーピング層となっているが、中央部はノンドープとなっているため、上層コンタクト３３のエッチングや腐食を防止することができる。従って、先の第１の実施形態と同様の効果が得られる。   As described above, in the present embodiment, the first multilayer graphene wiring 20a has the entire multilayer graphene layer 23a as a doping layer as in the first embodiment, so that the wiring resistance can be reduced. In the second multilayer graphene wiring 20b, only the edge of the multilayer graphene layer 23b is a doped layer, but the central portion is non-doped, so that etching and corrosion of the upper contact 33 can be prevented. Therefore, the same effect as in the first embodiment can be obtained.

また、第２の多層グラフェン配線２０ｂはエッジ部にＢｒがドーピングされているため、全体がノンドープよりも配線抵抗を低減できる利点もある。さらに、フォトレジスト等のマスクを用いることなくドーピングを行うことができるため、プロセスが簡略化される利点もある。   In addition, since the second multilayer graphene wiring 20b is doped with Br at the edge portion, the entire multilayer graphene wiring 20b has an advantage that the wiring resistance can be reduced as compared with non-doping. Furthermore, since doping can be performed without using a mask such as a photoresist, there is an advantage that the process is simplified.

（第４の実施形態）
本実施形態は、多層配線構造を配線パターンにパターニングした後に不純物をドーピングするのではなく、パターニングと同時にドーピングを行う方法である。 (Fourth embodiment)
The present embodiment is a method of performing doping simultaneously with patterning, instead of doping impurities after patterning a multilayer wiring structure into a wiring pattern.

前記図２（ｃ）に示すエッチングの工程で、ＲＩＥのエッチングガスとしてＢｒ，Ｆ5Ａｓ，Ｉ，Ｃｌ等のハロゲン元素を添加剤として含むものを用いる。このようなエッチングガスを用いることにより、図６に示すように、多層グラフェン配線構造２０の配線加工と多層グラフェン層２３へのドーピングを一括で行うことができる。 In the etching step shown in FIG. 2C, an RIE etching gas containing a halogen element such as Br, F 5 As, I, or Cl as an additive is used. By using such an etching gas, as shown in FIG. 6, wiring processing of the multilayer graphene wiring structure 20 and doping to the multilayer graphene layer 23 can be performed at once.

具体的には、メモリセル領域１００と周辺回路領域２００とに分けてパターニングし、メモリセル領域１００のパターニング時に上記のハロゲン元素を添加剤として含むガスでＲＩＥを行い、周辺回路領域２００のパターニング時はＣｏ，Ｈ2 等を添加剤として含むガスでＲＩＥを行えばよい。 Specifically, patterning is performed separately for the memory cell region 100 and the peripheral circuit region 200, and RIE is performed with a gas containing the above halogen element as an additive during patterning of the memory cell region 100. RIE may be performed with a gas containing Co, H 2 or the like as an additive.

また、ＲＩＥ時におけるドーピング速度を制御することにより、メモリセル領域１００と周辺回路領域２００とを同時にパターニングし、第３の実施形態と同様に、第１の多層グラフェン配線２０ａでは全体にドーピングし、第２の多層グラフェン配線２０ｂではエッジ部のみにドーピングを行うようにしても良い。   Further, by controlling the doping rate during RIE, the memory cell region 100 and the peripheral circuit region 200 are simultaneously patterned, and in the same way as in the third embodiment, the entire first multilayer graphene wiring 20a is doped, In the second multilayer graphene wiring 20b, only the edge portion may be doped.

このように本実施形態では、ドーピングを行った第１の多層グラフェン配線２０ａと、ドーピングを行わない（又はエッジ部のみにドーピングを行った）第２の多層グラフェン配線２０ｂとを実現することができ、第１の実施形態と同様の効果が得られる。しかも、ＲＩＥのガスの選択により、多層配線構造のパターニング時にドーピングを行うことができるため、工程が簡略化され、プロセス製造の低コスト化をはかることができる。   As described above, in this embodiment, it is possible to realize the first multilayer graphene wiring 20a with doping and the second multilayer graphene wiring 20b without doping (or doping only in the edge portion). The same effects as those of the first embodiment can be obtained. In addition, since the doping can be performed at the time of patterning the multilayer wiring structure by selecting the RIE gas, the process can be simplified and the cost of the process manufacturing can be reduced.

（変形例）
なお、本発明は上述した各実施形態に限定されるものではない。 (Modification)
The present invention is not limited to the above-described embodiments.

実施形態では、ハロゲン系の元素としてＢｒを用いたが、これに限らずＩ，Ｆ，Ｃｌを用いることも可能である。   In the embodiment, Br is used as the halogen-based element. However, the present invention is not limited to this, and it is also possible to use I, F, or Cl.

また、下層コンタクトに接続される多層グラフェン配線の全てをドーピング、上層コンタクトに接続される多層グラフェン配線の全てをノンドーピングとするのではなく、メモリセル領域ではドーピング、周辺回路領域ではノンドーピングとしても良い。即ち、下層コンタクトに接続されるか上層コンタクトに接続されるかでドーピングを切り分けるのではなく、メモリセル領域か周辺回路領域かでドーピングを切り分けるようにしても良い。メモリセル領域では下層コンタクトに接続される配線が多く、周辺回路領域では上層コンタクトに接続される配線が多いために、上記のように領域毎に切り分けることは有効となる。   In addition, all of the multilayer graphene wiring connected to the lower layer contact is doped, and all of the multilayer graphene wiring connected to the upper layer contact is not doped. Instead, the memory cell region is doped and the peripheral circuit region is not doped. good. That is, the doping may be separated in the memory cell region or the peripheral circuit region, instead of being separated depending on whether it is connected to the lower layer contact or the upper layer contact. Since there are many wirings connected to the lower layer contact in the memory cell region and many wirings connected to the upper layer contact in the peripheral circuit region, it is effective to separate each region as described above.

また、触媒下地層、触媒金属層、及びグラフェン層の材料等は、仕様に応じて適宜変更可能である。さらに、触媒金属層のみでグラフェン層が均一に成長する場合には、触媒下地層は省略することも可能である。   Moreover, the material of a catalyst base layer, a catalyst metal layer, a graphene layer, etc. can be suitably changed according to a specification. Furthermore, when the graphene layer grows uniformly with only the catalyst metal layer, the catalyst underlayer can be omitted.

本発明の幾つかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると同様に、特許請求の範囲に記載された発明とその均等の範囲に含まれるものである。   Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

（付記）
（図２，３のプロセス）
半導体素子が形成された基板上に層間絶縁膜及び下層コンタクトを形成する工程と、
前記層間絶縁膜上及び前記下層コンタクト上に、多層グラフェン層を有する多層グラフェン配線構造を形成する工程と、
前記多層グラフェン配線構造を配線パターンに加工し、前記下層コンタクトに接続される第１の多層グラフェン配線及び前記下層コンタクトに接続されない第２の多層グラフェン配線を形成する工程と、
前記第２の多層グラフェン配線をマスクした後に、前記第１の多層グラフェン配線にハロゲン系の元素をドーピングする工程と、
前記第２の多層グラフェン配線に接続される上層コンタクトを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 (Appendix)
(Process of Fig. 2 and 3)
Forming an interlayer insulating film and a lower layer contact on a substrate on which a semiconductor element is formed;
Forming a multilayer graphene wiring structure having a multilayer graphene layer on the interlayer insulating film and the lower layer contact;
Processing the multilayer graphene wiring structure into a wiring pattern to form a first multilayer graphene wiring connected to the lower layer contact and a second multilayer graphene wiring not connected to the lower layer contact;
Masking the second multilayer graphene wiring and then doping the first multilayer graphene wiring with a halogen-based element;
Forming an upper contact connected to the second multilayer graphene wiring;
A method for manufacturing a semiconductor device, comprising:

（図５のプロセス）
半導体素子が形成された基板上に層間絶縁膜及び下層コンタクトを形成する工程と、
前記層間絶縁膜上及び前記下層コンタクト上に、多層グラフェン層を有する多層グラフェン配線構造を形成する工程と、
前記多層グラフェン配線構造を配線パターンに加工し、前記下層コンタクトに接続される第１の多層グラフェン配線及び前記下層コンタクトに接続されない前記第１の多層グラフェン配線よりも幅広の第２の多層グラフェン配線を形成する工程と、
前記第１及び第２の多層グラフェン配線の側面からハロゲン系の元素をドーピングすることにより、前記第１の多層グラフェン配線の前記多層グラフェン層の全体をドーピングし、且つ前記第２の多層グラフェン配線の前記多層グラフェン層のエッジ部を選択的にドーピングする工程と、
前記第２の多層グラフェン配線に接続される上層コンタクトを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 (Process of FIG. 5)
Forming an interlayer insulating film and a lower layer contact on a substrate on which a semiconductor element is formed;
Forming a multilayer graphene wiring structure having a multilayer graphene layer on the interlayer insulating film and the lower layer contact;
The multilayer graphene wiring structure is processed into a wiring pattern, and a first multilayer graphene wiring connected to the lower layer contact and a second multilayer graphene wiring wider than the first multilayer graphene wiring not connected to the lower layer contact are formed. Forming, and
By doping a halogen-based element from the side surfaces of the first and second multilayer graphene wirings, the entire multilayer graphene layer of the first multilayer graphene wiring is doped, and the second multilayer graphene wiring Selectively doping an edge portion of the multilayer graphene layer;
Forming an upper contact connected to the second multilayer graphene wiring;
A method for manufacturing a semiconductor device, comprising:

（図６のプロセス）
半導体素子が形成された基板上に層間絶縁膜及び下層コンタクトを形成する工程と、
前記層間絶縁膜上及び前記下層コンタクト上に、多層グラフェン層を有する多層グラフェン配線構造を形成する工程と、
前記多層グラフェン配線構造を、ハロゲン系のガスを用いたＲＩＥにより配線パターンに加工し、前記下層コンタクトに接続される第１の多層グラフェン配線及び前記下層コンタクトに接続されない前記第１の多層グラフェン配線よりも幅広の第２の多層グラフェン配線を形成する工程と、
前記第２の多層グラフェン配線に接続される上層コンタクトを形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 (Process of FIG. 6)
Forming an interlayer insulating film and a lower layer contact on a substrate on which a semiconductor element is formed;
Forming a multilayer graphene wiring structure having a multilayer graphene layer on the interlayer insulating film and the lower layer contact;
The multilayer graphene wiring structure is processed into a wiring pattern by RIE using a halogen-based gas, and the first multilayer graphene wiring connected to the lower layer contact and the first multilayer graphene wiring not connected to the lower layer contact Forming a wide second multilayer graphene wiring; and
Forming an upper contact connected to the second multilayer graphene wiring;
A method for manufacturing a semiconductor device, comprising:

１０…基板
１１…Ｓｉ基板
１２…層間絶縁膜
１３…配線層
１４…層間絶縁膜
１５…コンタクトビア（下層コンタクト）
２０…多層グラフェン配線構造
２０ａ…第１の多層グラフェン配線
２０ｂ…第２の多層グラフェン配線
２１…触媒下地層
２２…触媒金属層
２３…多層グラフェン層
３１…表面保護層
３２…フォトレジスト
３３…コンタクトビア（上層コンタクト）
３４…配線層
１００…メモリセル領域
２００…周辺回路領域 DESCRIPTION OF SYMBOLS 10 ... Board | substrate 11 ... Si substrate 12 ... Interlayer insulation film 13 ... Wiring layer 14 ... Interlayer insulation film 15 ... Contact via (lower layer contact)
DESCRIPTION OF SYMBOLS 20 ... Multilayer graphene wiring structure 20a ... 1st multilayer graphene wiring 20b ... 2nd multilayer graphene wiring 21 ... Catalyst underlayer 22 ... Catalyst metal layer 23 ... Multilayer graphene layer 31 ... Surface protection layer 32 ... Photoresist 33 ... Contact via (Upper contact)
34 ... Wiring layer 100 ... Memory cell area 200 ... Peripheral circuit area

Claims (6)

半導体記憶装置のメモリセル領域及び周辺回路領域を有する基板と、
前記メモリセル領域上に下層側から順に、触媒下地層、触媒金属層、及びＢｒ，Ｉ，Ｆ，若しくはＣｌの不純物がドーピングされた多層グラフェン層を積層して形成された第１の多層グラフェン配線と、
前記周辺回路領域上に下層から順に、触媒下地層、触媒金属層、及び前記不純物がドーピングされていない多層グラフェン層を積層して形成され、前記第１の多層グラフェン配線と同一レイヤーに形成された第２の多層グラフェン配線と、
前記第１の多層グラフェン配線の下面に接続された下層コンタクトと、
前記第２の多層グラフェン配線の上面に接続された上層コンタクトと、
を具備したことを特徴とする半導体装置。 A substrate having a memory cell region and a peripheral circuit region of the semiconductor memory device;
A first multilayer graphene wiring formed by laminating a catalyst base layer, a catalyst metal layer, and a multilayer graphene layer doped with an impurity of Br, I, F, or Cl in order from the lower layer side on the memory cell region When,
In order from the lower layer on the peripheral circuit region, a catalyst underlayer, a catalyst metal layer, and a multilayer graphene layer not doped with the impurity are stacked and formed in the same layer as the first multilayer graphene wiring A second multilayer graphene wiring;
A lower layer contact connected to a lower surface of the first multilayer graphene wiring;
An upper contact connected to the upper surface of the second multilayer graphene wiring;
A semiconductor device comprising: 半導体素子が形成された基板と、
前記基板の上方に下層側から順に、触媒下地層、触媒金属層、及び所定の不純物がドーピングされた多層グラフェン層を積層して形成された第１の多層グラフェン配線と、
前記基板の上方に前記第１の多層グラフェン配線と同一レイヤーに形成され、下層から順に、触媒下地層、触媒金属層、及び前記不純物がドーピングされていない多層グラフェン層を積層して形成された第２の多層グラフェン配線と、
前記第１の多層グラフェン配線の下面に接続された下層コンタクトと、
前記第２の多層グラフェン配線の上面に接続された上層コンタクトと、
を具備したことを特徴とする半導体装置。 A substrate on which a semiconductor element is formed;
A first multilayer graphene wiring formed by laminating a catalyst underlayer, a catalyst metal layer, and a multilayer graphene layer doped with a predetermined impurity in order from the lower layer side above the substrate;
Is formed on the first multilayer graphene wiring and the same layer above the substrate, in order from the lower layer, catalyst underlying layer, the catalyst metal layer, and the said impurity is formed by laminating a multilayer graphene layer undoped 2 multilayer graphene wirings;
A lower layer contact connected to a lower surface of the first multilayer graphene wiring;
An upper contact connected to the upper surface of the second multilayer graphene wiring;
A semiconductor device comprising: 半導体素子が形成された基板と、
前記基板の上方に下層側から順に、触媒下地層、触媒金属層、及び所定の不純物がドーピングされた多層グラフェン層を積層して形成された第１の多層グラフェン配線と、
前記基板の上方に前記第１の多層グラフェン配線と同一レイヤーに前記第１の多層グラフェン配線よりも幅広に形成され、下層側から順に、触媒下地層、触媒金属層、及びエッジ部分に選択的に前記不純物がドーピングされた多層グラフェン層を積層して形成された第２の多層グラフェン配線と、
前記第１の多層グラフェン配線の下面に接続された下層コンタクトと、
前記第２の多層グラフェン配線の上面に接続された上層コンタクトと、
を具備したことを特徴とする半導体装置。 A substrate on which a semiconductor element is formed;
A first multilayer graphene wiring formed by laminating a catalyst underlayer, a catalyst metal layer, and a multilayer graphene layer doped with a predetermined impurity in order from the lower layer side above the substrate;
The first multilayer graphene wiring is formed in the same layer as the first multilayer graphene wiring above the substrate and wider than the first multilayer graphene wiring , and selectively from the lower layer side to the catalyst underlayer, the catalyst metal layer, and the edge portion. A second multilayer graphene wiring formed by stacking multilayer graphene layers doped with the impurities;
A lower layer contact connected to a lower surface of the first multilayer graphene wiring;
An upper contact connected to the upper surface of the second multilayer graphene wiring;
A semiconductor device comprising: 前記不純物は、Ｂｒ，Ｉ，Ｆ，又はＣｌであることを特徴とする請求項２又は３に記載の半導体装置。 The impurities, Br, I, F, or a semiconductor device according to claim 2 or 3, characterized in that is Cl. 前記下層コンタクトは、前記第１の多層グラフェン配線よりも下層側の配線を介して前記半導体素子に接続され、前記上層コンタクトは前記第２の多層グラフェン配線よりも上層側の配線に接続されていることを特徴とする請求項２〜４の何れかに記載の半導体装置。 The lower layer contact is connected to the semiconductor element via a lower layer side wiring than the first multilayer graphene wiring, and the upper layer contact is connected to a higher layer side wiring than the second multilayer graphene wiring. the semiconductor device according to claim 2-4, characterized in that. 前記第１の多層グラフェン配線はメモリセル領域に配置され、前記第２の多層グラフェン配線は周辺回路領域に配置されていることを特徴とする請求項２〜５の何れかに記載の半導体装置。 Said first multilayer graphene wiring is arranged in the memory cell region, the semiconductor device according to any one of claims 2-5 wherein the second multi-layer graphene wiring, characterized in that disposed in the peripheral circuit region.
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