JP5573638B2 - Information processing apparatus and operating method thereof - Google Patents

Description

  The present invention relates to an information processing apparatus and an operation method thereof.

  In an information processing apparatus such as a server, a memory module used as a main memory is mounted on an apparatus main body (motherboard or the like). The main memory plays a major role in the information processing apparatus. Therefore, it is desirable to diagnose the operation of the memory module with the memory module incorporated in the information processing apparatus.

  Patent Document 1 relates to a semiconductor test system, as shown in FIG. 4 of the same document, first disclosed is that an open / short inspection is performed, and then, if there is an open location, a process for identifying the open location is performed. Has been. The open / short inspection is performed by utilizing the DC measuring instrument disclosed in FIG. In order to identify the open location, the waveform detection waveform voltage comparison circuit 20 of FIG. 2 of the same document uses the waveform of the reflected signal returned in the actual connection check and the reference data stored in the waveform detection register 18. Compare the waveform. The circuit 20 outputs a normal signal when the reflected signal waveform matches the normal waveform signal. When the reflected signal waveform matches any of the open waveform signals, the circuit 20 outputs an open location instruction signal indicating that it matches any of the open waveform signals. The circuit 20 outputs the reflected signal waveform together with the abnormal signal when the reflected signal is different from each other. In addition, as described in the upper left column of page 5 of the same document, the waveform detection register 18 shown in FIG. 2 is registered in advance with the waveform data of the reflected waveform acquired in a state where the contacts P1 to P5 are individually opened. Points to keep in mind are explained.

  Patent Document 2 relates to a connector connection confirmation device and employs a circuit configuration shown in FIG. When confirming the presence or absence of poor contact, the connection is confirmed with the switch B shown in FIG. 2 of the same document turned on and the switch A turned off.

JP-A-4-114445 JP 11-296261 A

  The operation diagnosis of the memory module may be performed after the memory module is inserted into the main body connector and electrical connection between the two is ensured. By mounting the memory module on the connector, the memory module is connected to the memory controller on the main body side via the connector, and the memory controller performs an operation check of the memory module.

  However, even after the operation verification of the memory module by the memory controller, it is not known that the operation failure of the memory module is caused by the connection failure between the memory module and the connector. Therefore, some of the memory modules that are determined to be defective by the operation check of the memory module may be acceptable. A memory module determined as a defective product may not be incorporated into the product, and in this case, the yield of the memory module deteriorates at the final stage.

  As is clear from the above description, when the operation check of the module is performed on the main body side in a state where the module is incorporated into the main body device, the module is considered to be defective due to a poor connection between the module and the main body side connector. There is a risk of being judged. In the above description, the memory module is described as an example of a module, but the present invention is not limited to this.

  The information processing apparatus according to the present invention is configured such that a module is electrically connected through a plurality of contacts, a connector through which a plurality of bits of data are input from the module through the plurality of contacts, and the connector is connected to the connector. A bit error determination means for determining whether or not an error has occurred in a bit included in the data of a plurality of bits input via the connector, and a bit in which an error is detected by the bit error determination means A test waveform is input to the first wiring including the contact and the second wiring including the contact corresponding to the bit for which no error is detected by the bit error determination unit, and the test waveform is A connection state determination unit that determines the state of the first wiring by evaluating a difference in level of reflected waves generated in the first and second wirings. And, equipped with a.

  An operation method of an information processing apparatus according to the present invention is an information processing apparatus including a connector to which a module is electrically connected through a plurality of contacts, and a plurality of bits of data are input from the module through the plurality of contacts. The bit error determination means determines whether or not an error has occurred in the bits included in the data of a plurality of bits input via the connector, and the connection state determination means determines the bit error determination. A test waveform for the first wiring including the contact corresponding to the bit in which the error is detected by the means and the second wiring including the contact corresponding to the bit in which the error is not detected by the bit error determination means And the difference in level of the reflected wave generated in each of the first and second wirings is evaluated according to the test waveform. Determine the state.

  ADVANTAGE OF THE INVENTION According to this invention, it can suppress that a module is judged to be malfunctioning due to the connection failure between a module and a main body side connector.

1 is a schematic block diagram of an information processing apparatus according to a first embodiment. FIG. 3 is an explanatory diagram for explaining an operation of the information processing apparatus according to the first embodiment; 1 is a circuit diagram illustrating a specific configuration example of an information processing apparatus according to a first embodiment; FIG. 3 is a schematic diagram for explaining an inspection process according to the first embodiment; It is a schematic block diagram of the information processing apparatus concerning a reference example. It is the schematic for demonstrating the test | inspection process concerning a reference example.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram of the information processing apparatus. FIG. 2 is an explanatory diagram for explaining the operation of the information processing apparatus. FIG. 3 is a circuit diagram illustrating a specific configuration example of the information processing apparatus. FIG. 4 is a schematic diagram for explaining the inspection process.

  As shown in FIG. 1, a server (information processing apparatus) 100 includes a memory device (module) 10, a connector 20, a connection changeover switch (connection changeover means) 30, a memory controller (control means) 40, and a connection confirmation circuit (connection). State determination means) 50. The memory controller 40 includes a bit error detection unit (bit error determination means, error determination means) 41. The connection confirmation circuit 50 includes a line selection control unit (wiring selection unit) 51, a test waveform driver (test waveform supply unit) 52, a reflected wave comparison unit (level difference detection unit) 53, and a difference determination unit (level difference determination unit). 54.

  As is clear from FIG. 1, the number of connection wirings between the memory device 10 and the memory controller 40 is simply displayed for convenience of explanation. First, the description will be given focusing on the connection relationship of the above-described components.

  The memory device 10 has output terminals T10 to T16. The connector 20 has input terminals T20 to T26. The connection changeover switch 30 has input terminals Ti31 to Ti37. The connection changeover switch 30 has output terminals To41 to To47 as a first output terminal group, and has output terminals To51 to To57 as a second output terminal group. Hereinafter, the input and output terminals may be simply referred to as terminals without distinction.

  Depending on the mounting of the memory device 10 to the connector 20, the terminals T10 to T16 of the memory device 10 and the terminals T20 to T26 of the connector 20 are individually connected. Due to the contact between the terminal T10 and the terminal T20, a contact N10 is generated between them. Similarly, N11 to N16 are generated. Note that, when the memory device 10 is not completely attached to the connector 20, the contact does not occur well, and an open portion occurs. The specific shapes of the connector and the memory device are arbitrary. For example, the memory device is a board-like component in which a memory chip is mounted on a daughter board. For example, the connector is configured to sandwich and hold a terminal provided at one end of the memory board.

  The terminals T20 to T26 of the connector are individually connected to the terminals Ti31 to Ti37 of the connection changeover switch 30. The connection between the terminals T20 to T26 and the terminals Ti31 to Ti37 is ensured with high reliability.

  The terminals To41 to To47 of the connection changeover switch are individually connected to the terminal group of the memory controller 40 via the wirings L30 to L36. The terminals To51 to To57 of the connection changeover switch are individually connected to the terminal group of the connection confirmation circuit 50 via the wirings L40 to L46. The connection between the connection changeover switch 30 and the memory controller 40 is also ensured with high reliability. The connection between the connection changeover switch 30 and the connection confirmation circuit 50 is also ensured with high reliability.

  An output terminal of the bit error detection unit 41 provided in the memory controller 40 is connected to an input terminal of the connection changeover switch 30 and is connected to an input terminal of the line selection control unit 51. The output terminal of the line selection control unit 51 is connected to the test waveform driver 52. The test waveform driver 52 has two output terminals. The first output terminal of the test waveform driver 52 is connected to the first input terminal of the line selection control unit 51 via the wiring L1. The second output terminal of the test waveform driver 52 is connected to the second input terminal of the line selection control unit 51 via the wiring L2. The wiring L1 is connected to the first input terminal of the reflected wave comparison unit 53 via the contact DN1. The wiring L2 is connected to the second input terminal of the reflected wave comparison unit 53 via the contact DN2. The output terminal of the reflected wave comparison unit 53 is connected to the input terminal of the difference determination unit 54. The output terminal of the difference determination unit 54 is connected to the input terminal of the bit error detection unit 41.

  Hereinafter, functions and the like of each component described above will be described.

  The server 100 is a general information processing apparatus, and includes an arithmetic processing device such as a CPU (Central Processing Unit), a main storage device such as a hard disk, a substrate such as a motherboard and a daughter board, and the like.

  The memory device 10 is a storage device that functions as a primary storage device. The memory device 10 is mounted on the board on which the connector 20 is provided by being inserted into the connector 20. The memory device 10 includes a plurality of data lines, a plurality of address lines, and a plurality of control lines in addition to a memory cell arrangement region in which a large number of memory cells that store logical values are arranged.

  The connector 20 is a general connector and is provided on a mother board here. The connection changeover switch 30 is a switching circuit that distributes the output destination of the memory device 10 to either the memory controller 40 or the connection confirmation circuit 50. During normal operation, the connection changeover switch 30 outputs the inputs of the terminals Ti31 to Ti37 from the terminals To41 to To47. During the inspection operation, the connection changeover switch 30 outputs the inputs of the terminals Ti31 to Ti37 from the terminals To51 to To57. The selection state of the connection changeover switch 30 is determined by the output signal of the bit error detection unit 41.

  As is well known, the memory controller 40 is a control unit that controls memory access to the memory device 10. The bit error detection unit 41 is a functional circuit that determines the operation state of the memory device 10 based on redundant bits included in the output data of the memory device 10. The bit error detection unit 41 determines which of the bit groups constituting the output data of the memory device 10 has an error from the redundant bits described above. Note that the bit error detection method by the bit error detection unit 41 has been established at the present time, and a detailed description thereof will be omitted here.

  When the bit error detection unit 41 detects a bit error, the bit error detection unit 41 outputs a bit error detection signal (Sig_error). In response to the bit error detection signal, the connection changeover switch 30 connects the terminals Ti31 to Ti37 and the terminals To51 to To57. The line selection control unit 51 selects a set of output wirings from the wirings L40 to L46 based on the bit error detection signal. A set of wirings is a wiring corresponding to a bit in which an error has occurred (hereinafter, simply referred to as an inspection wiring) and a wiring corresponding to a bit in which an error has not occurred (hereinafter simply referred to as a comparison wiring). Are). The line selection control unit 51 outputs a start signal (Sig_start) to the test waveform driver 52 after completion of the line selection operation. The bit error detection signal includes information indicating which wiring is selected as the inspection wiring and which wiring is selected as the comparison wiring. The specific configuration of the line selection control unit 51 is arbitrary. For example, the line selection control unit 51 may be configured by a controller that processes a bit error detection signal and a switching circuit unit.

  The test waveform driver 52 outputs the same test waveform (inspection waveform) to each of the wirings L1 and L2 in response to the input of the above-described start signal (Sig_start). Each waveform input to the wirings L1 and L2 propagates to the memory device 10 side via the wiring (inspection wiring and comparison wiring) selected by the line selection control unit 51. If a contact is normally generated between the memory device 10 and the connector 20, the waveform input to the inspection wiring is input to the memory device. However, when there is no contact between the memory device 10 and the connector 20, the waveform input to the inspection wiring is reflected at the open location. Note that the specific waveform shape of the test waveform is arbitrary as long as it is ensured that the presence or absence of the open portion can be determined.

  The reflected wave comparison unit 53 compares the waveforms individually input from the wirings L1 and L2, and detects the level difference between the waveforms. The reflected wave comparison unit 53 outputs a signal having a value corresponding to the detected level difference. The difference determination unit 54 determines whether or not the input value from the reflected wave comparison unit 53 exceeds a threshold value. When the input value from the reflected wave comparison unit 53 exceeds the threshold value, the difference determination unit 54 outputs a signal indicating that an open location is included in the inspection wiring to the bit error detection unit 41. The bit error detection unit 41 outputs a signal for specifying a bit including an open part to an external processing circuit (Sig_out).

  As described above, the inspection wiring is a wiring corresponding to a bit in which an error has occurred, and the comparison wiring is a wiring corresponding to a bit in which no error has occurred. In the comparison wiring, a contact is normally generated between the memory device 10 and the connector 20. On the other hand, there is a possibility that the contact between the memory device 10 and the connector 20 does not normally occur in the inspection wiring. When no contact is generated between the memory device 10 and the connector 20 in the inspection wiring, the reflection position of the input waveform is different between the inspection wiring and the comparison wiring. The difference in the reflection position of each input waveform appears as a difference in waveform between sampling waveforms input to the reflected wave comparison unit 53 via the wirings L1 and L2. The threshold value set in the difference determination unit 54 is set so that the difference in waveform between the sampling waveforms indicates that the contact is not normally generated between the memory device 10 and the connector 20 in the inspection wiring. With such a mechanism, the connection state between the connector and the memory device is diagnosed.

  With reference to FIG. 2, the above point will be supplementarily described. In FIG. 2, the bit name B1 is attached to the bit corresponding to the terminal name T10. Bit names are similarly assigned to other terminal names.

  In the case illustrated in FIG. 2, the bit error detection unit 41 determines that an error has occurred in the bit corresponding to the output terminal T <b> 13 of the memory device 10 based on the redundant bit signal processing. The bit error detection unit 41 determines that no error has occurred in the bits corresponding to the remaining output terminals of the memory device 10. The bit error detection unit 41 outputs a signal to the connection changeover switch 30, and the state where the terminals Ti31 to Ti37 are connected to the terminals To51 to T57 from the state where the terminals Ti31 to Ti37 are connected to the terminals To41 to T47. Switch to. In addition, the bit error detection unit 41 outputs a signal instructing to select the wiring L43 corresponding to the bit with error and the wiring L44 corresponding to the bit without error to the line selection control unit 51, and the wiring L43 is for inspection. The wiring L44 is selected as the comparison wiring. As a result, the wiring L1 and the wiring L44 are connected, and the wiring L2 and the wiring L43 are connected. After selecting a set of wirings, the line selection control unit 51 instructs the test waveform driver 52 to output a waveform.

  In the case shown in FIG. 2, the waveform input from the test waveform driver 52 to the wiring L1 is input to the memory device 10 via the wiring L44, the terminal To55, the terminal Ti35, the wiring L24, the terminal T24, the contact N14, and the terminal T14. On the other hand, the waveform input to the wiring L2 from the test waveform driver 52 propagates to the memory device 10 side via the wiring L43, the terminal To54, the terminal Ti34, the wiring L23, the terminal T23, and the contact N13. This propagation signal is input to the memory device 10 via the terminal T13 if the contact N13 occurs, and is reflected at the open location if the contact N13 does not occur.

  With reference to FIG. 3, the specific structural example of the component shown in FIG. 1 is demonstrated. Here, the description will be made on the assumption of the case shown in FIG.

  The memory device 10 is simply expressed by a capacitor C1, a resistor R1, a capacitor C2, and a resistor R2. In the test waveform driver 52, the wirings L1 and L2 are connected, and the output of the driver 52a is supplied to the wiring L0 to which the wirings L1 and L2 are connected. A buffer is provided for each of the wirings L1 and L2. The reflected wave comparison unit 53 is configured by an operational amplifier as schematically shown in FIG. A resistor R3 is connected to the + input terminal of the amplifier AMP. A resistor R4 is provided on the feedback wiring that connects between the output terminal and the + input terminal of the amplifier AMP. The resistor R3 is provided to adjust the level between the inputs of the amplifier AMP. The operational amplifier detects a difference between input voltage values between the + input terminal and the − input terminal, and outputs a voltage value having a value corresponding to the difference value. The difference determination unit 54 is configured by a comparator or the like, and outputs a connection state determination signal indicating open detection when the output voltage value of the operational amplifier 53 exceeds a preset threshold voltage. Note that the circuit configuration shown in FIG. 3 is an example, and the present invention should not be limited to this example.

  With reference to FIG. 4, a defect isolation flow will be described. Connection confirmation is performed in accordance with the above-described configuration and procedure (S10). The reproduction test is performed both when there is a connection (when there is no open portion between the memory device and the connector) and when there is no connection (when there is an open portion between the memory device and the connector). This is because even if there is a connection, there may be an open portion other than between the memory device and the connector.

  The cause is classified as follows by the reproduction test (S20). In the case of R1, there is a problem with the memory device. In the case of R2, there is a problem with the main device. In the case of R3, it is a case of other troubles (however, including the case of connection troubles). The cause is classified as follows by the reproduction test (S30). In the case of R1, there is a problem with the memory device. In the case of R2, there is a problem with the main device. In the case of R3, it is a case of other troubles (however, a connection trouble is not included).

  As is clear from the above description, the server 100 according to the present embodiment selects the inspection wiring and the comparison wiring as a set of wiring based on the bit error determination result of the memory controller 40, and sets the set of wiring. A test waveform is input to the wiring, and by detecting the level difference of each reflected waveform detected from a set of wiring, it is detected that an unintended open portion is included in the inspection wiring. Since the detection of the bit error by the memory controller 40 is highly reliable, the open portion can be inspected depending on the result of presence / absence of the bit error. In this case, it is not necessary to separately provide a complicated controller for the server 100 for the inspection of the open portion, and the inspection of the open portion is performed with the actual machine while avoiding the complexity / high price of the configuration of the server 100. Can do. Since this connection check can be performed at the delivery destination of the server 100 after the product is shipped, it is very effective as a method for dealing with a connection failure that may occur when the memory is added.

Reference Example A reference example will be described with reference to FIGS. In this reference example, as is clear from comparison between FIG. 1 and FIG. 5, the connection changeover switch 30 and the connection confirmation circuit 50 shown in FIG. 1 are not provided in this example. Terminals T10 to T16 provided in the memory device 10 are supplied to the memory controller 40 via the terminals T20 to T26 of the connector. The bit error detection unit 41 detects a bit error based on redundant bit signal processing, as in the above-described embodiment.

  In the case of this reference example, when there is a problem with the mounting of the memory device 10 to the connector 20, a bit error is detected due to an open portion between the terminal of the memory device 10 and the terminal of the connector 20. In this case, since the memory device 10 is processed as a defective product, the yield deteriorates at the stage of incorporation into the main device. Further, as shown in FIG. 6, other problems include a connection failure between the memory device 10 and the connector 20. In the case of the above-described embodiment, it is possible to detect a mounting failure of the memory device 10 with respect to the connector 20, and thus it is possible to suppress the yield deterioration.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, a module other than the memory device may be attached to the connector. That is, the type of component connected to the connector is arbitrary.

100 servers (information processing equipment)

DESCRIPTION OF SYMBOLS 10 Memory device 20 Connector 30 Switch 40 Memory controller 41 Bit error detection part 50 Connection confirmation circuit 51 Line selection control part 52 Test waveform driver 53 Reflected wave comparison part 54 Difference determination part

Claims (8)

A connector in which a module is electrically connected through a plurality of contacts, and a plurality of bits of data are input from the module through the plurality of contacts;
Bit error determination means for determining whether or not an error has occurred in bits included in the data of a plurality of bits input through the connector and connected to the connector;
A first wiring including the contact corresponding to a bit in which an error is detected by the bit error determination means; and a second wiring including the contact corresponding to a bit in which no error is detected by the bit error determination means. A connection state determination means for inputting a test waveform and determining a state of the first wiring by evaluating a level difference between reflected waves generated in the first and second wirings according to the test waveform;
An information processing apparatus comprising:   The information processing apparatus according to claim 1, further comprising a connection switching unit that selectively switches an output destination of the connector between the bit error determination unit and the connection state determination unit.   The information processing apparatus according to claim 1, wherein the connection state determination unit inputs the test waveform having the same waveform to the first and second wirings. The connection state determination means includes
Wiring selection means for selecting the first and second wirings based on a signal supplied from the bit error determination means;
Test waveform supply means for generating the test waveform and outputting it to the first and second wirings;
Level difference detecting means connected to the first and second wirings and detecting a level difference of reflected waves generated in the first and second wirings according to the test waveform;
Level difference determination means for determining whether or not the first wiring includes an open portion based on a comparison between the level difference detected by the level difference detection means and a threshold;
The information processing apparatus according to any one of claims 1 to 3, further comprising: The module is a memory device;
5. The information processing apparatus according to claim 1, wherein the bit error determination unit specifies a bit in which an error has occurred based on a redundant bit output from the memory device. 6. . An operation method of an information processing apparatus comprising a connector to which a module is electrically connected through a plurality of contacts, and a plurality of bits of data are input from the module through the plurality of contacts,
The bit error determination means determines whether an error has occurred in the bits included in the data of a plurality of bits input through the connector,
The connection state determination means includes a first wiring including the contact corresponding to the bit in which an error is detected by the bit error determination means, and the contact corresponding to a bit in which no error is detected by the bit error determination means. A test waveform is input to the second wiring, and the state of the first wiring is determined by evaluating a level difference between reflected waves generated in the first and second wirings according to the test waveform. An operation method of the information processing apparatus.   The operation method of the information processing apparatus according to claim 6, wherein the connection state determination unit inputs the test waveform having substantially the same waveform to the first and second wirings. The module is a memory device;
8. The method of operating an information processing apparatus according to claim 6, wherein the bit error determination unit specifies a bit in which an error has occurred based on a redundant bit output from the memory device.

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