JP5447269B2 - Power semiconductor module test method - Google Patents
Power semiconductor module test methodInfo
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- JP5447269B2 JP5447269B2 JP2010174803A JP2010174803A JP5447269B2 JP 5447269 B2 JP5447269 B2 JP 5447269B2 JP 2010174803 A JP2010174803 A JP 2010174803A JP 2010174803 A JP2010174803 A JP 2010174803A JP 5447269 B2 JP5447269 B2 JP 5447269B2
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- 239000004065 semiconductor Substances 0.000 title claims description 49
- 238000010998 test method Methods 0.000 title claims description 7
- 238000001514 detection method Methods 0.000 claims description 21
- 238000012360 testing method Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 12
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- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Power Conversion In General (AREA)
- Inverter Devices (AREA)
Description
この発明は、パワー半導体モジュールに関し、特に、インバータ回路などが搭載され、この回路を構成するパワー素子の主端子間に流れる漏れ電流を正確に測定できるパワー半導体モジュールおよびその試験方法に関する。 The present invention relates to a power semiconductor module, and more particularly, to a power semiconductor module on which an inverter circuit or the like is mounted and which can accurately measure a leakage current flowing between main terminals of power elements constituting the circuit, and a test method thereof.
図１３は、３相のインバータ回路図である。このインバータ回路５１は、図示しない直流電源と、この直流電源の高電位側に接続するＰ端子８と、低電位側に接続するＮ端子９と、Ｐ端子８とＮ端子９に接続するＵ相、Ｖ相、Ｗ相の３相の上下アーム、図示しない負荷と接続し上下アームの接続点ａ，ｂ，ｃに接続する出力端子であるＵ端子１０、Ｖ端子１１、Ｗ端子１２で構成される。各アームは、例えば、ＩＧＢＴ４ａ，４ｂとこれと逆並列に接続するＦＷＤ５ａ，５ｂで構成される。また、直流電源には直流電圧を検出する電圧検出回路を構成する分圧回路２３は、直列接続された分圧抵抗２４からなり、Ｎ端子９と接続する分圧抵抗２４の電圧を検出することで、電源電圧を検出している。パワー半導体モジュール５００はインバータ回路５１を搭載し、分圧回路２３、上下アームを構成するＩＧＢＴ４ａ，４ｂ，ＦＷＤ５ａ，５ｂ、Ｐ端子８、Ｎ端子９および出力端子であるＵ端子１０、Ｖ端子１１およびＷ端子１２と、分圧回路２３を含む図示しない電源電圧検出回路や制御回路などで構成される。 FIG. 13 is a three-phase inverter circuit diagram. The inverter circuit 51 includes a DC power source (not shown), a P terminal 8 connected to the high potential side of the DC power source, an N terminal 9 connected to the low potential side, and a U phase connected to the P terminal 8 and the N terminal 9. , V-phase and W-phase three-phase upper and lower arms, U terminal 10, V terminal 11 and W terminal 12 which are output terminals connected to load points a, b and c of upper and lower arms connected to a load (not shown). The Each arm is composed of, for example, IGBTs 4a and 4b and FWDs 5a and 5b connected in reverse parallel thereto. Further, the voltage dividing circuit 23 constituting a voltage detecting circuit for detecting a DC voltage in the DC power source includes a voltage dividing resistor 24 connected in series, and detects the voltage of the voltage dividing resistor 24 connected to the N terminal 9. The power supply voltage is detected. The power semiconductor module 500 includes an inverter circuit 51, a voltage dividing circuit 23, IGBTs 4a, 4b, FWDs 5a, 5b constituting upper and lower arms, a P terminal 8, an N terminal 9, and an output terminal U terminal 10, a V terminal 11, and A power supply voltage detection circuit and a control circuit (not shown) including the W terminal 12 and the voltage dividing circuit 23 are configured.
このインバータ回路５１の各アームを構成するＩＧＢＴ４ａ，４ｂとＦＷＤ５ａ，５ｂはインバータ回路５１に組まれた後、組立作業でこれらの素子が劣化していないか否かを判定し、素子が劣化している場合には、そのパワー半導体モジュール５００を出荷しないなどの措置をとっている。 After the IGBTs 4a, 4b and FWDs 5a, 5b constituting each arm of the inverter circuit 51 are assembled in the inverter circuit 51, it is determined whether or not these elements have deteriorated during the assembly work. If the power semiconductor module 500 is present, measures such as not shipping the power semiconductor module 500 are taken.
図１４は、パワー半導体モジュール５００のＩＧＢＴとＦＷＤの漏れ電流を測定するときの回路図である。これはインバータ回路５１と分圧回路２３が搭載されたパワー半導体モジュール５００を示した回路図である。パワー半導体モジュール５００は分圧回路２３を搭載しており、図１４に示すように、漏れ電流測定回路６０を、例えば、Ｕ端子１０とＮ端子９の間に挿入すると、点線で示すように、上アームのＩＧＢＴ４ａとＦＷＤおよび分圧回路２３を通って流れる電流Ｉ５（数１００μＡ程度）が発生する。この電流Ｉ６は、被測定素子である下アームのＩＧＢＴ４ｂとＦＷＤ５ｂの主端子間に流れる漏れ電流Ｉ１と他アームの回り込みの漏れ電流Ｉ２，Ｉ３を合せた合計の電流Ｉ４（ｎＡ程度）に比べて１０5倍以上大きいために、従来はこれらを合せた電流Ｉ６が規定値以上になったときにパワー半導体モジュール５０が不良であると判定し、出荷を停止していた。 FIG. 14 is a circuit diagram when measuring leakage currents of the IGBT and FWD of the power semiconductor module 500. This is a circuit diagram showing a power semiconductor module 500 on which the inverter circuit 51 and the voltage dividing circuit 23 are mounted. The power semiconductor module 500 is equipped with a voltage dividing circuit 23. As shown in FIG. 14, when the leakage current measuring circuit 60 is inserted between the U terminal 10 and the N terminal 9, for example, A current I5 (about several hundred μA) flowing through the upper arm IGBTs 4a and FWD and the voltage dividing circuit 23 is generated. This current I6 is compared with the total current I4 (about nA), which is the sum of the leakage current I1 flowing between the main terminals of the lower arm IGBT 4b and FWD 5b, which is the element to be measured, and the leakage currents I2 and I3 of the other arms. Since it is larger by 10 5 times or more, it has been determined that the power semiconductor module 50 is defective when the combined current I6 exceeds a specified value, and the shipment is stopped.
特許文献１には、インバータ回路を構成する各アームの素子の漏れ電流を測定できる方法が開示されている。
特許文献１において、３相のインバータ回路の入力端子であるＰ端子とＮ端子にバイアス電圧印加装置を接続し、インバータ回路の入力端子（Ｐ端子またはＮ端子）と出力端子（例えば、Ｕ端子）の間に測定電圧印加装置を接続する。バイアス電圧Ｖ０＞測定電圧Ｖ１とすることで、被測定素子の漏れ電流に他アームに回り込む電流が合流するのを排除することができて、正確な漏れ電流を測定することができる。この特許文献１では、インバータ回路の各アームを構成する素子の主端子間に流れる漏れ電流を正確に測定できる方法を提供している。
Patent Document 1 discloses a method capable of measuring the leakage current of the elements of each arm constituting the inverter circuit.
In Patent Document 1, a bias voltage applying device is connected to a P terminal and an N terminal which are input terminals of a three-phase inverter circuit, and an input terminal (P terminal or N terminal) and an output terminal (for example, a U terminal) of the inverter circuit. A measuring voltage applying device is connected between the two. By setting the bias voltage V0> measurement voltage V1, it is possible to exclude the current flowing into the other arm from joining the leakage current of the device under measurement, and to measure the accurate leakage current. In this patent document 1, there is provided a method capable of accurately measuring a leakage current flowing between main terminals of elements constituting each arm of an inverter circuit.
また、特許文献２では、インバータ回路を構成するＭＯＳＦＥＴのゲート・ソース間の漏れ電流を測定する方法が開示されている。
また、特許文献３では、ビスの締め忘れ箇所を瞬時に識別できる回路基板が開示されている。
Patent Document 2 discloses a method for measuring a leakage current between the gate and source of a MOSFET constituting an inverter circuit.
Further, Patent Document 3 discloses a circuit board that can instantly identify a place where a screw is forgotten to be tightened.
また、特許文献４では、操作キーが設けられてたパネルの裏面側にプリント配線基板をネジ締めする構成において、ネジ部材の締め忘れを防止できる電子レンジについて開示されている。 Patent Document 4 discloses a microwave oven that can prevent a screw member from being forgotten to be tightened in a configuration in which a printed wiring board is screwed to the back side of a panel provided with operation keys.
しかし、前記の特許文献１では、漏れ電流を正確に測定するためには、測定電圧印加装置の他にバイアス電圧印加装置が必要となり、回路が複雑であり、装置コストが高くなる。 However, in Patent Document 1, in order to accurately measure the leakage current, a bias voltage application device is required in addition to the measurement voltage application device, the circuit is complicated, and the device cost increases.
また、特許文献２では、ゲートの漏れ電流を測定する回路については記載されているが、ＭＯＳＦＥＴのドレイン・ソース間の漏れ電流を正確に測定することについては説明されていない。 Patent Document 2 describes a circuit for measuring the leakage current of the gate, but does not describe the accurate measurement of the leakage current between the drain and source of the MOSFET.
また、特許文献３、４では、ビスの締め忘れ防止について開示されているが、インバータ回路のアームを構成する素子の主端子間の漏れ電流測定については記載されていない。
この発明の目的は、前記の課題を解決して、電圧検出回路を有するインバータ回路を搭載したパワー半導体モジュールにおいて、測定電圧のみを印加することで、インバータ回路の上下アームを構成する素子に流れる漏れ電流を簡便に正確に測定できるパワー半導体モジュールおよびその試験方法を提供することにある。
Further, Patent Documents 3 and 4 disclose prevention of screw tightening but do not describe leakage current measurement between main terminals of elements constituting the arm of the inverter circuit.
The object of the present invention is to solve the above-mentioned problems, and in a power semiconductor module equipped with an inverter circuit having a voltage detection circuit, by applying only the measurement voltage, the leakage that flows in the elements constituting the upper and lower arms of the inverter circuit An object of the present invention is to provide a power semiconductor module that can easily and accurately measure current and a test method thereof.
前記の目的を解決するために、特許請求の範囲の請求項１に記載の発明によれば、電源電圧を検出する電圧検出回路と、インバータ回路と、電源の高電位側に接続し前記インバータ回路の入力端子となるＰ端子と、電源の低電位側に接続し前記インバータ回路の入力端子となるＮ端子と、前記電圧検出回路を構成し前記Ｐ端子と前記Ｎ端子との間に接続される分圧回路と、前記インバータ回路の出力端子と、を具備し、前記分圧回路は、プリント基板に搭載され、前記分圧回路の一端を導出する前記プリント基板上の配線パターンが、導電性の接続部材を介して前記Ｐ端子に接続されることを特徴とするパワー半導体モジュールの試験方法において、前記分圧回路が搭載されたプリント基板の、前記分圧回路の一端を導出する配線パターンと前記Ｐ端子との接続を分離した状態で、前記インバータ回路の出力端子と前記インバータ回路の一方の入力端子との間に試験用の直流電圧を印加し、前記スイッチ素子がすべてオフ状態であるときに、前記インバータ回路の出力端子と前記入力端子との間に流れる漏れ電流を検出し、この漏れ電流検出値が所定値以内のパワー半導体モジュールを良品と判定し、前記配線パターンと前記Ｐ端子とを導電性の接続部材を介して接続する。 In order to solve the above object, according to the first aspect of the present invention, a voltage detection circuit for detecting a power supply voltage, an inverter circuit, and the inverter circuit connected to the high potential side of the power supply A P terminal serving as an input terminal of the power supply, an N terminal serving as an input terminal of the inverter circuit connected to a low potential side of a power source, and constituting the voltage detection circuit and connected between the P terminal and the N terminal. A voltage dividing circuit; and an output terminal of the inverter circuit. The voltage dividing circuit is mounted on a printed circuit board, and a wiring pattern on the printed circuit board that leads out one end of the voltage dividing circuit is electrically conductive. In the power semiconductor module testing method, wherein the power semiconductor module is connected to the P terminal via a connecting member, and a wiring pattern for deriving one end of the voltage dividing circuit on a printed circuit board on which the voltage dividing circuit is mounted; When a test DC voltage is applied between the output terminal of the inverter circuit and one input terminal of the inverter circuit in a state where the connection with the P terminal is separated, and all the switch elements are in an OFF state. In addition, a leakage current flowing between the output terminal of the inverter circuit and the input terminal is detected, a power semiconductor module whose leakage current detection value is within a predetermined value is determined as a non-defective product, and the wiring pattern and the P terminal Are connected via a conductive connecting member.
また、特許請求の範囲の請求項２に記載の発明によれば、電源電圧を検出する電圧検出回路と、インバータ回路と、電源の高電位側に接続し前記インバータ回路の入力端子となるＰ端子と、電源の低電位側に接続し前記インバータ回路の入力端子となるＮ端子と、前記電圧検出回路を構成し前記Ｐ端子と前記Ｎ端子との間に接続される分圧回路と、前記インバータ回路の出力端子と、を具備し、前記分圧回路は、プリント基板に搭載され、前記プリント基板に配置される配線パターンのうち、前記分圧回路の経路に配線パターンの切断箇所を設け、該切断箇所を金属性もしくは抵抗性の接続部材を介して接続することを特徴とするパワー半導体モジュールの試験方法において、前記分圧回路の経路の配線パターンが切断された状態で、前記インバータ回路の出力端子と前記インバータ回路の一方の入力端子との間に試験用の直流電圧を印加し、前記スイッチ素子がすべてオフ状態であるときに、前記インバータ回路の出力端子と前記入力端子との間に流れる漏れ電流を検出し、この漏れ電流検出値が所定値以内のパワー半導体モジュールを良品と判定し、前記配線パターン切断箇所を前記接続部材によって接続する。 According to the invention described in claim 2, the voltage detection circuit for detecting the power supply voltage, the inverter circuit, and the P terminal connected to the high potential side of the power supply and serving as the input terminal of the inverter circuit An N terminal that is connected to a low potential side of a power source and serves as an input terminal of the inverter circuit, a voltage dividing circuit that constitutes the voltage detection circuit and is connected between the P terminal and the N terminal, and the inverter An output terminal of the circuit, and the voltage dividing circuit is mounted on a printed circuit board, and among the wiring patterns arranged on the printed circuit board, a cut portion of the wiring pattern is provided in a path of the voltage dividing circuit, In the test method of a power semiconductor module, wherein the cut portion is connected through a metallic or resistive connecting member, the wiring pattern of the voltage dividing circuit path is cut and the wiring pattern is cut. When a test DC voltage is applied between the output terminal of the barter circuit and one input terminal of the inverter circuit, and all the switch elements are in the OFF state, the output terminal of the inverter circuit and the input terminal The power semiconductor module having a leakage current detection value within a predetermined value is determined as a non-defective product, and the wiring pattern cut portion is connected by the connecting member.
この発明によれば、インバータ回路の直流入力端子間に電圧検出回路を有するパワー半導体モジュールにおいて、分圧回路をインバータ回路から切り離すことができる。そして、インバータ回路の上下アームを構成する素子の漏れ電流を簡便に正確に測定できる。 According to the present invention, in the power semiconductor module having the voltage detection circuit between the DC input terminals of the inverter circuit, the voltage dividing circuit can be separated from the inverter circuit. And the leakage current of the element which comprises the upper and lower arms of an inverter circuit can be measured simply and accurately.
また、切り離しを分圧回路が搭載されたプリント基板をケースに固定するネジを外すことで行なうことで、簡単に切り離し作業とその後の結線作業を行なうことができる。
また、切り離し箇所をプリント基板に形成された分圧回路に繋がる配線に設け、切り離しをネジを用いたり、分圧抵抗の一つを用いることで、簡単に切り離し作業とその後の結線作業を行なうことができる。
Further, the separation work and the subsequent connection work can be easily performed by removing the screws that fix the printed circuit board on which the voltage dividing circuit is mounted to the case.
In addition, the separation part is provided on the wiring connected to the voltage dividing circuit formed on the printed circuit board, and the separation work and subsequent wiring work can be easily performed by using a screw or one of the voltage dividing resistors. Can do.
前記の作業を簡便にすることで、この作業によるコストアップを抑制できる。
この切り離し作業後の漏れ電流の測定で、漏れ電流が規定値以内に入っている場合は、ネジを締め直すなどして製品を完成させて、出荷することができる。
By simplifying the above work, the cost increase due to this work can be suppressed.
If the leakage current is measured within the specified value after the separation operation, the product can be completed and shipped by retightening the screws.
また、製品完成後にも簡単な方法で分圧回路が切り離せ、正確な漏れ電流測定ができる。 Even after the product is completed, the voltage divider circuit can be disconnected by a simple method, allowing accurate leakage current measurement.
実施の形態を以下の実施例で説明する。 Embodiments will be described in the following examples.
図１〜図６は、この発明の第１実施例のパワー半導体モジュールの構成図であり、図１は要部平面図、図２はプリント基板の要部平面図、図３は図１を矢印Ａの方向から見た内部の側断面図である。図４はＰ端子とＮ端子の構成図であり、同図（ａ）はＰ端子の要部平面図、同図（ｂ）は同図（ａ）を矢印Ｂの方向から見た正面図、同図（ｃ）はＮ端子の要部平面図、同図（ｄ）は同図（ｃ）を矢印Ｃの方向から見た正面図である。図５は、出力端子の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。図６は図１のＢ部および図２のＣ部の詳細図であり、同図（ａ）はＢ部の要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図、同図（ｃ）Ｃ部の拡大図である。また、図７は、図１〜図３に記載のパワー半導体モジュール１００の等価回路図である。 1 to 6 are configuration diagrams of a power semiconductor module according to a first embodiment of the present invention. FIG. 1 is a plan view of a main part, FIG. 2 is a plan view of a main part of a printed circuit board, and FIG. It is an internal side sectional view seen from the direction of A. 4 is a configuration diagram of the P terminal and the N terminal. FIG. 4A is a plan view of the main part of the P terminal, FIG. 4B is a front view of FIG. FIG. 4C is a plan view of the main part of the N terminal, and FIG. 4D is a front view of FIG. 5A and 5B are configuration diagrams of the output terminal. FIG. 5A is a plan view of the main part, and FIG. 5B is a cross-sectional view of the main part taken along line XX of FIG. 6 is a detailed view of a portion B in FIG. 1 and a portion C in FIG. 2. FIG. 6 (a) is a plan view of the main part of the portion B, and FIG. 6 (b) is an XX line in FIG. It is principal part sectional drawing cut | disconnected by (4), The same figure (c) It is an enlarged view of the C section. FIG. 7 is an equivalent circuit diagram of the power semiconductor module 100 shown in FIGS.
このパワー半導体モジュール１００は３相のインバータ回路５０とインバータ回路を構成するＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）を制御する制御回路２２で構成されている。制御回路２２は、プリント基板２１に搭載されている。また、プリント基板２１には電源電圧を検出するための回路として、分圧抵抗２３，２４からなる分圧回路と電圧検出回路２５も搭載されている。尚、ＩＧＢＴの代わりにＭＯＳＦＥＴを用いる場合もある。 The power semiconductor module 100 includes a three-phase inverter circuit 50 and a control circuit 22 that controls an IGBT (insulated gate bipolar transistor) constituting the inverter circuit. The control circuit 22 is mounted on the printed circuit board 21. The printed circuit board 21 is also equipped with a voltage dividing circuit including voltage dividing resistors 23 and 24 and a voltage detecting circuit 25 as a circuit for detecting the power supply voltage. A MOSFET may be used instead of the IGBT.
図１に示すように、一つのアームを構成する導電パターン３は、第１導電パターン３ａ〜第９導電パターン３ｉの９個からなる。これらの導電パターン３は、図３に示すように、放熱板１上に固着された導電パターン付絶縁基板２上に形成されている。導電パターン３は、インバータ回路の上アームを構成する４個の導電パターン３ａ〜３ｄと同じく下アームの一つを構成する４個の導電パターン３ｅ〜３ｈおよび出力端子が引き出される導電パターン３ｉからなる。なお、ここでは説明の重複を省くためにインバータ回路の１相分について説明するが、各相においても同様に構成されている（以下においても同様）。 As shown in FIG. 1, the conductive pattern 3 which comprises one arm consists of nine of the 1st conductive pattern 3a-the 9th conductive pattern 3i. As shown in FIG. 3, these conductive patterns 3 are formed on an insulating substrate 2 with a conductive pattern fixed on the heat sink 1. The conductive pattern 3 is composed of four conductive patterns 3e to 3h constituting one of the lower arms as well as the four conductive patterns 3a to 3h constituting the upper arm of the inverter circuit and the conductive pattern 3i from which the output terminal is drawn. . Here, in order to avoid duplication of explanation, one phase of the inverter circuit will be described, but each phase is similarly configured (the same applies hereinafter).
第１導電パターン３ａには上アームのＩＧＢＴ４ａのコレクタとこのＩＧＢ４ａと逆並列接続するＦＷＤ５ａ（還流ダイオード）のカソードが固着している。第２導電パターン３ｂには第１導電パターン３ａと接続するワイヤ６ａが固着し、第３導電パターン３ｃには、ＩＧＢＴ６ａのゲートと接続するワイヤ６ｃが固着し、第４導電パターン４ｄにはＩＧＢＴ６ａのエミッタと接続するワイヤ６ｄが固着する。 The collector of the upper arm IGBT 4a and the cathode of an FWD 5a (reflux diode) connected in reverse parallel to the IGBT 4a are fixed to the first conductive pattern 3a. A wire 6a connected to the first conductive pattern 3a is fixed to the second conductive pattern 3b, a wire 6c connected to the gate of the IGBT 6a is fixed to the third conductive pattern 3c, and an IGBT 6a is connected to the fourth conductive pattern 4d. The wire 6d connected to the emitter is fixed.
第５導電パターン３ｅには下アームのＩＧＢＴ４ｂのコレクタとこのＩＧＢ４ｂと逆並列接続するＦＷＤ５ｂのカソードが固着している。第６導電パターン３ｆにはＩＧＢＴ４ｂのエミッタとこのＩＧＢ４ｂと逆並列接続するＦＷＤ５ｂのアノードが接続するワイヤ７ｂが固着し、第７導電パターン３ｇには、ＩＧＢＴ４ｂのゲートと接続するワイヤ７ｃが固着し、第８導電パターン３ｈにはＩＧＢＴ４ｂのエミッタと接続するワイヤ７ｄが固着する。 A collector of the lower arm IGBT 4b and a cathode of the FWD 5b connected in reverse parallel to the IGBT 4b are fixed to the fifth conductive pattern 3e. A wire 7b connected to the emitter of the IGBT 4b and an anode of the FWD 5b connected in antiparallel with the IGBT 4b is fixed to the sixth conductive pattern 3f, and a wire 7c connected to the gate of the IGBT 4b is fixed to the seventh conductive pattern 3g. A wire 7d connected to the emitter of the IGBT 4b is fixed to the eighth conductive pattern 3h.
また、第９導電パターン３ｉには、ＩＧＢＴ４ａのエミッタとこのＩＧＢ４ａと逆並列接続するＦＷＤ５ａのアノードを接続するワイヤ６ｂが固着し、また、第５導電パターン３ｅと接続するワイヤ７ａが固着している。 Further, a wire 6b connecting the emitter of the IGBT 4a and an anode of the FWD 5a connected in reverse parallel to the IGBT 4a is fixed to the ninth conductive pattern 3i, and a wire 7a connected to the fifth conductive pattern 3e is fixed. .
第２導電パターン３ｂには、インバータ回路５０の図示しない電源の高電位側に接続するＰ端子８が接続し、第６導電パターン３ｆには、インバータ回路５０の電源の高電位側に接続するＮ端子９が接続する。また、第９導電パターン３ｉには、出力端子（Ｕ端子１０、Ｖ端子１１、Ｗ端子１２）が固着する。 A P terminal 8 connected to the high potential side of the power source (not shown) of the inverter circuit 50 is connected to the second conductive pattern 3b, and N connected to the high potential side of the power source of the inverter circuit 50 is connected to the sixth conductive pattern 3f. Terminal 9 is connected. Further, output terminals (U terminal 10, V terminal 11, W terminal 12) are fixed to the ninth conductive pattern 3i.
第３、第４導電パターン３ｃ、３ｄおよび第７、第８導電パターン３ｇ、３ｈは、制御端子１３に接続する。
図３に示すように、放熱板１にはケース１４を構成する枠１５が固着し、この枠１５は導電パターン付絶縁基板２を取り囲んでいる。また、この枠１５には端子台１６が埋め込まれている。この端子台１６は、後述のプリント基板２１上の配線パターンに接続される第１支柱１６ａ、Ｐ端子８に接続される第２支柱１６ｂ、第１，第２支柱を接続する支持台１６ｃで構成される。端子台１６は、第１，第２支柱を電気的に接続する導電性の部材で構成される。後述するように、第１，第２支柱にはネジ止めを行なうため、例えば銅や銅合金のような、剛性と導電性を備えた汎用的な金属材料で形成される。
The third and fourth conductive patterns 3 c and 3 d and the seventh and eighth conductive patterns 3 g and 3 h are connected to the control terminal 13.
As shown in FIG. 3, a frame 15 constituting the case 14 is fixed to the heat radiating plate 1, and the frame 15 surrounds the insulating substrate 2 with a conductive pattern. A terminal block 16 is embedded in the frame 15. The terminal block 16 includes a first support column 16a connected to a wiring pattern on the printed circuit board 21 described later, a second support column 16b connected to the P terminal 8, and a support table 16c connecting the first and second support columns. Is done. The terminal block 16 is composed of a conductive member that electrically connects the first and second columns. As will be described later, the first and second support columns are formed of a general-purpose metal material having rigidity and conductivity, such as copper or copper alloy, for screwing.
第１支柱１６ａと第２支柱１６ｂの少なくとも最上部（台座部）は枠１５から露出している。枠１５を樹脂成形によって構成する際に、第１支柱１６ａと第２支柱１６ｂの最上部（台座部）を樹脂成形の型枠で覆い、支持台１６ｃを型枠内に露出させることにより、端子台１６の露出部以外の部分が樹脂内に埋め込まれた枠１５を得ることができる。このように、枠１５に端子台１６を一体に成形することで、端子台１６を枠１５の所定位置に固定することができる。また、枠１５の上はケース１４を構成する図示しない蓋で塞がれている。 At least the uppermost part (pedestal part) of the first support column 16 a and the second support column 16 b is exposed from the frame 15. When the frame 15 is formed by resin molding, the uppermost portions (pedestal portions) of the first support column 16a and the second support column 16b are covered with a resin-molded mold frame, and the support table 16c is exposed in the mold frame to thereby form a terminal. A frame 15 in which a portion other than the exposed portion of the table 16 is embedded in the resin can be obtained. Thus, the terminal block 16 can be fixed to a predetermined position of the frame 15 by integrally forming the terminal block 16 on the frame 15. Further, the frame 15 is closed by a lid (not shown) that constitutes the case 14.
この枠１５上にはプリント基板２１が固定される。。図２に示すように、プリント基板２１には、ＩＧＢＴ４の制御回路２２、分圧回路２３、分圧回路２３の分圧抵抗２４に発生する電圧により電源電圧を検出する検出回路２５が搭載される。また、電圧検出回路２５には分圧回路２３からの電圧が入力される。また、配線パターン２８には、分圧回路２３をＰ端子８に接続するための導出部２７が形成される。 A printed circuit board 21 is fixed on the frame 15. . As shown in FIG. 2, on the printed circuit board 21, a control circuit 22 for the IGBT 4, a voltage dividing circuit 23, and a detection circuit 25 for detecting a power supply voltage based on a voltage generated in the voltage dividing resistor 24 of the voltage dividing circuit 23 are mounted. . Further, the voltage from the voltage dividing circuit 23 is input to the voltage detection circuit 25. In addition, a lead-out portion 27 for connecting the voltage dividing circuit 23 to the P terminal 8 is formed in the wiring pattern 28.
図３に示すように、制御端子１３はピン形状をしており、プリント基板２１のスルーホールを貫通して導電パターン付き絶縁基板２とプリント基板２１とを接続する。この接続によって、分圧回路２３のＮ端子側（電源の低電位側）の接続も完了する。 As shown in FIG. 3, the control terminal 13 has a pin shape, and connects the insulating substrate 2 with the conductive pattern and the printed board 21 through the through hole of the printed board 21. By this connection, the connection on the N terminal side (the low potential side of the power supply) of the voltage dividing circuit 23 is also completed.
配線パターン２８に設けられた導出部２７はその中央部分にネジ孔を有している。そして、後述の漏れ電流試験を行なった後、良品と判定された製品については、配線パターン２８の導出部２７のネジ孔にネジ２９を挿入し、ネジ２９を第１支柱１６ａのネジ孔３０に羅合する（締め付ける）。ネジ２９でプリント基板２１を第１支柱１６ａに固定することで、プリント基板２１の配線パターン２８は、導出部２７，ネジ２９を介して第１支柱ａに電気的に接続され、支持台１６ｃを介して第２支柱１６ｂに接続されたＰ端子８に接続される。このようにして、分圧回路２３はＰ端子８とＮ端子との間に接続されることになる。 The lead-out portion 27 provided in the wiring pattern 28 has a screw hole at the center thereof. Then, after a leakage current test, which will be described later, for a product determined to be non-defective, a screw 29 is inserted into the screw hole of the lead-out portion 27 of the wiring pattern 28, and the screw 29 is inserted into the screw hole 30 of the first column 16a. Combine (tighten). By fixing the printed circuit board 21 to the first support column 16a with the screw 29, the wiring pattern 28 of the printed circuit board 21 is electrically connected to the first support column a through the lead-out portion 27 and the screw 29, and the support base 16c is attached. To the P terminal 8 connected to the second support column 16b. In this way, the voltage dividing circuit 23 is connected between the P terminal 8 and the N terminal.
上記の例では、プリント基板２１の導出部２７とＰ端子８とは、それぞれ第１支柱１６ａ，第２支柱１６ｂに接続固定されたがこれに限らない。例えば、１つの支柱上にＰ端子８とプリント基板２１とをスペーサを介して重ね、１つのネジで共締めし、このネジを介してプリント基板２１の導出部２７とＰ端子８とを接続する構成としてもよい。 In the above example, the lead-out portion 27 and the P terminal 8 of the printed circuit board 21 are connected and fixed to the first support column 16a and the second support column 16b, respectively, but are not limited thereto. For example, the P terminal 8 and the printed circuit board 21 are stacked on a single support via a spacer, and are fastened together with one screw, and the lead-out portion 27 of the printed circuit board 21 and the P terminal 8 are connected through the screw. It is good also as a structure.
また、プリント基板２１の導出部２７とＰ端子８との接続にネジを用いたがこれに限らない。例えば、導出部２７のネジ孔にビスを挿入し、支柱にかしめてもよい。ただし、パワー半導体モジュールの故障原因の解析など、再び分圧回路を取り外す場合には、導出部２７とＰ端子８との接続にネジを用いた方が簡便となる。 Moreover, although the screw was used for the connection of the derivation | leading-out part 27 of the printed circuit board 21, and the P terminal 8, it does not restrict to this. For example, a screw may be inserted into the screw hole of the lead-out portion 27 and crimped to the support. However, when removing the voltage dividing circuit again, such as for analyzing the cause of failure of the power semiconductor module, it is easier to use a screw for connecting the lead-out portion 27 and the P terminal 8.
なお、図１の例では、第２支柱１６ｂとＰ端子８との接続は、図４に示すように、Ｐ端子８と一体加工で形成された補助端子８ａを、第２支柱１６ｂにネジ止めすることで行なっている。 In the example of FIG. 1, the connection between the second support column 16b and the P terminal 8 is accomplished by screwing the auxiliary terminal 8a formed integrally with the P terminal 8 to the second support column 16b as shown in FIG. It is done by doing.
図７は、パワー半導体モジュールに搭載されるインバータ回路図である。このインバータ回路５０は３相のインバータ回路である。このインバータ回路５０は、図示しない電源の高電位側に接続するＰ端子８と、低電位側に接続するＮ端子９と、Ｐ端子８に接続する上アームのＩＧＢＴ４ａおよびＦＷＤ５ａとからなる。また、Ｎ端子９に接続する下アームのＩＧＢＴ４ｂおよびＦＷＤ５ｂと、上アームと下アームの接続点ａ，ｂ，ｃに接続する出力端子（Ｕ端子１０、Ｖ端子１１、Ｗ端子１２）からなる。また、、Ｐ端子８とＮ端子９の間には分圧回路２３が接続され、Ｐ端子８と分圧回路２３の間の配線パターン２８にはネジ部２７が設けられ、このネジ部２７のネジ２９の脱着により、Ｐ端子８と分圧回路２３の切り離しと結線が行なわれる。 FIG. 7 is an inverter circuit diagram mounted on the power semiconductor module. This inverter circuit 50 is a three-phase inverter circuit. The inverter circuit 50 includes a P terminal 8 connected to the high potential side of a power source (not shown), an N terminal 9 connected to the low potential side, and an IGBT 4a and FWD 5a of the upper arm connected to the P terminal 8. Further, it comprises a lower arm IGBT 4b and FWD 5b connected to the N terminal 9, and output terminals (U terminal 10, V terminal 11, W terminal 12) connected to connection points a, b and c of the upper arm and the lower arm. A voltage dividing circuit 23 is connected between the P terminal 8 and the N terminal 9, and a screw portion 27 is provided in the wiring pattern 28 between the P terminal 8 and the voltage dividing circuit 23. By removing and attaching the screw 29, the P terminal 8 and the voltage dividing circuit 23 are disconnected and connected.
次に、上述したパワー半導体モジュール１００のインバータ回路を構成する半導体素子（ＩＧＢＴ，ＦＷＤ）の漏れ電流を測定する方法について説明する。
図８は、このパワー半導体モジュール１００のＩＧＢＴ、ＦＷＤの漏れ電流を測定する方法を説明した図である。
Next, a method for measuring the leakage current of the semiconductor elements (IGBT, FWD) constituting the inverter circuit of the power semiconductor module 100 described above will be described.
FIG. 8 is a diagram for explaining a method for measuring leakage currents of IGBTs and FWDs of the power semiconductor module 100.
まず、導出部２７にネジ２９を締結する前の、分圧回路２３がＰ端子８から切り離された状態で、Ｕ端子１０が正電位、Ｎ端子９が負電位になるように漏れ電流測定回路３１を接続する。漏れ電流測定回路３１は、内部に試験用の直流電源３２を備え、図示の極性でインバータ回路５０の各アームに直流電圧を印加する。このときインバータ回路を構成するＩＧＢＴはすべてオフ状態である。 First, a leakage current measuring circuit so that the U terminal 10 is at a positive potential and the N terminal 9 is at a negative potential in a state where the voltage dividing circuit 23 is disconnected from the P terminal 8 before the screw 29 is fastened to the lead-out portion 27. 31 is connected. The leakage current measurement circuit 31 includes a test DC power supply 32 inside, and applies a DC voltage to each arm of the inverter circuit 50 with the polarity shown in the figure. At this time, all IGBTs constituting the inverter circuit are in an off state.
次に、漏れ電流測定回路３１の電流メータ３３で電流を測定する。このとき、プリント基板の導出部２７はネジで２９で第１支柱１６ａに接続されていないため、分圧回路２３は、インバータ回路の直流入力端子であるＰ端子８とＮ端子９との間には接続されていないため、直流電源３２から分圧回路２３を介して電流が流れることがない。 Next, the current is measured by the current meter 33 of the leakage current measuring circuit 31. At this time, since the lead-out portion 27 of the printed circuit board is not connected to the first support 16a with a screw 29, the voltage dividing circuit 23 is interposed between the P terminal 8 and the N terminal 9 which are DC input terminals of the inverter circuit. Are not connected to each other, so that no current flows from the DC power source 32 via the voltage dividing circuit 23.
図８の接続では、印加された各アームには、図示矢印の経路で漏れ電流３６，３７，３８が流れる。これらの漏れ電流３６，３７，３８の合計の漏れ電流４０を電流メータ３３で測定する。 In the connection of FIG. 8, leakage currents 36, 37, and 38 flow through the applied arms along the paths indicated by the arrows. The total leakage current 40 of these leakage currents 36, 37 and 38 is measured by the current meter 33.
この漏れ電流４０の大きさが規定値以内の場合、図示の経路での漏れ電流が規定値以内と判定する。図８は、直流電源３２をＮ端子９とインバータ回路のＵ相の出力端子との間に接続したが、他の経路についても漏れ電流の以上がないかを試験するため、Ｎ端子９とインバータ回路の他の出力端子（Ｖ相，Ｗ相）間、Ｐ端子８とインバータ回路の出力端子（Ｕ相，Ｖ相，Ｗ相）間について、それぞれ漏れ電流の測定を行なう。すべての経路（例えば６通りの接続）について漏れ電流の異常がないと判定されるとそのパワー半導体モジュール１００は良品であると判定する。良品と判定されたパワー半導体モジュールは、導出部２７のネジ２９を固定して、分圧回路２３をＰ端子８に接続し、パワー半導体モジュール１００を完成させる。
一旦ネジ２９を固定した後は、通常の使用では分圧回路を再度分離することはないので、ロックペイントなどを塗布するなどして振動などでネジ２９が緩むのを防止するとよい。
When the magnitude of the leakage current 40 is within the specified value, it is determined that the leakage current in the path shown is within the specified value. In FIG. 8, the DC power source 32 is connected between the N terminal 9 and the U-phase output terminal of the inverter circuit. In order to test whether there is more leakage current in other paths, the N terminal 9 and the inverter The leakage current is measured between the other output terminals (V phase, W phase) of the circuit and between the P terminal 8 and the output terminals (U phase, V phase, W phase) of the inverter circuit. When it is determined that there is no leakage current abnormality for all paths (for example, six connections), the power semiconductor module 100 is determined to be a non-defective product. For the power semiconductor module determined to be a non-defective product, the screw 29 of the lead-out portion 27 is fixed, the voltage dividing circuit 23 is connected to the P terminal 8, and the power semiconductor module 100 is completed.
Once the screw 29 is fixed, the voltage dividing circuit is not separated again in normal use. Therefore, it is preferable to prevent the screw 29 from being loosened by vibration or the like by applying a lock paint or the like.
もし、この漏れ電流４０の大きさが規定値を超えた場合、パワー半導体モジュール１００を不良と判定して、出荷を停止する。
前記したように、電圧検出回路２５を有するインバータ回５０路を搭載したパワー半導体モジュール５００において、分圧回路２３を切り離すことで、インバータ回路５０の上下アームを構成する素子（ＩＧＢＴ４ａ，４ｂ，ＦＷＤ５ａ，５ｂ）に流れる漏れ電流を簡便に正確に測定できる。
If the magnitude of the leakage current 40 exceeds a specified value, the power semiconductor module 100 is determined to be defective and the shipment is stopped.
As described above, in the power semiconductor module 500 equipped with the inverter circuit 50 having the voltage detection circuit 25, by separating the voltage dividing circuit 23, the elements (IGBTs 4a, 4b, FWD 5a, The leakage current flowing through 5b) can be measured easily and accurately.
また、切り離しを分圧回路２３が搭載されたプリント基板２１をケース１４に固定するネジ２９を外すことで行なうことで、簡単に切り離し作業とその後の結線作業を行なうことができる。 Further, the separation work and the subsequent connection work can be easily performed by removing the screws 29 for fixing the printed circuit board 21 on which the voltage dividing circuit 23 is mounted to the case 14.
前記の作業を簡便にすることで、この作業によるコストアップを抑制できる。
この切り離し作業後の漏れ電流の測定で、漏れ電流が規定値以内に入っている場合は、ネジ２９を締め直すなどして製品を完成させて、出荷することができる。
By simplifying the above work, the cost increase due to this work can be suppressed.
If the leakage current is measured within the specified value after the separation operation, the product can be completed and shipped by retightening the screw 29 or the like.
また、製品完成後にも簡単な方法で分圧回路２３が切り離せ、正確な漏れ電流測定ができる。
また、特許文献１の方法と比べて、バイアス電圧印加装置が不要なため、設備費用が安く漏れ電流の測定も簡便である。
In addition, the voltage dividing circuit 23 can be separated by a simple method even after the product is completed, and an accurate leakage current can be measured.
Compared with the method of Patent Document 1, since a bias voltage application device is not required, the equipment cost is low and the measurement of leakage current is also simple.
図９〜図１１は、この発明の第２実施例のパワー半導体モジュールの構成図であり、図９は要部平面図、図１０はプリント基板の要部平面図、図１１は図１０のＤ部の拡大図である。第３配線パターン３ｃの隣に距離を置いて第１０配線パターン３ｊを設ける。この第１０配線パターン３ｊと第１配線パターン３ａをワイヤ６ｅで接続する。第１０配線パターン３ｊと配線パターン２８は制御端子１３ａを経由して接続している。第１導電パターン３ａは、ワイヤ６ａを介して第２導電パターン３ｂに接続し、第２導電パターン３ｂはＰ端子８に接続する。つまり、配線パターン２８はＰ端子８に接続している。 9 to 11 are configuration diagrams of a power semiconductor module according to a second embodiment of the present invention. FIG. 9 is a plan view of the main part, FIG. 10 is a plan view of the main part of the printed circuit board, and FIG. It is an enlarged view of a part. A tenth wiring pattern 3j is provided at a distance next to the third wiring pattern 3c. The tenth wiring pattern 3j and the first wiring pattern 3a are connected by a wire 6e. The tenth wiring pattern 3j and the wiring pattern 28 are connected via the control terminal 13a. The first conductive pattern 3a is connected to the second conductive pattern 3b through the wire 6a, and the second conductive pattern 3b is connected to the P terminal 8. That is, the wiring pattern 28 is connected to the P terminal 8.
この例では、配線パターン２８は、Ｐ端子（制御端子１３ａ）寄りの箇所に、配線パターンの切断箇所３１を設けている。そして、ネジ２９はプリント基板２１を指示する支柱１６ｄのネジ穴３０ａに挿入して固定する。切断箇所３１で切断された配線パターン２８は、ネジ２９により相互に接続され、分圧回路２３がＰ端子に接続される。 In this example, the wiring pattern 28 is provided with a wiring pattern cutting portion 31 at a location near the P terminal (control terminal 13a). Then, the screw 29 is inserted into the screw hole 30a of the support 16d that points to the printed circuit board 21 and fixed. The wiring patterns 28 cut at the cutting points 31 are connected to each other by screws 29, and the voltage dividing circuit 23 is connected to the P terminal.
このパワー半導体モジュール２００のＩＧＢＴ、ＦＷＤの漏れ電流を測定する方法は図８と同じである。また、第１実施例と同様の効果が得られる。
支柱１６ｄは、絶縁性の部材で形成すればよい。導体パターン付絶縁基板の空き領域に形成してもよいし、枠１５に設けてもよい。
The method for measuring the leakage current of the IGBT and FWD of the power semiconductor module 200 is the same as in FIG. Further, the same effect as in the first embodiment can be obtained.
The support 16d may be formed of an insulating member. You may form in the empty area | region of an insulated substrate with a conductor pattern, and you may provide in the frame 15. FIG.
図１２は、この発明の第３実施例のパワー半導体モジュール３００ａ、３００ｂの要部平面図である。図１１と同様に、第３配線パターン３ｃの隣に距離を置いて第１０配線パターン３ｊを設ける。この第１０配線パターン３ｊと第１配線パターン３ａをワイヤ６ｅで接続する。第１０配線パターン３ｊと配線パターン２８は制御端子４を経由して接続している。第１導電パターン３ａは、ワイヤ６ａを介して第２導電パターン３ｂに接続し、第２導電パターン３ｂはＰ端子８に接続する。つまり、配線パターン２８はＰ端子８に接続している。 FIG. 12 is a plan view of an essential part of power semiconductor modules 300a and 300b according to the third embodiment of the present invention. Similar to FIG. 11, a tenth wiring pattern 3j is provided at a distance next to the third wiring pattern 3c. The tenth wiring pattern 3j and the first wiring pattern 3a are connected by a wire 6e. The tenth wiring pattern 3j and the wiring pattern 28 are connected via the control terminal 4. The first conductive pattern 3a is connected to the second conductive pattern 3b through the wire 6a, and the second conductive pattern 3b is connected to the P terminal 8. That is, the wiring pattern 28 is connected to the P terminal 8.
この例では、配線パターン２８は、Ｐ端子（制御端子１３ａ）寄りの箇所に、配線パターンの切断箇所３２を設けている。同図（ａ）は、切断箇所３２を抵抗素子２４で接続したものである。つまり、分圧回路を構成する抵抗素子のうちの１つを接続部材として用い切断箇所を接続している。 In this example, the wiring pattern 28 is provided with a wiring pattern cutting portion 32 at a location near the P terminal (control terminal 13a). FIG. 4A shows the cutting portion 32 connected by the resistance element 24. In other words, one of the resistance elements constituting the voltage dividing circuit is used as a connection member to connect the cut portions.
また同図（ｂ）は切断箇所３２を導電バーで接続している。図１１との違いは、ネジ２９の代わりに導電バー４２で配線パターン２８を接続している。
このパワー半導体モジュール３００ａ，３００ｂのＩＧＢＴ、ＦＷＤの漏れ電流を測定する方法は図８と同じである。また、第１実施例と同様の効果が得られる。
In FIG. 5B, the cut points 32 are connected by a conductive bar. The difference from FIG. 11 is that the wiring pattern 28 is connected by a conductive bar 42 instead of the screw 29.
The method for measuring the leakage current of the IGBT and FWD of the power semiconductor modules 300a and 300b is the same as that in FIG. Further, the same effect as in the first embodiment can be obtained.
そして、漏れ電流試験を完了した後に、抵抗素子４１もしくは導電パー４２をはんだ付けもしくは導電性接着剤などで接合して、切断箇所３２を接続する。
なお、上記の各実施形態において、電圧検出回路の分圧回路をＰ端子とＮ端子との間に接続するにあたり、分圧回路のＮ端子側を先に接続し、分圧回路のＰ端子側を切り離した状態で漏れ電流試験を行なっている。これは、分圧抵抗２３，２４と電圧検出回路２５に試験用の電圧が印加される状態となるのを避けるためである。
Then, after completing the leakage current test, the resistive element 41 or the conductive par 42 is joined by soldering or a conductive adhesive, and the cut portion 32 is connected.
In each of the above embodiments, when connecting the voltage dividing circuit of the voltage detection circuit between the P terminal and the N terminal, the N terminal side of the voltage dividing circuit is connected first, and the P terminal side of the voltage dividing circuit is connected. Leakage current test is performed with the switch disconnected. This is to avoid a state in which a test voltage is applied to the voltage dividing resistors 23 and 24 and the voltage detection circuit 25.
すなわち、分圧回路のＰ端子側を先に接続し、分圧回路のＮ端子側を切り離した状態で、漏れ電流試験のためにインバータの出力端子と直流入力端子（Ｐ端子）との間に試験用の電圧を印加すると、分圧抵抗２３，２４と電圧検出回路２５に試験用の電圧が印加される状態となる。このように、分圧抵抗２３，２４と電圧検出回路２５に試験用の電圧が印加されると、インバータ回路の下アーム側を構成するＩＧＢＴの制御回路２２などの低圧側と、分圧回路のＮ端子側との試験用の電圧が加わるので、プリント基板上のパターンで上記の電圧に対して絶縁を保てる沿面距離を確保しなければならない。 That is, with the P terminal side of the voltage dividing circuit connected first and the N terminal side of the voltage dividing circuit disconnected, between the output terminal of the inverter and the DC input terminal (P terminal) for the leakage current test. When a test voltage is applied, a test voltage is applied to the voltage dividing resistors 23 and 24 and the voltage detection circuit 25. As described above, when a test voltage is applied to the voltage dividing resistors 23 and 24 and the voltage detecting circuit 25, the low voltage side such as the IGBT control circuit 22 constituting the lower arm side of the inverter circuit, and the voltage dividing circuit Since a test voltage is applied to the N terminal side, it is necessary to ensure a creepage distance that can maintain insulation against the above voltage with a pattern on the printed circuit board.
このように、プリント基板上のパターンで沿面距離を確保し、基板を大きくすることはコスト上昇の要因となる。
分圧回路のＰ端子側を切り離す構成とすることにより、漏れ電流試験のためだけに基板面積を増大、コスト上昇を避けることができる。
In this way, securing the creepage distance with the pattern on the printed circuit board and enlarging the circuit board cause an increase in cost.
By adopting a configuration in which the P terminal side of the voltage dividing circuit is separated, the substrate area can be increased only for the leakage current test, and an increase in cost can be avoided.
１ 放熱板
２ 導電パターン付絶縁基板
３ａ 第１導電パターン
３ｂ 第２導電パターン
３ｃ 第３導電パターン
３ｄ 第４導電パターン
３ｅ 第５導電パターン
３ｆ 第６導電パターン
３ｇ 第７導電パターン
３ｈ 第８導電パターン
３ｉ 第９導電パターン
３ｊ 第１０導電パターン
４ａ，４ｂ ＩＧＢＴ
５ａ，５ｂ ＦＷＤ
６ａ，６ｂ，６ｃ，６ｄ，６ｅ，７ａ，７ｂ，７ｃ，７ｄ ワイヤ
８ Ｐ端子
８ａ 補助端子
９ Ｎ端子
１０ Ｕ端子
１１ Ｖ端子
１２ Ｗ端子
１３,１３ａ 制御端子
１４ ケース
１５ 枠
１６ 端子台
１６ａ 第１支柱
１６ｂ 第２支柱
１６ｃ 支持台
２１ プリント基板
２２ 制御回路
２３、２４ 分圧抵抗
２５ 電圧検出回路
２６ ＣＰＵ
２７ 導出部
２８ 配線パターン
２９ ネジ
３０ ネジ穴
３１ 漏れ電流測定回路
３２ 電源
３３ 電流メータ
３６，３７，３８、４０ 漏れ電流
ａ，ｂ，ｃ 接続点
DESCRIPTION OF SYMBOLS 1 Heat sink 2 Insulated board | substrate with a conductive pattern 3a 1st conductive pattern 3b 2nd conductive pattern 3c 3rd conductive pattern 3d 4th conductive pattern 3e 5th conductive pattern 3f 6th conductive pattern 3g 7th conductive pattern 3h 8th conductive pattern 3i 9th conductive pattern 3j 10th conductive pattern 4a, 4b IGBT
5a, 5b FWD
6a, 6b, 6c, 6d, 6e, 7a, 7b, 7c, 7d Wire 8 P terminal 8a Auxiliary terminal 9 N terminal 10 U terminal 11 V terminal 12 W terminal 13, 13a Control terminal 14 Case 15 Frame 16 Terminal block 16a First 1 support 16b 2nd support 16c support 21 printed circuit board 22 control circuit 23, 24 voltage dividing resistor 25 voltage detection circuit 26 CPU
27 Lead-out part 28 Wiring pattern 29 Screw 30 Screw hole 31 Leakage current measuring circuit 32 Power supply 33 Current meter 36, 37, 38, 40 Leakage current a, b, c Connection point
Claims (2)
電源の高電位側に接続し前記インバータ回路の入力端子となるＰ端子と、電源の低電位側に接続し前記インバータ回路の入力端子となるＮ端子と、前記電圧検出回路を構成し前記Ｐ端子と前記Ｎ端子との間に接続される分圧回路と、前記インバータ回路の出力端子と、を具備し、A P terminal connected to the high potential side of the power supply and serving as the input terminal of the inverter circuit; an N terminal connected to the low potential side of the power supply and serving as the input terminal of the inverter circuit; and the P terminal constituting the voltage detection circuit And a voltage dividing circuit connected between the N terminal and the output terminal of the inverter circuit,
前記分圧回路は、プリント基板に搭載され、前記分圧回路の一端を導出する前記プリント基板上の配線パターンが、導電性の接続部材を介して前記Ｐ端子に接続されることを特徴とするパワー半導体モジュールの試験方法において、The voltage dividing circuit is mounted on a printed circuit board, and a wiring pattern on the printed circuit board that leads out one end of the voltage dividing circuit is connected to the P terminal via a conductive connecting member. In the test method of the power semiconductor module,
前記分圧回路が搭載されたプリント基板の、前記分圧回路の一端を導出する配線パターンと前記Ｐ端子との接続を分離した状態で、前記インバータ回路の出力端子と前記インバータ回路の一方の入力端子との間に試験用の直流電圧を印加し、前記スイッチ素子がすべてオフ状態であるときに、前記インバータ回路の出力端子と前記入力端子との間に流れる漏れ電流を検出し、この漏れ電流検出値が所定値以内のパワー半導体モジュールを良品と判定し、前記配線パターンと前記Ｐ端子とを導電性の接続部材を介して接続することを特徴とするパワー半導体モジュールの試験方法。One of the output terminal of the inverter circuit and one input of the inverter circuit in the state where the connection between the wiring pattern leading out one end of the voltage dividing circuit and the P terminal is separated on the printed circuit board on which the voltage dividing circuit is mounted A leakage current flowing between the output terminal and the input terminal of the inverter circuit is detected when a DC voltage for testing is applied between the terminals and all of the switch elements are in an off state. A method for testing a power semiconductor module, comprising: determining a power semiconductor module having a detected value within a predetermined value as a non-defective product; and connecting the wiring pattern and the P terminal via a conductive connecting member.
電源の高電位側に接続し前記インバータ回路の入力端子となるＰ端子と、電源の低電位側に接続し前記インバータ回路の入力端子となるＮ端子と、前記電圧検出回路を構成し前記Ｐ端子と前記Ｎ端子との間に接続される分圧回路と、前記インバータ回路の出力端子と、を具備し、A P terminal connected to the high potential side of the power supply and serving as the input terminal of the inverter circuit; an N terminal connected to the low potential side of the power supply and serving as the input terminal of the inverter circuit; and the P terminal constituting the voltage detection circuit And a voltage dividing circuit connected between the N terminal and the output terminal of the inverter circuit,
前記分圧回路は、プリント基板に搭載され、前記プリント基板に配置される配線パターンのうち、前記分圧回路の経路に配線パターンの切断箇所を設け、該切断箇所を金属性もしくは抵抗性の接続部材を介して接続することを特徴とするパワー半導体モジュールの試験方法において、The voltage dividing circuit is mounted on a printed circuit board, and among the wiring patterns arranged on the printed circuit board, a wiring pattern cutting portion is provided in a path of the voltage dividing circuit, and the cutting portion is connected with metal or resistance In a test method of a power semiconductor module, characterized by being connected through a member,
前記分圧回路の経路の配線パターンが切断された状態で、前記インバータ回路の出力端子と前記インバータ回路の一方の入力端子との間に試験用の直流電圧を印加し、前記スイッチ素子がすべてオフ状態であるときに、前記インバータ回路の出力端子と前記入力端子との間に流れる漏れ電流を検出し、この漏れ電流検出値が所定値以内のパワー半導体モジュールを良品と判定し、前記配線パターン切断箇所を前記接続部材によって接続することを特徴とするパワー半導体モジュールの試験方法。A test DC voltage is applied between the output terminal of the inverter circuit and one input terminal of the inverter circuit in a state where the wiring pattern of the path of the voltage dividing circuit is cut, and all the switch elements are turned off. In this state, a leakage current flowing between the output terminal of the inverter circuit and the input terminal is detected, a power semiconductor module having a leakage current detection value within a predetermined value is determined as a non-defective product, and the wiring pattern is cut A test method for a power semiconductor module, wherein the locations are connected by the connecting member.
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| DE112015006874T5 (en) | 2015-09-03 | 2018-05-30 | Mitsubishi Electric Corporation | power converter |
| WO2019098217A1 (en) * | 2017-11-17 | 2019-05-23 | アイシン・エィ・ダブリュ株式会社 | Inverter control board |
| CN114325062B (en) * | 2022-03-10 | 2022-06-10 | 杭州飞仕得科技有限公司 | Current testing method of power module |
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| JP2002158420A (en) * | 2000-11-21 | 2002-05-31 | Nec Yonezawa Ltd | Method for connecting power supply line and signal line of printed board, and electric apparatus |
| JP2005318690A (en) * | 2004-04-27 | 2005-11-10 | Sanyo Electric Co Ltd | Inverter module |
| JP2010087072A (en) * | 2008-09-30 | 2010-04-15 | Hitachi Automotive Systems Ltd | Power semiconductor module and inverter system using the same |
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2010
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