JP5389566B2 - Grid-connected inverter system - Google Patents

Description

  The present invention relates to a grid interconnection inverter system.

  Conventionally, a grid-connected inverter system that converts DC power generated by a solar cell or the like into AC power and supplies the AC power to a commercial power system has been developed.

A thin film solar cell that has been in widespread use in recent years deteriorates unless the negative electrode is grounded. Therefore, in the grid-connected inverter system A100 using the thin film solar cell, as shown in FIG. The negative electrode of 100 output lines is grounded. In countries such as the United States, it is obliged to ground one pole of a solar cell. In Figure 21, when the negative electrode of the DC power source (solar cell) 100 is grounded by a ground line L _G1, ground line L _G2 and the current path of the ground line L _G1 and the earth and the commercial electric power system 400 is formed, There is an inconvenience that a direct current flows out to the commercial power system 400 through this current path. In order to prevent this inconvenience, the grid connection regulations provide that a transformer 207 is provided at the output end of the inverter device 200, and the inverter device 200 and the commercial power system 400 are electrically insulated by the transformer 207. It has been.

  21 is a circuit that converts a DC voltage input from the DC power supply 100 into an AC voltage by switching a switching element (not shown). The filter circuit 203 is a circuit that removes switching noise included in the AC voltage output from the inverter circuit 202, and the control circuit 204 is a DC current and DC voltage input to the inverter circuit 202, and from the inverter circuit 202. A circuit that generates a PWM signal for controlling switching of the switching element in the inverter circuit 202 based on the output AC current, the AC current output from the filter circuit 203, and the AC voltage output from the transformer 207. is there.

  Due to recent changes in the world situation (Fukuda Vision at the Toyako Summit, Obama administration's Green New Deal policy, etc.), it is necessary to increase the capacity of distributed power sources such as solar cells. Therefore, in order to increase the capacity of the grid-connected inverter system to the megawatt level, as shown in FIG. 22, a plurality of grid-connected inverter systems (three in FIG. 22) connected in parallel to the commercial power system 400 Some A100s are manufactured as one grid-connected inverter system A200.

FIG. 22 shows a configuration in which three grid-connected inverter systems having the same configuration as the grid-connected inverter system A100 shown in FIG. 21 are connected in parallel. The DC power supplies 100a, 100b, and 100c are the DC power supplies shown in FIG. The inverter devices 200a, 200b, and 200c correspond to the inverter device 200 of FIG. The negative electrodes of the output lines of the DC power supplies 100a, 100b, and 100c are grounded by ground lines L _G1a , L _G1b , and L _G1c , respectively. Although not shown, each inverter device 200a, 200b, and 200c is input with a signal for synchronizing the fluctuation timing of the reactive power fluctuation method, which is an active method for detecting an isolated operation during a system power failure, for example. It has a configuration that.

  In the grid-connected inverter system A200 shown in FIG. 22, the inverter devices 200a, 200b, and 200c each have a built-in transformer 207, and the inverter devices 200a, 200b, and 200c are electrically connected to the commercial power system 400 by each transformer 207. Therefore, direct current does not flow out from the inverter devices 200a, 200b, and 200c to the commercial power system 400. In addition, since the inverter devices 200a, 200b, and 200c are also separated from each other in circuit, current does not circulate between the inverter device 200a and the inverter device 200b. The same applies to the inverter device 200b and the inverter device 200c, and the inverter device 200c and the inverter device 200a.

JP 2008-182836 A

  In the grid-connected inverter system A200 shown in FIG. 22, there is an advantage that it is possible to prevent a direct current from flowing out from the inverter devices 200a, 200b, and 200c to the ground and a circulating current between the inverter devices 200a, 200b, and 200c. However, since the inverters 200a, 200b, and 200c are each provided with the transformer 207, three transformers 207 are required. Since the transformer 207 is used at a commercial frequency (50 Hz or 60 Hz), it is generally large in size, heavy in weight, and high in unit price. Therefore, the grid-connected inverter system A200 that requires three transformers 207 has disadvantages such as an increase in the overall size, an increase in weight, and an increase in manufacturing cost. This inconvenience becomes more remarkable as the number of inverter devices connected in parallel increases.

  Further, in the transformer 207, power loss occurs due to winding resistance and iron core eddy current. Since a power loss occurs in each of the transformers 207 of the inverter devices 200a, 200b, and 200c, there is a disadvantage that the power conversion efficiency in the entire grid-connected inverter system A200 is lowered.

  The present invention has been conceived under the circumstances described above, and provides a grid-connected inverter system capable of suppressing the number of necessary transformers even when a plurality of inverter devices are connected in parallel. That is the purpose.

  In order to solve the above problems, the present invention takes the following technical means.

The grid-connected inverter system provided by the first aspect of the present invention is connected in parallel to each other, converts DC power from a DC power source into AC power, and outputs the AC power without passing through a transformer. Inverter device, and a transformer provided between a connection point on the output side of the plurality of inverter devices and the power system, and one of the pair of output ends of the DC power supply is grounded Each of the plurality of inverter devices detects a zero-phase current from a PWM control inverter circuit, a control circuit that generates a PWM signal for controlling the PWM control inverter circuit, and an output current of the PWM control inverter circuit A zero-phase current detection circuit, and any one of the control circuits of each of the inverter devices is based on a zero-phase current signal detected by the zero-phase current detection circuit. DC component extraction means for extracting a flow component, and command value signal generation means for generating a command value signal for controlling the DC component extracted by the DC component extraction means to be zero. The command value signal generated by the signal generating means is compared with the carrier signal to generate the PWM signal.

  According to this configuration, since the control circuit of each inverter device controls the DC component of the zero-phase current to be zero, even if a current path is formed between the inverter devices, the DC component circulating current Can be suppressed.

  In a preferred embodiment of the present invention, the command value signal generating means is inputted with the DC component extracted by the DC component extracting means, performs a PI control, and outputs a correction value. The deviation between the correction target value obtained by adding the correction value output from the first PI control means to the preset target value and the input voltage of the PWM control inverter circuit is input, and PI control is performed. Second PI control means for outputting a correction value and a generation circuit for generating the command value signal based on the correction value output by the second PI control means.

The grid-connected inverter system provided by the second aspect of the present invention is connected in parallel to each other, converts DC power from a DC power source into AC power, and outputs this AC power without passing through a transformer. Inverter device, and a transformer provided between a connection point on the output side of the plurality of inverter devices and the power system, and one of the pair of output ends of the DC power supply is grounded Each of the plurality of inverter devices detects a zero-phase current from a PWM control inverter circuit, a control circuit that generates a PWM signal for controlling the PWM control inverter circuit, and an output current of the PWM control inverter circuit A zero-phase current detection circuit, and any one of the control circuits of each of the inverter devices is based on a zero-phase current signal detected by the zero-phase current detection circuit. A tertiary component extracting means for extracting a secondary component; and a command value signal generating means for generating a command value signal for controlling the tertiary component extracted by the tertiary component extracting means to be zero, The PWM signal is generated by comparing the command value signal generated by the command value signal generating means with a carrier signal.

  According to this configuration, since the control circuit of each inverter device controls the third-order component of the zero-phase current to be zero, even if a current path is formed between the inverter devices, Circulating current can be suppressed.

  In a preferred embodiment of the present invention, the third-order component extracting means corresponds to a zero-phase current signal input from the zero-phase current detection circuit and a rotation angle corresponding to a frequency three times the frequency of the voltage of the power system. A rotation conversion means for calculating a converted zero-phase current signal by performing a rotation coordinate conversion of: and a filter means for extracting a DC component of the converted zero-phase current signal as a third-order component of the zero-phase current signal. The command value signal generating means is input with the tertiary component extracted by the tertiary component extracting means, performs PI control and outputs a correction value, and the correction value includes the rotation angle. Reverse rotation conversion means for performing reverse rotation coordinate conversion and calculating a conversion correction value, and generating a command value signal based on the conversion correction value calculated by the reverse rotation conversion means.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a figure for demonstrating 1st Embodiment of the grid connection inverter system which concerns on this invention. It is a figure for demonstrating 2nd Embodiment of the grid connection inverter system which concerns on this invention. It is a figure for demonstrating the current pathway formed. It is a figure for demonstrating in detail the factor which a circulating current generate | occur | produces. It is a figure for demonstrating the waveform of the zero phase current output from an inverter apparatus. It is a figure for demonstrating the circulation path | route of the circulating current of a high frequency component. It is a figure which shows the voltage waveform of an output voltage when the phase difference has generate | occur | produced in the PWM signal. FIG. 7 is an equivalent circuit diagram obtained by simplifying the circuit diagram shown in FIG. 6. It is a figure for demonstrating 3rd Embodiment of the grid connection inverter system which concerns on this invention. It is a figure for demonstrating the phase correction of a clock pulse signal. It is a figure for demonstrating the 2nd Example of 3rd Embodiment. It is a figure for demonstrating the 3rd Example of 3rd Embodiment. It is a figure for demonstrating the 4th Example of 3rd Embodiment. It is a figure for demonstrating the circulation path | route of the circulating current of a direct current component. FIG. 15 is an equivalent circuit diagram obtained by simplifying the circuit diagram shown in FIG. 14. It is a figure for demonstrating 4th Embodiment of the grid connection inverter system which concerns on this invention. It is a figure which shows another Example of 4th Embodiment. It is a figure for demonstrating 5th Embodiment of the grid connection inverter system which concerns on this invention. It is the block block diagram which added the circuit which respectively suppresses a direct current component, a tertiary component, and a high frequency component to the control circuit of the inverter apparatus. It is a figure for demonstrating the waveform of the zero phase current after a circulating current suppression measure. It is a figure for demonstrating the grid connection inverter system provided with the conventional transformer. It is a figure for demonstrating the grid connection inverter system of the structure which connected three grid connection inverter systems shown in FIG. 21 in parallel.

  Embodiments of the present invention will be specifically described below with reference to the drawings.

  FIG. 1 is a diagram for explaining a first embodiment of a grid-connected inverter system according to the present invention.

As shown in the figure, the grid-connected inverter system A includes three DC power supplies 10a, 10b, and 10c, three inverter devices 20a, 20b, and 20c, and one transformer 30. The DC power supplies 10a, 10b, and 10c are connected to inverter devices 20a, 20b, and 20c, respectively. The output terminals of the inverter devices 20a, 20b, and 20c are connected in parallel to each other. The transformer 30 is connected between the connection point of the inverter devices 20a, 20b, and 20c and the commercial power system 40. Accordingly, the grid-connected inverter system A includes a configuration in which three distributed power sources including a DC power source and an inverter device are connected in parallel to the commercial power system 40 through one transformer 30 and include a DC power source 10a. , 10b, and 10c are converted into AC power and supplied to the commercial power system 40. The commercial power system 40 is a three-phase, three-wire power system, and one of the phases (for example, the V phase) is grounded by the ground line _LG2 .

  In the first embodiment, the number of distributed power sources is three, but this is an example, and the number of units connected in parallel may be two or four or more, and can be arbitrarily set.

The DC power supplies 10a, 10b, and 10c supply DC power to the grid interconnection inverter system A, and include solar cells. The solar cell is a thin-film solar cell, and one of the output lines (the negative output line in FIG. 1) is grounded by ground lines L _G1a, L _{G1b, and} L _G1c . The solar cell is not limited to a thin film solar cell. The solar cell may be another type of solar cell other than the thin film system, and the output end of the solar cell may not be grounded. A solar cell generates direct-current power by converting solar energy into electrical energy. DC voltages output from the DC power supplies 10a, 10b, and 10c are input to the inverter devices 20a, 20b, and 20c, respectively.

Inverter 20a, 20b, 20c, respectively DC power source 10a, 10b, is converted into an AC voltage a DC voltage input from 10c, and outputs to the transformer 30. Although not shown, each inverter device 20a, 20b, 20c is input with a signal for synchronizing the fluctuation timing of the reactive power fluctuation system, which is an active system for detecting an isolated operation at the time of a system power failure, for example. The

  As shown in the figure, the inverter device 20 a includes a DC / DC converter circuit 21, an inverter circuit 22, a filter circuit 23, and a control circuit 24. In the figure, the control circuit 24 controls the inverter circuit 22, and the control circuit for controlling the DC / DC converter circuit 21 is not related to the present invention and is omitted.

The DC / DC converter circuit 21 is a step-up converter that boosts a DC voltage input from the DC power supply 10 a and outputs the boosted voltage to the inverter circuit 22. The DC / DC converter circuit 21 switches the switching element (not shown) on and off based on the PWM signal input from the control circuit 24, thereby changing the DC voltage input from the DC power supply 10a to a predetermined voltage level. Boosted to output. The configuration of the DC / DC converter circuit 21 is not limited to this, and any known boost converter may be used.

  The inverter circuit 22 converts the DC voltage input from the DC / DC converter circuit 21 into an AC voltage and outputs the AC voltage. In the first embodiment, since the commercial power system 40 is a three-phase three-wire power system, the inverter circuit 22 is a three-phase full bridge inverter. Therefore, the inverter circuit 22 through the filter circuit 23 and the transformer 30 to the commercial power system 40 are connected by three output lines of U-phase, V-phase, and W-phase output voltages. The configuration of the inverter circuit 22 is not limited to the three-phase full-bridge inverter, and may be appropriately determined according to the connected commercial power system 40 and other conditions. That is, the inverter circuit 22 may be a single-phase inverter instead of a three-phase inverter, or a half-bridge inverter instead of a full-bridge inverter.

  The inverter circuit 22 has a three-phase bridge circuit (not shown) including three arms in which two switching elements are connected in series, and each switching element is based on a PWM signal input from the control circuit 24. By switching on and off, the DC voltage input from the DC / DC converter circuit 21 is converted into an AC voltage. The AC voltage output from the inverter circuit 22 is input to the filter circuit 23.

  The filter circuit 23 removes a switching frequency component from the AC voltage input from the inverter circuit 22. The filter circuit 23 includes a low-pass filter including a reactor and a capacitor (not shown). The AC voltage from which the switching frequency component has been removed by the filter circuit 23 is output to the transformer 30. The configuration of the filter circuit 23 is not limited to this, and any known filter circuit for removing the switching frequency component may be used.

The control circuit 24 generates a PWM signal by a triangular wave comparison method that compares the command value signal with a triangular wave carrier signal, and outputs the PWM signal to the inverter circuit 22. The command value signal is a sine wave signal having a frequency close to the system frequency (50 Hz or 60 Hz). The command value signal includes a direct current and a direct voltage input to the DC / DC converter circuit 21, a direct current voltage (hereinafter referred to as “bus voltage”) output from the DC / DC converter circuit 21 (input to the inverter circuit 22). ), The AC current output from the inverter circuit 22, the AC current and AC voltage output from the filter circuit 23, and their target values. In the figure, a detection circuit for detecting the input current and input voltage to the DC / DC converter circuit 21, the bus voltage, the output current of the inverter circuit 22, the output current and output voltage of the filter circuit 23 is shown. Description is omitted.

  The carrier signal is a triangular wave having a frequency (for example, 4 kHz) that is several times or several tens of times that of the command value signal. The control circuit 24 adjusts the output voltage of the inverter circuit 22 by controlling the operation of the inverter circuit 22 (switching on and off of each switching element) with the PWM signal.

  Although not shown in the figure, the internal configuration of the inverter devices 20b and 20c is the same as that of the inverter device 20a.

  The transformer 30 boosts the AC voltage output from the inverter devices 20a, 20b, and 20c to a voltage for supplying the commercial power system 40. Moreover, the transformer 30 is connected between the connection point on the output side of the three inverter devices 20a, 20b, and 20c connected to each other and the commercial power system 40, and the inverter devices 20a, 20b, and 20c are connected to each other. It is electrically insulated from the commercial power system 40.

  As described above, in the first embodiment, the transformer 30 is connected between the connection point on the output side of the three inverter devices 20a, 20b, and 20c connected to each other and the commercial power system 40. In each inverter device 20a, 20b, 20c, no transformer is provided. Therefore, compared with the case where the transformers 207 are provided in the respective inverter devices 200a, 200b, and 200c as in the conventional grid-connected inverter system A200 (see FIG. 22), the grid-connected inverter system A includes the transformers. The number can be reduced to one. Thereby, compared with the conventional grid connection inverter system A200, the whole size can be reduced, the weight can be reduced, and the manufacturing cost can be suppressed.

  Further, in the conventional grid-connected inverter system A200, the inverters 200a, 200b, and 200c are each provided with the transformer 207, and thus the power loss due to the transformer 207 occurs in each of the inverter devices 200a, 200b, and 200c. In the interconnected inverter system A, only power loss is caused by one transformer 30. Therefore, even if the transformer 30 is structurally somewhat larger than the transformer 207 provided in each conventional inverter device 200a, 200b, 200c, the power loss in the transformer 30 is reduced by the three transformers 207. Compared with the conventional grid-connected inverter system A200, the overall power conversion efficiency can be improved.

  In addition, although the said 1st Embodiment demonstrated the case where another DC power supply 10a, 10b, 10c was each connected to each inverter apparatus 20a, 20b, 20c, it is not restricted to this. As shown in FIG. 2, the configuration may be such that the output of one DC power supply 10 is distributed and input to the inverter devices 20a, 20b, and 20c.

  FIG. 2 is a diagram for explaining a second embodiment of the grid-connected inverter system according to the present invention. In the figure, the same or similar elements as those in the grid interconnection inverter system A shown in FIG.

System interconnection inverter system A 'shown in FIG. 2 is that the three inverters device 20a to one of the DC power supply 10 (the negative electrode is grounded by a ground line L _G1), 20b, 20c are connected in parallel Thus, it is different from the grid interconnection inverter system A. In the figure, the description of the internal configuration of the inverter devices 20a, 20b, and 20c is omitted (the same applies to FIG. 3).

  In the second embodiment, in addition to the operational effects of the first embodiment described above, the output power of the DC power supply 10 is shared by other inverter devices even when any of the inverter devices 20a, 20b, 20c fails. Power can be converted. In addition, the number of operating inverter devices can be adjusted according to the output power of the DC power supply 10. Furthermore, it is possible to reduce the number of wires from the DC power supply to the inverter device as compared with the case where a plurality of DC power sources are connected to different inverter devices. Therefore, when the DC power supply and the inverter device are installed apart from each other, it is possible to reduce the man-hours for installing the system.

  Incidentally, in the grid-connected inverter systems A and A ′ according to the present invention shown in FIG. 1 and FIG. 2, the inverter devices 20a, 20b, and 20c are not provided with a transformer, and the inverter devices 20a, 20b, and 20c are not provided. Are connected to each other, and the negative ends of the input terminals of the inverter devices 20a, 20b, and 20c are connected to each other. For example, current circulates between the inverter device 20a and the inverter device 20b. A current path is formed. Similarly, a current path through which current circulates is formed between the inverter device 20b and the inverter device 20c and between the inverter device 20c and the inverter device 20a.

  FIG. 3 is a diagram for explaining a current path formed between the inverter device 20a and the inverter device 20b.

  Since the negative electrode a of the DC power supply 10a is grounded to the ground G and the negative electrode b of the DC power supply 10b is also connected to the ground G, the negative electrode a and the negative electrode b are electrically connected. Since one input terminal of the inverter device 20a is connected to the negative electrode a of the DC power supply 10a and one input terminal of the inverter device 20b is connected to the negative electrode b of the DC power supply 10b, the inverter device 20a and the inverter device 20b are connected. Are electrically connected on the input side. Further, for example, the U-phase output line of the inverter device 20a and the U-phase output line of the inverter device 20b are connected at the connection point c, so that the inverter device 20a and the inverter device 20b are electrically connected on the output side. It is connected to the. Therefore, a current path (thick line path shown in the figure) of the negative electrode a, the inverter device 20a, the connection point c, the inverter device 20b, and the negative electrode b is formed.

  For example, when the output power of the DC power supply 10a is larger than the output power of the DC power supply 10b, the output voltage of the inverter device 20a becomes higher than the output voltage of the inverter device 20b, and the circulating current I flows through the current path shown by the thick line in FIG. . As a result, the output power of the inverter device 20b decreases. The above phenomenon also occurs between the inverter device 20b and the inverter device 20c and between the inverter device 20c and the inverter device 20a.

  FIG. 4 is a diagram for explaining in detail the factors that cause the circulating current. In FIG. 1, the DC / DC converter circuit 21, the inverter circuit 22, and the filter circuit 23 of the inverter devices 20a and 20b in FIG. 1 are a boost chopper unit, a three-phase full bridge inverter unit, and an LCL filter unit, respectively. The circuit diagram of the inverter apparatuses a and b in the case is shown. In order to simplify the description, the boost chopper section has the same characteristics, the switching elements Q1 to Q6 of the inverter device a, and the switching patterns Q1 to Q6 of the inverter device b have the same switching pattern. Focus only on the states of Q1 and Q2. The description here is only an example of the circulating current. Actually, the circulating current is generated through a variety of paths depending on the combination of the switching patterns of the step-up chopper section and the three-phase full-bridge inverter section.

  Considering the state where the switching element Q1 is on and the switching element Q2 is off between the inverter devices a and b, the energy is stored in the filter LCL1 from the DC power supply side through the step-up chopper unit. (See FIG. 4 (a)). Here, when a difference is generated between the input powers Pin1 and Pin2 from the DC power source, a difference is generated in the energy accumulated in the filter LCL1 in each of the inverter devices a and b.

Next, consider a case where the switching element Q1 is turned off and Q2 is turned on (see FIG. 4B). In this case, the circulating current path shown in the figure is formed (thick line path shown in the figure). When there is no power difference between the input powers Pin1 and Pin2 from the DC power supply, a potential difference (= V _L1 −V _L2 [V]) due to the accumulated energy difference does not occur in the voltage across the filter LCL1 in each inverter device a and b. . Therefore, even if a circulating current path is formed, no circulating current is generated, and all the accumulated energy of each filter LCL1 is output to the system side. When conversion loss is not taken into consideration, output power Pout [W] = Pin1 + Pin2 [W]. However, if there is a power difference between the input powers Pin1 and Pin2 from the DC power supply, a potential difference (= V _L1 −V _L2 [V] due to the accumulated energy difference between the voltages at both ends of the filter LCL1 in each inverter device a and b. ) Occurs. Due to this potential difference, a circulating current is generated between the inverter devices a and b via the circulating current path shown in the figure. Therefore, if the power for the circulating current is Ploop, Pout [W] = Pin1 + Pin2−Ploop [W], and the conversion efficiency is significantly reduced depending on the magnitude of the circulating current.

  FIG. 5 is a diagram for explaining the waveform of the zero-phase current Iz output from the inverter device 20a.

The sinusoidal waveform shown in the upper part of FIG. 5 shows an example of the waveform of the U-phase current Iu output from the U-phase output line of the inverter device 20a. Since the circulating current I is superimposed on the U-phase current Iu, it is not an ideal sine wave. The waveforms of the V-phase current and the W-phase current output from the V-phase and W-phase output lines are similar. On the other hand, the sinusoidal waveform shown in the lower part of FIG. 5 shows an example of the waveform of the zero-phase current Iz output from the inverter device 20a when the circulating current I flows. Zero-phase current Iz is obtained by adding the U-phase current Iu, V-phase current Iv, and W-phase current Iw, a DC power source 10a, 10b, 10c and the inverter device 20a, 20b, 20 c electrostatic against the ground If the capacity is negligible, the zero-phase current Iz can be regarded as the circulating current I. The zero-phase current Iz ′ when the circulating current I is not flowing becomes zero as shown by the dotted line in FIG.

  There are three types of current flowing as a circulating current: a direct current component, a third harmonic component of the U-phase current Iu, and a high-frequency component having a switching frequency (the frequency of the carrier signal, for example, 4 kHz). The current Iz becomes a mixed alternating current. Therefore, as shown in FIG. 5, the zero-phase current Iz when the circulating current I is flowing is a DC component Iave in which a high-frequency component having the frequency of the carrier signal is superimposed on the third-order harmonic component of the U-phase current Iu. The AC signal varies in amplitude around the level of.

  In the present invention, a configuration for suppressing these circulating currents superimposed on the zero-phase current Iz is incorporated in each of the inverter devices 20a, 20b, and 20c. Specifically, each inverter device 20a, 20a, 20b, and 20c has a feedback control system that suppresses the above-described third-order component and high-frequency component included in the zero-phase current Iz of the output current output from each inverter device 20a, 20b, 20c. 20b and 20c are provided in the control circuits 24, respectively, and the phase of the PWM signal output from each control circuit 24 is matched to suppress the DC component.

  Next, a third embodiment including a control circuit incorporating a configuration for suppressing high frequency components will be described. First, the cause of the flow of the high-frequency component zero-phase current Iz will be described.

FIG. 6 is a diagram for explaining the circulation path of the circulating current of the high-frequency component. This figure is a circuit diagram in which DC power supplies 10a and 10b are added to the circuit diagram shown in FIG. In order to simplify the description, the input voltage from the DC power supply is the same (Vin1 = Vin2), the step-up chopper unit is stopped, and attention is paid only to the states of the switching elements Q1 and Q2 of the inverter devices a and b. When switching element Q1 of inverter device a and switching element Q1 of inverter device b are switched on and off at the same timing (both switching element Q2 of inverter device a and switching element Q2 of inverter device b are at the same timing) The voltage at the points Va and Vb of the inverter devices a and b (hereinafter referred to as “output voltages Va and Vb”) is set to Vin1 (= Vin2) or the ground potential. since the fixed, circulating current does not occur. Here, when the switching timings of the switching elements Q1 and Q2 of the inverter devices a and b do not coincide with each other, that is, when a phase difference occurs in the PWM signal input to the inverter devices a and b. Think.

  FIG. 7 shows voltage waveforms of the output voltages Va and Vb when a phase difference is generated in the PWM signals input to the inverter devices a and b. As shown in the figure, there is a voltage difference between the output voltages Va and Vb in the period P1 and the period P3 due to the phase difference between the input PWM signals.

  Here, description will be given focusing on only the period P1 shown in FIG. Va rises (ie, switching element Q1 of inverter device a is on and switching element Q2 is off) while Va and Vb continue to be zero (that is, switching element Q1 of inverter device b is off and switching element Q2 is on). This state will be described with a simplified equivalent circuit diagram.

  FIG. 8 is a simplified equivalent circuit diagram in a state where Vb in FIG. 6 is zero. In the figure, only the L component is described for the filter LCL1, the inductance value of the filter LCL1 of the inverter device a is La, and the inductance value of the filter LCL1 of the inverter device b is Lb.

FIG. 5A shows a state where Va and Vb are both zero. As an initial condition, La and Lb are assumed to have no energy accumulation (initial current is zero). When a transition is made from this state to the period P1 (ie, Q1 is on and Q2 is off), a circulating current I _loop is generated via La and Lb by applying the DC power supply voltage Vin1 between Va and Vb. (Refer to (b) in the figure). The circulating current I _loop at this time is calculated by the following equation (2) based on the well-known equation (1) showing the characteristics of the inductor.

  As is apparent from the above equation (2), the peak value of the high-frequency circulating current increases as t increases (the phase difference of the PWM signal increases and the state shown in FIG. 2B continues longer).

  Therefore, in the period P1, since the output voltage Va of the inverter device a is higher than the output voltage Vb of the inverter device b, a circulating current flows from the inverter device a to the inverter device b. On the other hand, in the period P3, since the output voltage Vb is higher than the output voltage Va in the period P3, a circulating current flows from the inverter device b to the inverter device a. In the periods P2 and P4, since the output voltage Va and the output voltage Vb are the same potential, no circulating current flows between the inverter device a and the inverter device b. When the frequency (switching frequency) of the PWM signal is 4 kHz, for example, the time from the period P1 to P4 is (1/4000) seconds, so the circulating current flowing from the inverter device 20a to the inverter device 20b is a high frequency current of 4 kHz. Therefore, when the phase of the PWM signal does not match, a high-frequency circulating current having the frequency of the PWM signal is superimposed on the output current. As a result, the zero-phase current Iz is superimposed with a circulating current of a high-frequency component (see FIG. 5).

  In 3rd Embodiment, the circulating current of the high frequency component of switching frequency is suppressed by making the phase of the PWM signal output from the control part 24 of each inverter apparatus 20a, 20b, 20c correspond. In the third embodiment, the inverter device 20a comprehensively controls the inverter devices 20b and 20c, the inverter device 20a corresponds to the “master inverter device” of the present invention, and the inverter devices 20b and 20c “ Corresponds to "slave inverter device".

  FIG. 9 is a diagram for explaining a third embodiment of the grid-connected inverter system according to the present invention. In the figure, only a part of the internal configuration of the control circuit 24 is shown. The configuration other than the control circuit 24 is the same as that of the grid interconnection inverter system A shown in FIG. In the figure, the control circuits 24 of the inverter devices 20a, 20b, and 20c are control circuits 24a, 24b, and 24c, respectively.

  The control circuit 24a includes an internal oscillation unit 1a, a carrier signal generation unit 2a, a PWM signal generation unit 3a, and a phase correction unit 4a. The internal oscillation unit 1a generates a clock pulse signal CLK having a predetermined frequency (for example, 4 kHz). The internal oscillator 1a outputs the generated clock pulse signal CLK to the carrier signal generator 2a and the phase corrector 4a. The carrier signal generation unit 2a generates the carrier signal CR based on the clock pulse signal CLK input from the internal oscillation unit 1a. The carrier signal generation unit 2a outputs the generated carrier signal CR to the PWM signal generation unit 3a.

  The PWM signal generation unit 3a generates the PWM signal PWM1 by the triangular wave comparison method from the carrier signal CR input from the carrier signal generation unit 2a and the command value signal input from the command value signal generation unit (not shown). is there. The PWM signal generation unit 3a outputs the generated PWM signal PWM1 to the inverter circuit 22. The command value signal generator generates a command value signal for each phase (U phase, V phase, W phase) and outputs the command value signal to the PWM signal generator 3a. The PWM signal generation unit 3a generates three PWM signals for each phase by comparing the command value signal for each phase with the carrier signal CR. The PWM signal generation unit 3a also generates a PWM signal obtained by inverting each of the three generated PWM signals. The PWM signal PWM1 is represented as a signal including these six PWM signals.

  The phase correction unit 4a generates a clock pulse signal CLK 'in which the phase of the clock pulse signal CLK input from the internal oscillation unit 1a is advanced. The phase correction unit 4a outputs a clock pulse signal CLK 'to the control circuits 24b and 24c. In the third embodiment, input / output of signals between the control circuits 24a, 24b, and 24c is performed via the I / O ports. In this case, the phase of the signal is delayed by an element such as a photocoupler. The phase correction unit 4a generates a clock pulse signal CLK 'whose phase is advanced from the clock pulse signal CLK in order to correct the phase delay.

  FIG. 10 is a diagram for explaining the phase correction of the clock pulse signal CLK. FIG. 5A shows the clock pulse signal CLK output from the internal oscillation unit 1a. FIG. 4B shows the clock pulse signal CLK ′ output from the phase correction unit 4a. The phase of the clock pulse signal CLK ′ is advanced by a predetermined value θ from the clock pulse signal CLK. The predetermined value θ is set in advance to an appropriate value by experiment according to the phase delay of the signal through the I / O port. FIG. 4C shows a clock pulse signal CLK ″ input to carrier signal generators 2b and 2c (described later) of the control circuits 24b and 24c. The signal output from the control circuit 24a is the control circuit 24b. , 24c, the phase is delayed by θ, so that the phase of the clock pulse signal CLK ″ is delayed by a predetermined value θ from the clock pulse signal CLK ′. As a result, the clock pulse signal CLK ″ having the same phase as the clock pulse signal CLK input to the carrier signal generation unit 2a is input to the carrier signal generation units 2b and 2c.

  Returning to FIG. 9, the control circuit 24b includes a carrier signal generation unit 2b and a PWM signal generation unit 3b. The carrier signal generation unit 2b and the PWM signal generation unit 3b perform the same functions as the carrier signal generation unit 2a and the PWM signal generation unit 3a of the control circuit 24a. The carrier signal generation unit 2b receives the clock pulse signal CLK ″ whose phase is delayed from the clock pulse signal CLK ′ output from the phase correction unit 4a. As described above, the clock pulse signal CLK ′ is an internal oscillator. The clock pulse signal CLK output from the unit 1a is a signal obtained by advancing in advance by the phase θ delayed at the time of input / output between the control circuits 24a, 24b, 24c. Therefore, the clock pulse signal CLK ″ is the clock pulse signal The signal is in phase with CLK. Accordingly, the phase of the PWM signal PWM2 generated by the PWM signal generation unit 3b matches the phase of the PWM signal PWM1 generated by the PWM signal generation unit 3a.

  The control circuit 24c includes a carrier signal generation unit 2c and a PWM signal generation unit 3c. The carrier signal generation unit 2c and the PWM signal generation unit 3c perform the same functions as the carrier signal generation unit 2a and the PWM signal generation unit 3a of the control circuit 24a. Since the clock pulse signal CLK ″ input to the carrier signal generation unit 2c is also a signal in phase with the clock pulse signal CLK, the phase of the PWM signal PWM3 generated by the PWM signal generation unit 3c is PWM signal generation. This coincides with the phase of the PWM signal PWM1 generated by the unit 3a.

  Also in 3rd Embodiment, since the number of the transformers used for a system can be suppressed, there can exist an effect similar to the said 1st and 2nd embodiment. Furthermore, in the third embodiment, the phases of the PWM signals PWM1, PWM2, and PWM3 output from the control circuits 24a, 24b, and 24c, respectively, match. Therefore, even if the current path of the circulating current is formed between the inverter devices 20a, 20b, and 20c, the circulating current of the high frequency component of the switching frequency can be suppressed. As a result, the circulating current of the high frequency component superimposed on the zero phase current Iz is suppressed.

  In the third embodiment, the case where the phase delay of the signal output from the control circuit 24a to the control circuit 24b is the same as the phase delay of the signal output from the control circuit 24a to the control circuit 24c will be described. However, if the delay phases are different, the phases may be corrected according to the respective delay phases. That is, a phase correction unit that corrects the phase delay of the signal output from the control circuit 24a to the control circuit 24b, and a phase correction unit that corrects the phase delay of the signal output from the control circuit 24a to the control circuit 24c. What is necessary is just to provide.

  FIG. 11 illustrates another example of the third embodiment (hereinafter, the example illustrated in FIG. 9 described above is referred to as a first example, and this example is referred to as a second example). FIG. In the figure, the same or similar elements as those in the first embodiment shown in FIG.

  The second embodiment shown in FIG. 11 differs from the first embodiment in that two phase correction units are provided. The phase correction unit 41a generates a clock pulse signal CLK1 ′ in which the phase of the clock pulse signal CLK input from the internal oscillation unit 1a is advanced by the delay phase θ ′ of the signal output from the control circuit 24a to the control circuit 24b. Output. The clock pulse signal CLK1 ′ output from the phase correction unit 41a is input to the carrier signal generation unit 2b as the clock pulse signal CLK1 ″ delayed by the phase θ ′. The clock pulse signal CLK1 ″ is the same as the clock pulse signal CLK. Since the signals match in phase, the phase of the PWM signal PWM2 generated by the PWM signal generation unit 3b matches the phase of the PWM signal PWM1 generated by the PWM signal generation unit 3a.

  The phase correction unit 42a generates a clock pulse signal CLK2 ′ in which the phase of the clock pulse signal CLK input from the internal oscillation unit 1a is advanced by the delay phase θ ″ of the signal output from the control circuit 24a to the control circuit 24c. The clock pulse signal CLK2 ′ output from the phase correction unit 42a is input to the carrier signal generation unit 2c as the clock pulse signal CLK2 ″ delayed by the phase θ ″. The clock pulse signal CLK2 ″. Becomes a signal in phase with the clock pulse signal CLK, so the phase of the PWM signal PWM3 generated by the PWM signal generation unit 3c matches the phase of the PWM signal PWM1 generated by the PWM signal generation unit 3a.

  In the second embodiment, control is performed even when the delay phase θ ′ of the signal output from the control circuit 24a to the control circuit 24b is different from the delay phase θ ″ of the signal output from the control circuit 24a to the control circuit 24c. The phases of the PWM signals PWM1, PWM2, and PWM3 output from the circuits 24a, 24b, and 24c can be made to coincide with each other, and the circulating current of the high frequency component of the switching frequency can be suppressed. The circulating current of the superimposed high frequency component is suppressed.

  In the first and second embodiments, the case where the phase correction unit is provided in the control circuit 24a on the clock pulse signal output side is described. However, the control circuit 24b on the clock pulse signal input side is described. , 24c may be provided with a phase correction unit.

  FIG. 12 is a diagram for explaining a third example of the third embodiment. In the figure, the same or similar elements as those in the second embodiment shown in FIG.

  In the third embodiment shown in FIG. 12, in place of the phase correction units 41a and 42a provided in the control circuit 24a, the phase correction units 4b and 4c are provided in the control circuits 24b and 24c, respectively. Different from the example.

  Even in the third embodiment, even when the delay phase θ ′ of the signal output from the control circuit 24a to the control circuit 24b is different from the delay phase θ ″ of the signal output from the control circuit 24a to the control circuit 24c, the control is performed. The phases of the PWM signals PWM1, PWM2, and PWM3 output from the circuits 24a, 24b, and 24c can be made to coincide with each other, and the circulating current of the high frequency component of the switching frequency can be suppressed. The circulating current of the superimposed high frequency component is suppressed.

  In the first to third embodiments, the case where the clock pulse signal is output from the control circuit 24a to the control circuits 24b and 24c has been described. However, a carrier signal may be output.

  FIG. 13 is a diagram for explaining a fourth example of the third embodiment. In the figure, the same or similar elements as those in the first embodiment shown in FIG.

  In the fourth embodiment shown in FIG. 13, instead of the phase correction unit 4 a advancing and outputting the phase of the clock pulse signal CLK, the carrier phase correction unit 4 a ′ advances and outputs the phase of the carrier signal CR. The circuit 24b, 24c is different from the first embodiment in that the carrier signal generators 2b, 2c are not provided.

  The carrier phase correction unit 4a 'generates a carrier signal CR' in which the phase of the carrier signal CR input from the carrier signal generation unit 2a is advanced by a predetermined value θ. The carrier phase correction unit 4a 'outputs the carrier signal CR' to the control circuits 24b and 24c. The PWM signal generation units 3b and 3c receive a carrier signal CR "delayed by a phase θ from the carrier signal CR 'output from the carrier phase correction unit 4a'. The carrier signal CR" is phase-shifted with the carrier signal CR. Are the same signals. As a result, the phases of the PWM signals PWM2 and PWM3 generated by the PWM signal generation units 3b and 3c coincide with the phase of the PWM signal PWM1 generated by the PWM signal generation unit 3a.

  Also in the fourth embodiment, the phases of the PWM signals PWM1, PWM2, and PWM3 output from the control circuits 24a, 24b, and 24c can be matched, and the circulating current of the high-frequency component of the switching frequency can be suppressed. As a result, the circulating current of the high frequency component superimposed on the zero phase current Iz is suppressed. In the fourth embodiment, similarly to FIG. 11, two carrier phase correction units are provided in the control circuit 24a, and the carrier signal CR is advanced by the corresponding phases θ ′ and θ ″, respectively. Alternatively, the carrier phase correction unit may be provided in each of the control circuits 24b and 24c in the same manner as in FIG.

  The clock pulse signal CLK input from the internal oscillation unit 1a of the control circuit 24a to the carrier signal generation unit 2a and the clock pulse signal input to the carrier signal generation units 2b and 2c in the control circuits 24b and 24c, respectively. When the phase shift is small and the phase difference between the PWM signals generated by the PWM signal generation units 3a, 3b, and 3c caused by the phase shift is not particularly problematic, the phase correction unit can be omitted. Similarly, when the phase difference between the PWM signals generated by the PWM signal generation units 3a, 3b, and 3c is not particularly problematic, the carrier phase correction unit is omitted in the case where the phase difference is caused by the carrier signal phase shift. Can do.

In the third embodiment, the case where three inverter devices are connected in parallel is described. However, the present invention is applied even when there are two inverter devices or four or more inverter devices connected. Can do. Even when separate DC power supplies are connected to the respective inverter devices (see FIG. 1), the present invention can be applied to the case where the output of one DC power supply is distributed and input to each inverter device (see FIG. 2). Can be applied.

  Next, a fourth embodiment of the grid-connected inverter system according to the present invention will be described.

  FIG. 14 is a diagram for explaining the circulation path of the circulation current of the DC component. This figure is different from the circuit diagram shown in FIG. 6 only in the circulation path of the circulating current indicated by a bold line. For simplification of explanation, the characteristics on the DC power supply side are assumed to be the same (the output power is the same), and the switching patterns of the three-phase full-bridge inverter portions of the inverter devices a and b are also assumed to be the same. The difference between the inverter devices a and b is only the bus voltage difference. The bus voltages are the voltages Vbus1 and Vbus2 across the capacitor C1 in the inverter devices a and b shown in FIG. In order to make this bus voltage constant, switching of the step-up chopper section and the three-phase full-bridge inverter section is controlled.

At this time, if a difference occurs in the bus voltage of the inverter devices a and b due to a control error due to variations in the bus voltage detection circuit, for example, the bus voltage Vbus1 of the inverter device a is higher than the bus voltage Vbus2 of the inverter device b ( Vbus1> Vbus2), a circulating current I _loop flowing through the thick circulation path shown in FIG. In addition, the circulation path shown in FIG. 14 is a thing at the time of paying attention only to the state of switching element Q1, Q2. As described above, when the states of the switching elements are limited, the circuit diagram shown in FIG. 14 can be converted into the equivalent circuit diagram shown in FIG. In the figure, the step-up chopper part including the capacitor C1 of the inverter devices a and b is replaced with an ideal DC power supply and an internal resistance, the filter LCL1 is replaced only with the L component, and the inductance of the filter LCL1 of the inverter device a The value is La, and the inductance value of the filter LCL1 of the inverter device b is Lb.

  Considering the case of Vbus1 = Vbus2, since the switching patterns of the switching elements Q1 and Q2 of the inverter devices a and b are the same, no circulating current is generated between the inverter devices a and b. However, when Vbus1> Vbus2, a circulating current is generated from the inverter devices a to b with the switching element Q1 on and Q2 off as shown in FIG. At this time, when Q1 of the switching elements of the inverter devices a and b are simultaneously switched off and Q2 is switched on, the inverter devices a to b are continued by the inductance action of La and Lb as shown in FIG. Circulating current flows in the same direction. In other words, by alternately switching the states of FIG. 5A and FIG. 5B, a DC component circulating current flowing in the same direction is continuously generated.

  Therefore, the DC component circulating current superimposed on the zero-phase current Iz (see FIG. 5) is generated when a difference occurs between the bus voltages of the inverter devices 20a, 20b, and 20c. In the fourth embodiment, in each of the inverter devices 20a, 20b, and 20c, a DC component is extracted from the zero-phase current Iz of the output current, and a correction value for performing feedback control to zero is added to the target value of the bus voltage. By doing so, the circulating current of the DC component is suppressed.

  FIG. 16 is a diagram for explaining a fourth embodiment of the grid-connected inverter system according to the present invention. Only the internal configuration of the inverter device 20a is shown in FIG. The internal configuration of the inverter devices 20b and 20c is the same as that of the inverter device 20a, and the other configuration is the same as that of the grid interconnection inverter system A shown in FIG. Also, the description of the internal configuration of the control circuit 24 that is not particularly related to the above-described main points of the fourth embodiment (such as the internal oscillation unit 1a and the carrier signal generation unit 2a) is omitted.

  In the inverter device 20a shown in the figure, a zero-phase current detection circuit 26 is provided on the output side of the filter circuit 23. The zero-phase current detection circuit 26 detects the alternating current of each phase (U-phase, V-phase, W-phase) output from the filter circuit 23 and adds the detected alternating current signal of each phase to the zero-phase. A current signal is generated and output to the control circuit 24. The bus voltage detection circuit 25 detects the bus voltage output from the DC / DC converter circuit 21, and outputs the detected bus voltage signal to the control circuit 24. The detection that is not shown in FIG. Circuit.

  The control circuit 24 includes a DC component extraction unit 5, a command value signal generation unit 6, and a PWM signal generation unit 3. The direct current component extraction unit 5 removes an alternating current component from the zero phase current signal input from the zero phase current detection circuit 26 and extracts a direct current component, and includes a low-pass filter. The DC component extraction unit 5 outputs the extracted DC component of the zero-phase current signal to the command value signal generation unit 6.

  The command value signal generation unit 6 includes a bus voltage signal input from the bus voltage detection circuit 25, a bus voltage target value that is a target value thereof, and a DC component of a zero-phase current signal input from the DC component extraction unit 5. From this, a command value signal is generated and output to the PWM signal generating unit 3.

  The command value signal generation unit 6 includes PI control units 61 and 62 and a current control unit 63. The PI control unit 61 is for feedback control of the DC component of the zero-phase current signal to zero. The PI control unit 61 receives the DC component of the zero-phase current signal from the DC component extraction unit 5, performs PI control, and outputs a correction value. The correction value is added to the bus voltage target value (hereinafter, the bus voltage target value to which the correction value is added is referred to as “correction target value”). The PI control unit 62 is for feedback control of the bus voltage of the inverter device 20a to the correction target value. The PI control unit 62 receives a deviation between the bus voltage signal input from the bus voltage detection circuit 25 and the correction target value, performs PI control, and outputs the correction value to the current control unit 63. The current control unit 63 is for performing feedback control of the alternating current of each phase output from the filter circuit 23 to the target current. The current control unit 63 generates a command value signal for each phase based on the correction value input from the PI control unit 62 and outputs the command value signal to the PWM signal generation unit 3. Specifically, the deviation between each alternating current signal detected from each phase alternating current output from the filter circuit 23 and the target current value obtained by adding the correction value input from the PI control unit 62 is made zero. The correction value is output as a command value signal.

  As described above, the PWM signal generation unit 3 generates the PWM signal PWM1 from the carrier signal CR input from the carrier signal generation unit (not shown) and the command value signal input from the command value signal generation unit 6. It is. The PWM signal generation unit 3 outputs the generated PWM signal PWM1 to the inverter circuit 22.

  Also in the fourth embodiment, since the number of transformers to be used can be suppressed, the same operational effects as those in the first and second embodiments can be obtained. Furthermore, in the fourth embodiment, since the DC component of the zero-phase current signal is feedback-controlled to zero, even if a current path is formed between the inverter devices 20a, 20b, and 20c, the circulating current of the DC component is reduced. Can be suppressed.

  In the fourth embodiment, the zero-phase current detection circuit 26 detects the alternating current of each phase output from the filter circuit 23, and adds the detected alternating current signals of each phase, thereby adding a zero-phase current signal. Although it is set as the structure which produces | generates, it is not restricted to this. For example, the zero phase current detection circuit 26 may be a zero phase current transformer. In addition, as shown in FIG. 17, a similar effect can be obtained by providing a circulating current detection circuit that detects a current flowing on the ground line on the DC power supply side and inputting it to the DC component extraction unit 5. Further, the internal configuration of the command value signal generation unit 6 is not limited to the above, and is a configuration that generates a command value signal for feedback control of the DC component of the zero-phase current signal input from the DC component extraction unit 5 to zero. I just need it.

  In addition, in 4th Embodiment, although suppression control of the circulating current of a DC component is performed by all the inverter apparatuses 20a, 20b, 20c, it is not restricted to this. The suppression control may be performed only by any one of the inverter devices 20a, 20b, and 20c (for example, the inverter device 20a). Even in this case, since the DC component of the zero-phase current signal of one inverter device is suppressed, even if a current path is formed between the inverter devices 20a, 20b, 20c, the circulating current of the DC component is suppressed. Can do.

  In addition, the suppression control may not be performed by only one of the inverter devices 20a, 20b, and 20c (for example, the inverter device 20a). Even in this case, since the DC component of the zero-phase current signal of the remaining two inverter devices is suppressed, the circulating current of the DC component is suppressed even if a current path is formed between the inverter devices 20a, 20b, and 20c. be able to. Further, since all the inverter devices 20a, 20b, and 20c simultaneously suppress the circulating current, it is possible to avoid the inconvenience that the control becomes unstable (the control interferes and the control convergence point is not determined).

  Next, a fifth embodiment of the grid-connected inverter system according to the present invention will be described.

Generally, in a grid-connected inverter system for photovoltaic power generation, maximum power point tracking control (hereinafter referred to as “Pmax control”) is provided as a standard in order to effectively extract the output power of the solar cell. There are many. If the Pmax control is performed for each solar cell array, high efficiency can be realized. Therefore, when the system of the present invention is applied to a solar cell, each inverter device 20a, 20b, 20c is independently controlled by the configuration of FIG. It is better to go. Therefore, in such a case, the pattern of the PWM signal output from the control circuit 24 of each inverter device 20a, 20b, 20c is different.

  For example, with respect to the output power of the solar cell array connected to the inverter device 20a (corresponding to the DC power source 10a in FIG. 1), the solar cell array connected to the inverter device 20b (in FIG. 1 to the DC power source 10b) When the output power of (corresponding) is larger, the duty width of the PWM signal of the inverter device 20b (the length of time in the pulse ON state) is controlled to be larger than that of the inverter device 20a. That is, the PWM signal is turned on and off at different timings between the inverter devices 20a, 20b, and 20c, and as a result, a circulating current is generated. This point is the same as the generation factor of the circulating current of the high frequency component described in the third embodiment (see FIGS. 6 to 8). However, unlike the case of the PWM signal phase difference shown in FIG. 7, the circulating current caused by the difference in duty width changes in conjunction with the magnitude of the instantaneous value of the inverter output current. As a result, when the inverter circuit 22 (see FIG. 1) is a three-phase full bridge inverter, a high frequency component is converted into a third order component by the impedance component of the filter circuit 23 and the like, and is generated.

  Therefore, the circulating current of the third-order component superimposed on the zero-phase current Iz (see FIG. 5) causes a difference in the output power of each inverter device 20a, 20b, 20c and the duty width of the PWM signal differs. Occur. In the fifth embodiment, in each inverter device 20a, 20b, 20c, a third-order component is extracted from the zero-phase current Iz of the output current, and a correction value for performing feedback control to zero is added to the command value signal. This suppresses the circulating current of the tertiary component.

  A method for extracting the third-order component from the zero-phase current Iz of the output current will be described below.

  When the zero-phase current signal input from the zero-phase current detection circuit 26 is converted into a rotating coordinate system that rotates at a rotation angle 3ωt (where ω is an angular frequency (ω = 2πf) of the frequency f of the system voltage). The third-order component that is the component of the same rotation angle 3ωt is converted into a DC component (hereinafter, the DC component after the rotation coordinate conversion is referred to as “DC amount”). Since the components other than the tertiary component are converted to AC components (hereinafter, the AC component after the rotation coordinate conversion is referred to as “AC amount”), by removing the AC amount and extracting the DC amount, Only tertiary components can be extracted.

The zero-phase current signal is set to Iz (t) = Asin (3ωt + θ), and the rotation matrix [sin3ωt cos3ωt] ^T is multiplied from the left side. Then, the sin component α and the cos component β after rotation conversion are calculated by the following equation ( 3 ). Note that the zero-phase current signal includes a high-frequency component and a direct-current component, but is removed when the direct-current amount is extracted from the sin component α and the cos component β. .

Here, when the DC amount is extracted with respect to [α β] ^T , the following equation (4) is calculated. [α β] ^T is a constant value, and the amplitude A and the phase difference θ of the zero-phase current signal Iz (t) = Asin (3ωt + θ) can be calculated.

When the zero-phase current signal Iz (t) is restored from [α β] ^T , it can be calculated by the following equation (5) by multiplying the inverse transformation matrix (2 · [sin3ωt cos3ωt]) from the left side. it can.

  FIG. 18 is a diagram for explaining a fifth embodiment of the grid interconnection inverter system according to the present invention. In the figure, a part of the internal configuration of the control circuit 24 and the zero-phase current detection circuit 26 are shown. The configuration other than the control circuit 24 and the zero-phase current detection circuit 26 is the same as that of the grid-connected inverter system A shown in FIG. Also, descriptions of the internal configurations of the control circuit 24 that are not necessary in the description of the fifth embodiment (such as the internal oscillation unit 1a and the carrier signal generation unit 2a) are omitted.

  The control circuit 24 includes a PWM signal generation unit 3 and a command value signal generation unit 6. As described above, the PWM signal generation unit 3 generates the PWM signal PWM1 from the carrier signal CR input from the carrier signal generation unit (not shown) and the command value signal input from the command value signal generation unit 6. The generated PWM signal PWM1 is output to the inverter circuit 22 (see FIG. 1).

  The command value signal generation unit 6 generates a command value signal based on the zero phase current signal input from the zero phase current detection circuit 26 and outputs the command value signal to the PWM signal generation unit 3. The command value signal generation unit 6 includes a current control unit 63 and a zero-phase tertiary component control unit 64. As described above, the current control unit 63 generates a command value signal for feedback control of the AC current of each phase output from the filter circuit 23 (see FIG. 1) to the target current, and the PWM signal generation unit 3 Output to.

  The zero-phase third-order component control unit 64 extracts a third-order component from the zero-phase current signal input from the zero-phase current detection circuit 26, and outputs a correction value for performing feedback control to zero. . The command value signal output from the current control unit 63 is added to the correction value output from the zero-phase third-order component control unit 64 and input to the PWM signal generation unit 3.

  The zero-phase third-order component control unit 64 includes a rotation conversion unit 641, filter units 642 and 643, PI control units 644 and 645, and a correction value generation unit 646.

  The rotation converter 641 converts the zero-phase current signal Iz (t) input from the zero-phase current detection circuit 26 into a sin component Izs (t) and a cos component Izc based on the following equations (6) and (7). This is converted to (t), and corresponds to the above-described equation (3). The sin component Izs (t) is output to the filter unit 642, and the cos component Izc (t) is output to the filter unit 642.

Izs (t) = Iz (t) · sin 3ωt (6)
Izc (t) = Iz (t) · cos 3ωt (7)
Here, it is assumed that ω = 2πf [rad / s] and the value of the frequency f [Hz] matches the frequency of the system voltage by a PLL or the like.

  The filter unit 642 extracts the direct current amount Ys by removing the alternating current amount from the sin component Izs (t) input from the rotation conversion unit 641 and outputs it. The filter unit 643 removes the AC amount from the cos component Izc (t) input from the rotation conversion unit 641 and extracts and outputs the DC amount Xc, and corresponds to the above-described equation (4). The rotation conversion unit 641 and the filter units 642 and 643 convert the third-order component of the zero-phase current signal into a DC amount and extract it.

  The PI control units 644 and 645 are for feedback control of the third-order component of the zero-phase current signal to zero. The PI control unit 644 receives a deviation between the DC amount Ys output from the filter unit 642 and its target value “0”, performs PI control, and outputs a DC amount correction value Yspi. The PI control unit 645 receives a deviation between the DC amount Xc output from the filter unit 643 and its target value “0”, performs PI control, and outputs a DC amount correction value Xcpi.

  The correction value generation unit 646 converts the DC amount correction value Yspi and the DC amount correction value Xcpi input from the PI control units 644 and 645, respectively, into sin component correction values based on the following equations (8) and (9). This is converted to Izsr (t) and cos component correction value Izcr (t) and added to output a correction value Izr (t), which corresponds to the above-mentioned equation (5).

Izsr (t) = 2 ・ Yspi ・ sin (3ωt + φ) (8)
Izcr (t) = 2 ・ Xcpi ・ cos (3ωt + φ) (9)
Here, φ is a value for compensating for a delay element of the zero-phase current detection circuit 26 and a delay element (inductance component) on the circulating current path of the inverter circuit 22 , and is an appropriate value according to various inverter devices. Set to

  In the fifth embodiment, in order to facilitate the suppression control of the third-order component, the third-order component of the zero-phase current signal is extracted by multiplying the zero-phase current signal Iz (t) by the rotation matrix and then extracting the DC amount. Although it is extracted separately for the sin component and the cos component, it is not limited to this. The tertiary component may be directly extracted from the zero-phase current signal Iz (t), or may be controlled as it is without extracting the DC amount.

  Also in the fifth embodiment, since the number of transformers to be used can be suppressed, the same effects as those in the first and second embodiments can be achieved. Furthermore, in the fifth embodiment, since the tertiary component of the zero-phase current signal is feedback-controlled to zero, even if a current path is formed between the inverter devices 20a, 20b, and 20c, the tertiary component is circulated. Current can be suppressed.

  Note that the internal configuration of the command value signal generation unit 6 is not limited to the above, and generates a command value signal for feedback control of the third-order component of the zero-phase current signal input from the zero-phase current detection circuit 26 to zero. Any configuration may be used.

  In addition, in 5th Embodiment, although suppression control of the circulating current of a tertiary component is performed by all the inverter apparatuses 20a, 20b, 20c, it is not restricted to this. The suppression control may be performed only by any one of the inverter devices 20a, 20b, and 20c (for example, the inverter device 20a). Even in this case, since the tertiary component of the zero-phase current signal of one inverter device is suppressed, even if a current path is formed between the inverter devices 20a, 20b, 20c, the circulating current of the tertiary component is suppressed. can do.

  In addition, the suppression control may not be performed by only one of the inverter devices 20a, 20b, and 20c (for example, the inverter device 20a). Even in this case, since the tertiary component of the zero-phase current signal of the remaining two inverter devices is suppressed, even if a current path is formed between the inverter devices 20a, 20b, and 20c, the circulating current of the tertiary component is reduced. Can be suppressed. Further, since all the inverter devices 20a, 20b, and 20c simultaneously suppress the circulating current, it is possible to avoid the inconvenience that the control becomes unstable (the control interferes and the control convergence point is not determined).

Since the three types of circulating current suppression countermeasure circuits of the third to fifth embodiments described above have different types of circulating currents to be suppressed, if any one is provided, the zero-phase current Iz is reduced. Although there is an effect of suppressing, if a configuration in which any two are combined or a configuration in which all are combined, the zero phase current Iz can be suppressed to zero as much as possible.

  FIG. 19 is a block configuration diagram in which a circuit for suppressing high-frequency components, DC components, and tertiary components is added to the control circuit 24a of the inverter device 20a. Note that the configuration of the block A in the control circuit 24b of the inverter device 20b and the control circuit 24c of the inverter device 20c is different from that in FIG. 19 and includes only carrier signal generation units 2b and 2c.

  A block A surrounded by a one-dot difference line in the drawing is a circuit for suppressing high-frequency components, a block B is a circuit for suppressing DC components, and a block C is a circuit for suppressing tertiary components. . In block A, the phase of the clock pulse signal CLK generated by the internal oscillation unit 1a is corrected and output to each control circuit 24b, 24c in order to match the phase of the PWM signal output from each control circuit 24a, 24b, 24c. Is performed. In block B, an operation for feedback control of the DC component of the zero-phase current Iz to zero is performed, and in block C, an operation for feedback control of the third-order component of the zero-phase current Iz to zero is performed.

  Therefore, the PWM signal generation unit 3 includes a carrier signal having a phase in common with the carrier signals of the control circuits 24b and 24c, a command value signal for performing feedback control of the DC component and the tertiary component of the zero-phase current Iz to zero. Is generated, and the PWM signal PWM1 is generated and output to the inverter circuit 22. By controlling the on / off operation of the switching element by the PWM signal PWM1, the three-phase current and the zero-phase current output from the inverter circuit 22 are, for example, as shown in FIG.

Figure 20 is a waveform diagram corresponding to FIG. 5, the waveform shown in the upper part is the waveform of the U-phase current Iu, the waveform shown in the lower stage, the waveform of the zero-phase current Iz.

  As is apparent from a comparison between FIG. 5 and FIG. 5, the zero-phase current Iz has a DC component, a third-order component, and a high-frequency component sufficiently suppressed, and an ideal zero-phase current Iz ′ (level 0 current) The waveform changes minutely in the vicinity. Also, the U-phase current Iu has a substantially ideal sine waveform with substantially no distortion, with the DC component, the tertiary component and the high frequency component sufficiently suppressed. Therefore, a decrease in output power of the inverter device 20a due to the circulating current can be suppressed.

  The grid interconnection inverter system according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the grid-connected inverter system according to the present invention can be varied in design in various ways.

A, A 'Grid-connected inverter system 10, 10a, 10b, 10c DC power supply 20a, 20b, 20c Inverter device 21 DC / DC converter circuit 22 Inverter circuit 23 Filter circuit 24, 24a, 24b, 24c Control circuit 1a Internal oscillator 2a, 2b, 2c Carrier signal generation unit 3, 3a, 3b, 3c PWM signal generation unit 4a, 41a, 42a, 4b, 4c Phase correction unit 4a ' Carrier phase correction unit 5 DC component extraction unit 6 Command value signal generation unit 61 , 62 PI control unit 63 Current control unit 64 Zero-phase third-order component control unit 641 Rotation conversion unit 642, 643 Filter unit 644,645 PI control unit 646 Correction value generation unit 25 Bus voltage detection circuit 26 Zero-phase current detection circuit 30 Transformer 40 Commercial power system

Claims (4)

A plurality of inverter devices connected in parallel to each other, converting DC power from a DC power source into AC power, and outputting the AC power without passing through a transformer;
A connecting point on the output side of the plurality of inverter devices, and a transformer provided between the power system, and
Equipped with a,
One of the pair of output terminals of the DC power supply is grounded,
Each of the plurality of inverter devices includes a PWM control inverter circuit, a control circuit that generates a PWM signal for controlling the PWM control inverter circuit, and a zero that detects a zero-phase current from an output current of the PWM control inverter circuit Phase current detection circuit,
Any control circuit of each of the inverter devices,
DC component extracting means for extracting a DC component from the zero phase current signal detected by the zero phase current detection circuit;
Command value signal generating means for generating a command value signal for controlling the DC component extracted by the DC component extracting means to be zero, and
The command value signal generated by the command value signal generating means is compared with a carrier signal to generate the PWM signal.
This is a grid-connected inverter system. The command value signal generating means is
First PI control means for inputting a DC component extracted by the DC component extraction means, performing PI control, and outputting a correction value;
The deviation between the correction target value obtained by adding the correction value output from the first PI control means to the preset target value and the input voltage of the PWM control inverter circuit is input, and correction is performed by performing PI control. Second PI control means for outputting a value;
A generating circuit for generating the command value signal based on a correction value output from the second PI control means;
The grid interconnection inverter system according to claim 1 , comprising: A plurality of inverter devices connected in parallel to each other, converting DC power from a DC power source into AC power, and outputting the AC power without passing through a transformer;
A connecting point on the output side of the plurality of inverter devices, and a transformer provided between the power system, and
With
One of the pair of output terminals of the DC power supply is grounded,
Each of the plurality of inverter devices includes a PWM control inverter circuit, a control circuit that generates a PWM signal for controlling the PWM control inverter circuit, and a zero that detects a zero-phase current from an output current of the PWM control inverter circuit Phase current detection circuit,
Any control circuit of each of the inverter devices,
A third-order component extracting means for extracting a third-order component from the zero-phase current signal detected by the zero-phase current detection circuit;
Command value signal generation means for generating a command value signal for controlling the tertiary component extracted by the tertiary component extraction means to zero, and
The command value signal generated by the command value signal generating means is compared with a carrier signal to generate the PWM signal.
This is a grid-connected inverter system. The tertiary component extraction means includes
Rotation conversion for calculating a converted zero-phase current signal by performing a rotation coordinate conversion of a rotation angle corresponding to a frequency three times the frequency of the voltage of the power system on the zero-phase current signal input from the zero-phase current detection circuit Means,
Filter means for extracting a DC component of the converted zero-phase current signal as a third-order component of the zero-phase current signal;
The command value signal generating means is
PI control means that receives the tertiary component extracted by the tertiary component extraction means, performs PI control, and outputs a correction value;
Reverse rotation conversion means for performing reverse rotation coordinate conversion of the rotation angle on the correction value to calculate a conversion correction value,
Generating a command value signal based on the conversion correction value calculated by the reverse rotation conversion means;
The grid interconnection inverter system according to claim 3 .

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