JP5347879B2 - Class D amplifier circuit - Google Patents

Description

  The present invention relates to a class D amplifier circuit.

  Conventionally, a class D amplifier circuit that converts an input signal such as an audio signal into a pulse width modulation signal having a constant amplitude and amplifies the power of the pulse width modulation signal is widely known. For example, Patent Document 1 discloses a half-bridge class D amplifier circuit that supplies power with a single power supply (see FIG. 8).

JP 2009-33336 A

In the technique disclosed in Patent Document 1, the output current output from the output point S cannot be reversed (the direction in which the output current flows is reversed), and a coupling capacitor C2 for removing a DC component is provided. Since it is essential (see FIG. 8), there is a problem that the circuit scale is enlarged.
Here, a mode in which a negative potential lower than the reference potential is generated using a DC / DC converter and is supplied to the power supply line 220 shown in FIG. According to this aspect, although the coupling capacitor C2 is not required, a DC / DC converter is required. Therefore, there is a problem that the configuration becomes complicated and the cost increases accordingly.
In view of the above circumstances, an object of the present invention is to enable the output current of a class D amplifier circuit to be inverted with a simple configuration.

In order to solve the above problems, a class D amplifier circuit according to the present invention includes a first transistor disposed between a high-level power supply line (for example, the power supply line 41 shown in FIG. 1) and a first node; A second transistor disposed between the higher power supply line and the second node, and a third transistor disposed between the first node and the lower power supply line (for example, the ground line 43 shown in FIG. 1). A fourth transistor disposed between the second node and the lower power supply line, a coil disposed between the first node and the second node, and a second node and the load. A fifth transistor, a capacitor whose one electrode is connected to a connection point between the fifth transistor and a load (for example, the third node ND3 shown in FIG. 1), and a fixed potential is supplied to the other electrode; , Second transistor, third transistor, fourth Comprising a control unit for controlling the transistor and each of the on-off of the fifth transistor (for example, modulation unit 10 shown in FIG. 1), the control unit switches between a first state and a second state in response to an input signal, The first state includes a first period and a second period after the first period, and the second state includes a first period and a second period after the first period. And the control unit turns on the first transistor and the fourth transistor and turns off the second transistor, the third transistor, and the fifth transistor in the first period of the first state. A current flowing from the first node to the second node is passed through the coil, and one of the first transistor and the third transistor is connected to the fifth transistor in the second period of the first state. The transistor is turned on, and the other of the first transistor and the third transistor, the second transistor, and the fourth transistor are turned off, and a current from the first node to the second node is set. The capacitor element is charged while flowing to the load, and in the first period of the second state, the second transistor and the third transistor are turned on, and the first transistor, the fourth transistor, and the fifth transistor are turned on. The transistor is turned off, and a current from the second node to the first node is passed through the coil. In the second period of the second state, one of the first transistor and the third transistor and the The fifth transistor is turned on, and the first transistor and the third transistor are The other transistor, the second transistor, and the fourth transistor are turned off, and a current from the second node to the first node is supplied to the load and the capacitor is charged.

In the first state, the control unit can turn the first transistor off and the third transistor on after the current flowing from the first node to the second node flows through the coil. The control unit can also maintain the first transistor in the on state and the third transistor in the off state after flowing a current from the first node to the second node through the coil.
In the second state, the control unit can turn on the first transistor and turn off the third transistor after flowing a current from the second node to the first node through the coil. The control unit can also maintain the third transistor in the on state and the first transistor in the off state after flowing a current from the second node to the first node through the coil. A combination of the on / off operation of the first transistor and the third transistor in the first state and the on / off operation of the first transistor and the third transistor in the second state is arbitrary.

  In the present invention, the output current of the class D amplifier circuit can be inverted by switching between the first state and the second state according to the input signal. According to the present invention, since a coupling capacitor and a DC / DC converter are unnecessary, there is an advantage that the output current of the class D amplifier circuit can be inverted with a simple configuration.

  As a specific aspect of the class D amplifier circuit according to the present invention, the control unit performs pulse width modulation on the input signal to generate a pulse width modulation signal, and the pulse width modulation signal is converted into a first transistor, a second transistor, Output to the gates of the third transistor, the fourth transistor, and the fifth transistor.

It is a figure which shows schematic structure of the class D amplifier circuit which concerns on embodiment of this invention. It is a timing chart which shows operation of the 1st state. It is a figure which shows the state of the drive part in a 1st state. It is a figure which shows the state of the drive part in a 1st state. It is a timing chart which shows operation of the 2nd state. It is a figure which shows the state of the drive part in a 2nd state. It is a figure which shows the state of the drive part in a 2nd state. It is a figure which shows schematic structure of the conventional class D amplifier circuit.

  FIG. 1 is a diagram showing a schematic configuration of a class D amplifier circuit 100 according to an embodiment of the present invention. As shown in FIG. 1, the class D amplifier circuit 100 includes a modulation unit 10 and a drive unit 20. The modulation unit 10 modulates the input signal AIN into a pulse width modulation signal (OUTPP, OUTMP, OUTG, OUTPN, OUTMN) having a constant amplitude. In the present embodiment, the input signal AIN is an analog audio signal. The drive unit 20 drives a load (for example, a speaker) 30 based on a pulse width modulation signal (OUTPP, OUTMP, OUTG, OUTPN, OUTMN).

  As shown in FIG. 1, the drive unit 20 includes a first transistor Tr1 to a fifth transistor Tr5, a coil L, and a capacitive element C. The first transistor Tr1 to the fourth transistor Tr4 are arranged between a power supply line 41 to which a power supply potential VDD is supplied and a ground line 43 to which a ground potential GND (<VDD) is supplied. The N-channel first transistor Tr1 is disposed between the power supply line 41 and the first node ND1. A pulse width modulation signal OUTPP is supplied to the gate of the first transistor Tr1. The N-channel type second transistor Tr2 is disposed between the power supply line 41 and the second node ND2. The pulse width modulation signal OUTMP is supplied to the gate of the second transistor Tr2. The N-channel third transistor Tr3 is disposed between the first node ND1 and the ground line 43. A pulse width modulation signal OUTMN is supplied to the gate of the third transistor Tr3. The N-channel fourth transistor Tr4 is disposed between the second node ND2 and the ground line 43. A pulse width modulation signal OUTPN is supplied to the gate of the fourth transistor Tr4.

  A coil L is provided between the first node ND1 and the second node ND2. An N-channel fifth transistor Tr5 is provided between the second node ND2 and the load 30. A pulse width modulation signal OUTG is supplied to the gate of the fifth transistor Tr5. The capacitive element C includes a first electrode D1 and a second electrode D2. The first electrode D1 is connected to a third node ND3 interposed on the current path from the fifth transistor Tr5 to the load 30. The second electrode D2 is connected to the ground line 43.

  In the present embodiment, the modulation unit 10 generates a pulse width modulation signal (OUTPP, OUTMP, OUTG, OUTPN, OUTMN) so as to switch between the first state and the second state according to the input signal AIN. In the “first state”, the current from the first node ND1 to the second node ND2 flows through the coil L in a state where the coil L and the load 30 are electrically disconnected, and then the coil L and the load 30 are Electrically connected, a current from the first node ND1 to the second node ND2 flows through the load 30 and charges the capacitive element C. On the other hand, in the “second state”, the current from the second node ND2 to the first node ND1 flows through the coil L in a state where the coil L and the load 30 are electrically disconnected. Are electrically connected to each other, and a current from the second node ND2 toward the first node ND1 flows through the load 30 and charges the capacitive element C.

  Hereinafter, specific operations in each of the first state and the second state will be described. As shown in FIGS. 2 and 5, the class D amplifier circuit 100 according to the present embodiment is in a state where the coil L and the load 30 are electrically disconnected in both the first state and the second state. A first period T1 in which the current from the power supply line 41 flows through the coil L and a second period T2 in which the coil L and the load 30 are electrically connected and the current flowing through the coil L is supplied to the load 30 are 1 Operates as a cycle. The time length and the number of cycles of the first period T1 and the second period T2 are variably set according to the pulse width modulation signal.

  First, the operation in the first state will be described with reference to FIGS. When the first period T1 starts, as shown in FIG. 2, the pulse width modulation signal OUTPP and the pulse width modulation signal OUTPN are set to a high level, while the pulse width modulation signal OUTG, the pulse width modulation signal OUTMP, and the pulse width are set. The modulation signal OUTMN is set to a low level. Therefore, as shown in FIG. 3, the first transistor Tr1 and the fourth transistor Tr4 are controlled to be in the on state, while the second transistor Tr2, the third transistor Tr3, and the fifth transistor Tr5 are controlled to be in the off state. . Thereby, the current from the power supply line 41 flows to the ground line 43 via the first transistor Tr1, the coil L, and the fourth transistor Tr4. In the present embodiment, since the current flowing through the coil L is positive in the direction from the first node ND1 to the second node ND2, the current value of the current flowing through the coil L in the first period T1 as shown in FIG. Rises over time.

  Subsequently, when the second period T2 starts, the pulse width modulation signal OUTPP and the pulse width modulation signal OUTPN change to a low level, and the pulse width modulation signal OUTG and the pulse width modulation signal OUTMN change to a high level. Therefore, as shown in FIG. 4, the first transistor Tr1 and the fourth transistor Tr4 transition to the off state, and the third transistor Tr3 and the fifth transistor Tr5 transition to the on state. When the first transistor Tr1 transitions to the OFF state, the current flowing from the power supply line 41 to the coil L is cut off, but the current directed from the first node ND1 to the second node ND2 by the induced electromotive force generated in the coil L. Continues to flow through the coil L. However, as shown in FIG. 2, the current value of the current flowing through the coil L in the second period T2 decreases with time. Then, the current is supplied to the load 30 via the fifth transistor Tr5. As a result, the potential of the third node ND3 (the output potential of the class D amplifier circuit 100) increases with time (see FIG. 2).

  The second period T2 ends when the pulse width modulation signals OUTG and OUTMN change to a low level and the third transistor Tr3 and the fifth transistor Tr5 transition to the off state. The potential of the third node ND3 at the end point of the second period T2 is held by the capacitive element C until the second period T2 is started in the next cycle. Thus, since the potential of the third node ND3 can be suppressed from changing after the second period T2 is completed, there is an advantage that the amount of unnecessary electromagnetic radiation (EMI: Electro Magnetic Interference) can be reduced.

  Next, the operation in the second state will be described with reference to FIGS. As shown in FIG. 5, when the first period T1 starts, the pulse width modulation signal OUTMP and the pulse width modulation signal OUTMN are set to a high level, while the pulse width modulation signal OUTPP, the pulse width modulation signal OUTPN, and the pulse width are set. The modulation signal OUTG is set to a low level. Therefore, as shown in FIG. 6, the second transistor Tr2 and the third transistor Tr3 are controlled to be in the on state, while the first transistor Tr1, the fourth transistor Tr4, and the fifth transistor Tr5 are controlled to be in the off state. . Thereby, the current from the power supply line 41 flows to the ground line 43 through the second transistor Tr2, the coil L, and the third transistor Tr3. Since the current flowing in the direction from the second node ND2 to the first node ND1 has a negative value, the current value of the current flowing through the coil L in the first period T1 decreases with time as shown in FIG. The absolute value of the current value increases with time).

  Subsequently, when the second period T2 starts, the pulse width modulation signal OUTMP changes to a low level, while the pulse width modulation signal OUTG changes to a high level. Therefore, as shown in FIG. 7, the second transistor Tr2 transitions to the off state, while the fifth transistor Tr5 transitions to the on state. Although the current flowing from the power supply line 41 to the coil L is cut off by the second transistor Tr2 transitioning to the OFF state, the current from the second node ND2 to the first node ND1 is induced by the induced electromotive force generated in the coil L. Continues to flow through the coil L. As shown in FIG. 5, in the second period T2, the current value of the current flowing through the coil L increases with time (the absolute value of the current value decreases with time). The current is supplied to the load through the fifth transistor Tr5. That is, a current in the direction opposite to that in the first state flows through the load 30. At this time, the electric charge existing at the third node ND3 moves (sucks) to the ground line 43 via the fifth transistor, the coil L, and the third transistor Tr3, so that the potential of the third node ND3 decreases with time. (See FIG. 5).

  The second period T2 ends when the pulse width modulation signals OUTG and OUTMN change to a low level and the third transistor Tr3 and the fifth transistor Tr5 transition to the off state. Similar to the first state described above, the potential of the third node ND3 at the end point of the second period T2 is held by the capacitive element C until the second period T2 is started in the next cycle.

  As described above, in this embodiment, the current flowing through the load 30 (the output current of the class D amplifier circuit 100) is inverted by switching between the first state and the second state according to the input signal AIN. be able to. According to the present invention, since a coupling capacitor and a DC / DC converter are unnecessary, there is an advantage that the output current of the class D amplifier circuit can be inverted with a simple configuration.

  Further, the class D amplifier circuit 100 according to the present embodiment is switched to the first state when the rate of change per unit time of the input signal AIN is positive, and when the rate of change per unit time of the input signal AIN is negative. Is switched to the second state. As described above, the potential of the third node ND3 (the output potential of the class D amplifier circuit 100) increases with time in the first state (that is, the rate of change per unit time becomes positive), while the second Since the state decreases with time (that is, the rate of change per unit time becomes negative), the waveform of the output potential of the class D amplifier circuit 100 and the waveform of the input signal AIN are similar to each other.

<Modification>
The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible. Also, two or more of the modifications shown below can be combined.

(1) Modification 1
The input signal AIN is an analog audio signal, but is not limited to this, and the format of the input signal AIN is arbitrary. For example, the input signal AIN can be a digital audio signal. When the input signal AIN is a digital audio signal, the modulation unit 10 is a digital circuit, and it is preferable to reduce the quantization noise by providing a noise shaping filter at the preceding stage.

(2) Modification 2
In the above-described embodiment, in the first state, after a current from the first node ND1 to the second node ND2 flows through the coil L, the first transistor Tr1 is turned off and the third transistor Tr3 is turned on. However, for example, after the current from the first node ND1 to the second node ND2 flows in the coil L, the first transistor Tr1 can be kept on and the third transistor Tr3 can be kept off. In short, it is sufficient that the potential of the first node ND1 is fixed to a predetermined value in the second period T2. The same applies to the second state. In the above-described embodiment, after the current from the second node ND2 to the first node ND1 flows through the coil L, the first transistor Tr1 is kept off and the third transistor Tr3 is kept on. After the current from the second node ND2 to the first node ND1 flows in the coil L, the first transistor Tr1 may be turned on and the third transistor Tr3 may be turned off.

(3) Modification 3
In the above-described embodiment, the second electrode D2 of the capacitive element C is connected to the ground line 43, but not limited to this, the fixed potential supplied to the second electrode D2 is arbitrary.

(4) Modification 4
In the above-described embodiment, the transistors (Tr1 to Tr5) included in the drive unit 20 are all N-channel transistors, but the present invention is not limited thereto, and the conductivity type of each transistor included in the drive unit 20 is arbitrary. . For example, all of the transistors (Tr1 to Tr5) included in the drive unit 20 may be P-channel transistors, or some may be P-channel transistors and the rest may be N-channel transistors.

DESCRIPTION OF SYMBOLS 10 ... Modulation part, 20 ... Drive part, 30 ... Load, 41 ... Power supply line, 43 ... Ground line, Load 100 ... Class D amplifier circuit, AIN ... Input signal, C ... Capacitance element, D1 …… First electrode, D2 …… Second electrode, L …… Coil, ND1 …… First node, ND2 …… Second node, ND3 …… Third node, Tr1 …… First transistor, Tr2 …… Second transistor, Tr3 ... third transistor, Tr4 ... fourth transistor, Tr5 ... fifth transistor, GND ... ground potential, VDD ... power supply potential.

Claims (2)

A first transistor disposed between the high-side power line and the first node;
A second transistor disposed between the high-level power supply line and a second node;
A third transistor disposed between the first node and the lower power line;
A fourth transistor disposed between the second node and the lower power line;
A coil provided between the first node and the second node;
A fifth transistor provided between the second node and a load;
A capacitive element in which one electrode is connected to a connection point between the fifth transistor and the load, and a fixed potential is supplied to the other electrode;
A controller that controls on / off of each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor;
The controller is
Switching between the first state and the second state according to the input signal,
The first state includes a first period and a second period after the first period;
The second state includes a first period and a second period after the first period,
The controller is
In the first period of the first state,
The first transistor and the fourth transistor are turned on, and the second transistor, the third transistor, and the fifth transistor are turned off, and current flowing from the first node to the second node is changed to the coil. Sink
In the second period of the first state,
One of the first transistor and the third transistor and the fifth transistor are turned on, and the other of the first transistor and the third transistor, the second transistor, and the fourth transistor As an off state, a current flowing from the first node to the second node is supplied to the load and the capacitive element is charged.
In the first period of the second state,
The second transistor and the third transistor are turned on, and the first transistor, the fourth transistor, and the fifth transistor are turned off, and a current from the second node to the first node is supplied to the coil. Sink
In the second period of the second state,
One of the first transistor and the third transistor and the fifth transistor are turned on, and the other of the first transistor and the third transistor, the second transistor, and the fourth transistor In an off state, a current flowing from the second node to the first node is supplied to the load and the capacitive element is charged.
Class D amplifier circuit. The controller generates a pulse width modulation signal by performing pulse width modulation on the input signal, and the pulse width modulation signal is converted into the first transistor, the second transistor, the third transistor, the fourth transistor, and the Output to each gate of the fifth transistor;
The class D amplifier circuit according to claim 1 .

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