JP4980743B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device that converts a DC voltage into an AC voltage and drives a load such as an electric motor.

In a conventional power conversion device, a sine wave voltage output to a load is controlled in a stepped manner (for example, see Patent Document 1). A plurality of power converters equipped with DC power supplies having different voltages are connected in series to supply an AC voltage to the load. Each power converter is connected so as to be connected in series so that the combined voltage changes in a step shape and becomes a sine wave shape.
For example, each power converter has a DC voltage of Vdc, and each has a circuit configuration that can output voltages of + Vdc, 0, and −Vdc. When 0 is output as the output voltage, all power converters output 0. When + Vdc is output, one power converter outputs + Vdc, and the rest outputs 0. When + 2Vdc is output, two may output + Vdc.
When this method is further advanced and power converters having different DC voltages are combined, for example, when the first-stage power converter has a DC voltage of 3 Vdc and the second-stage power converter has a DC voltage of Vdc, + Vdc is output when The second stage power converter outputs + Vdc, and the first stage outputs 0. When +2 Vdc is output, +3 Vdc is output at the first stage and −Vdc is output at the second stage, and the combined voltage is +2 Vdc.

US Pat. No. 3,579,081

In the conventional power converter, since a plurality of power converters are connected in series and the combined output voltage waveform is controlled to be stepped, the number of steps is set to obtain a voltage with less distortion. There is a problem that it is necessary to increase, resulting in an increase in the number of converters and an economical disadvantage.
The present invention has been made to solve the above problems, and an object of the present invention is to obtain a voltage waveform with little distortion even if the number of power converters is small.

The power converter according to the present invention outputs a first output voltage based on a first DC power supply so as to follow a voltage command value that is an AC signal by an on / off operation of the first DC power supply and switching element. The power conversion means calculates the average value of the first output voltage waveform output from the first power conversion means for each predetermined sampling period, and estimates the average voltage value of the waveform obtained by connecting the average values for each sampling period. The second output voltage is output based on the second DC power supply so as to follow the deviation between the voltage command value and the average voltage value by ON / OFF operation of the switching element. Comprising second power conversion means;
A voltage obtained by superimposing the second output voltage on the first output voltage is output as a voltage in response to the voltage command value.

  As described above, in the power conversion device according to the present invention, the second power conversion unit outputs the second output so as to fill the deviation between the first output voltage output from the first power conversion unit and the voltage command value. Since the voltage is output and the voltage obtained by superimposing the second output voltage on the first output voltage is used as the final output voltage, the second power conversion unit particularly reduces distortion of the final output voltage. As a whole, a voltage waveform with little distortion can be obtained with a small amount of power conversion means.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram for explaining a power conversion apparatus according to Embodiment 1 of the present invention. The first DC potential group 1 as the first DC power supply has two potentials P11 and P12 (P11> P12), and is connected to the first power conversion means 2. The DC side of the first power conversion means 2 is connected to the first DC potential group 1 and the AC side is connected to the second power conversion means group 3 via the first output terminals T1a, T1b, T1c, A voltage is output from the second power conversion means group 3 to the second output terminals T2a, T2b, and T2c. For example, a load such as an electric motor is connected to the second output terminals T2a, T2b, and T2c and driven.

First, an overview of the overall configuration will be described.
The voltage command values V2a ^* , V2b ^* , V2c ^* to be generated by the second output terminals T2a, T2b, T2c are input to the first potential selection means 4, and the first potential selection means 4 The switching states S21, S22, and S23 of the conversion unit 2 are output, and the switching sequence SEQ and the switching period signal SWT are output to the voltage estimation unit 5.
The voltage estimation means 5 outputs average voltage values V1a ′, V1b ′, and V1c ′ from the waveform of the voltage (first output voltage) output to the first output terminals T1a, T1b, and T1c by a method described later.
Subtracting means 7a, 7b, 7c, the average voltage value V1a ', V1b', V1c 'voltage command ^{V2a *,} V2b *, calculates the deviation between V2c ^*, inputted to the second potential selection means 6.

  The second potential selection means 6 outputs the switching states S31a, S32a, S31b, S32b, S31c, S32c of the second power conversion means group 3, and the second power conversion means 32a, 32b, 32c The potential P3a1> P3a2, P3b1> P3b2, and P3c1> P3c2 of the second DC potential groups 31a, 31b, and 31c, which are the second DC power supplies, are selected and a voltage is output. The second output terminals T2a, T2b, and T2c have a voltage (second output) output from the second power conversion unit group 3 to a voltage (first output voltage) output from the first power conversion unit 2. The output voltage is superimposed on the output voltage.

FIG. 2 is a configuration diagram for explaining the details of the first potential selection means 4 according to the first embodiment of the present invention. The command value V2a ^{* of the} voltage to be generated by the second output terminal T2a is normalized by dividing by the potential difference between the potentials P11 and P12 of the first DC potential group 1 by the subtracting means 416a and the dividing means 402a. At 403a, the switching period signal SWT1a is calculated and input to the subtracting means 404a via the sample hold means 407a.
Generated by the sampled and held switching period signal SWT1a ′ and the reference signal generating means 401a by the comparing means constituted by the subtracting means 404a and the function means 405a that becomes 0 when the input is negative and 1 otherwise. SW1a, which is the result of comparison with the reference signal SWT0a, is input to the switching pattern selection means 406a.
The switching pattern selection unit 406a outputs the switching state S21 of the first power conversion unit 2 based on the switching pattern SEQa and the comparison result SW1a.

The reference signal SWT0a is sampled by the sample hold means 408a and is output together with the switching period signal SWT1a ′ (a signal indicated as SWTa ′ in the figure). The switching patterns SEQa, SEQb, SEQc (signals shown as SEQ in the figure), switching period signals SWT1a ′, SWT1b ′, SWT1c ′ and reference signals SWT0a ′, SWT0b ′, SWT0c ′ are output to the voltage estimation means 5. (Signal indicated as SWT 'in the figure). The configuration for outputting the switching states S22 and S23 from the voltage command values V2b ^* and V2c ^* is the same.

FIG. 3 is a configuration diagram for explaining the details of the voltage estimation means 5 according to the first embodiment of the present invention. The state estimating unit 52a inputs the switching pattern SEQa and the switching period signal SWTa ′ to the subtracting units 501a and 502a, and outputs the output by the multiplying units 505a and 506a via the limiting units 503a and 504a. Multiply each of the two elements.
The outputs of the multiplying means 505a and 506a are added by the adding means 507a and divided by the constant value Δ by the dividing means 508a to output the average switching state SSa for a predetermined sampling period Ts. The multiplication means 51a multiplies the potential difference between the average switching state SSa and the potentials P11 and P12 of the first DC potential group 1, and the potential P12 is added by the addition means 53a to obtain the average voltage value V1a ′.
The average voltage value V1a ′ obtained here is a voltage having a waveform obtained by connecting the average value of the first output voltage waveform output to the first output terminal T1a every sampling period Ts.
The configuration for calculating V1b ′ and V1c ′ from SEQb and SWTb ′ and SEQc and SWTc ′ is also the same.

FIG. 4 is a configuration diagram for explaining the details of the second potential selection means 6 according to the first embodiment of the present invention. Since the potential selection means 6 includes the same potential selection means 61a, 61b, 61c for each phase, the configuration of the potential selection means 61a is shown here. The comparison means composed of the subtraction means 603a and 604a and the function means 605a and 606a which is 0 when the input is a negative value and 1 otherwise, has a deviation between the voltage command value V2a ^* and the average voltage value V1a ′. A signal obtained by multiplying the signal held by the sample hold means 607a for each sampling period and the reference signal SWT20a generated by the signal generation means 601a by the potential difference between the potentials P3a1 and P3a2 of the second DC potential group 31a by the multiplication means 602a. Input and output the switching states S31a and S32a of the second power conversion means 32a.

Next, the operation of each unit will be described. First, an operation in which the switching states S21, S22, and S23 are output from the voltage command value V2a ^* and the first power conversion unit 2 outputs a potential to the first output terminal T1a will be described.
The voltage command value V2a ^* is an AC signal (fixed frequency or variable frequency AC signal including a DC component) having a magnitude in the range of potentials P12 to P11 of the first DC potential group 1. When the potential P12 is subtracted by the subtracting means 416a and divided by the potential difference P11-P12 by the dividing means 402a, a signal having a normalized magnitude of 0 to 1 is obtained, and the subtracting means 403a uses the inverted signal. 1 is added to calculate the switching period signal SWT1a.

FIG. 5 shows a graph for explaining an example of the waveform of each part. A sine wave voltage command value V2a ^* and a signal SWT1a ′ obtained by sampling and holding the calculated sine wave signal SWT1a are shown in the first and second graphs. The signal SWT0a generated by the signal generating means 401a is also shown in the second graph of FIG. The third stage of FIG. 5 shows the time-expanded waveform of the second stage, and SWT1a ′ and SWT0a are compared by the subtracting means 404a and the function means 405a. When SWT1a ′ is larger than SWT0a, SW1a is 0, and conversely, when SWT0a is large, SW1a is 1 in the fourth stage. The switching pattern selection unit 406a refers to the element of SEQa = (0, 1) according to the value of SW1a. That is, when SW1a is 0, the first element 0 of SEQa is referenced, and when SW1a is 1, the second element 1 is referenced and the value is output to S21.

In this way, when the voltage command value V2a ^* is close to P12, the time for taking the potential of P12 is long, and when V2a ^* is close to P11, the time for taking the potential of P11 is long. ^The time taken for P11 and P12 with a distribution proportional to ^* is given to S21 as a switching state. As a result, it is possible to output to the first output terminal T1a a voltage at which the temporal average potential during the repetition period of the SWT0a is a value proportional to the voltage command value V2a ^* .
The same applies to the operation in which the switching states S22 and S23 are given from the voltage command values V2b ^* and V2c ^* .

Then, according to the switching state of S21, in the first power conversion means 2, when S21 is 0, the low potential P12 of the first DC potential group 1 is set, and when S21 is 1, the first DC potential group 1 is set. The high potential P11 is output to the first output terminal T1a. Similarly, the potential of P11 or P12 is output to the first output terminals T1b and T1c, respectively, according to the switching states of S22 and S23. By operating in this way, potentials proportional to the voltage command values V2a ^* , V2b ^* , V2c ^* are output to the first output terminals T1a, T1b, T1c.

  Next, the operation of the voltage estimation unit 5 will be described. The SWT0a 'and SWT1a' sampled by the first potential selection means 4 are input, and the subtraction means 501a subtracts SWT0a 'from SWT1a' and restricts it to the range of 0 to Δ by the restriction means 503a. Here, Δ is the amount of change in which SWT0a ′ increases between Ts, and corresponds to Ts / T, where T is the repetition period of SWT0a ′. The subtracting means 502a adds S to SWT0a 'and subtracts SWT1a'. This is equivalent to subtracting SWT1a 'from the estimated value of SWT0a' after one sample. The output of the subtracting means 502a is also limited to the range of 0 to Δ by the limiting means 504a. Thereby, for example, when SWT1a ′ is equal to or greater than SWT0a ′ + Δ, the output of the limiting unit 503a is Δ, and the output of the limiting unit 504a is 0. When SWT1a 'is smaller than SWT0a' + Δ and greater than or equal to SWT0a ', the output of limiting means 503a is SWT1a'-SWT0a', and the output of limiting means 504a is SWT0a '+ Δ-SWT1a'. When SWT1a 'is smaller than SWT0a', the output of limiting means 503a is 0, and the output of limiting means 504a is Δ.

Accordingly, the outputs of the limiting means 503a and 504a represent the time distribution taking the first and second elements of the switching pattern SEQa in the Ts period. Multiplying means 505a and 506a multiply the first element 0 of SEQa and the output of limiting means 503a, the second element 1 of SEQa and the output of limiting means 504a, add them by adding means 507a, and then add Δ by dividing means 508a. When dividing, the average switching state SSa in the switching period Ts is obtained.
As an example, a waveform is shown in FIG. In this example, the sampling period Ts is 1/8 with respect to the repetition period T of SWT0a ′. In the first three sampling periods, SWT1a ′ is greater than or equal to SWT0a ′, and the average switching state SSa in each sampling period is equal to the first element of SEQa and is zero. In the fourth sampling period, SWT0a ′ and SWT1a ′ intersect within the sampling period to change the switching state. However, due to the relationship between SWT0a ′ and SWT0a ′ + Δ and SWT1a ′, intermediate between the first element and the second element of SEQa Value. In the fifth to eighth sampling periods, SWT1a ′ is smaller than SWT0a ′, and the average switching state SSa is 1. An example of the average switching state SSa is shown in the second graph of FIG. Then, the potential difference P11-P12 between the average switching state SSa and the first DC potential group 1 is multiplied by the multiplying means 51a, and when the potential P12 is added by the adding means 53a, the potential output to the first output terminal T1a is sampled. It is estimated as an average potential value V1a ′ averaged by Ts. An example of the waveform is shown in the third row of FIG.
That is, the waveform of the average potential value V1a ′ is a waveform obtained by calculating the average value of the first output voltage waveform output from the first power conversion unit 2 for each sampling period and connecting the average value for each sampling period. .

Next, the operation of the second potential selection means 6 will be described. A result obtained by subtracting the voltage average value V1a ′ from the voltage command value V2a ^* is used as a voltage command value to be output by the second power conversion unit 32a, and is sampled and held by the sample hold unit 607a to output the SWT 21a ′. The triangular wave reference signal SWT20a having the sampling period Ts generated by the signal generating means 601a is multiplied by the potential difference of the second DC potential group 31a by the multiplying means 602a to obtain the SWT22a, and the subtracting means 603a, 604a and the function means 605a. , 606a is compared with the SWT 21a ′.
The output of the function means 605a is 1 when the SWT 21a ′ is equal to or greater than the SWT 22a, and is 0 when the SWT 21a ′ is smaller than the SWT 22a. The function means 606a outputs 1 when the signal obtained by inverting the sign of the SWT 21a ′ is equal to or higher than the SWT 22a, and outputs 0 when the signal is smaller than that. As a result, the function means 605a is 1 or 0 and the function means 606a is 0 on the positive side of the SWT 21a ', whereas the function means 605a is 0 and the function means 606a is 1 or 0 on the negative side. The outputs of the function means 605a and 606a are in the switching states S31a and S32a, respectively, and the switching state of the second power conversion means 32a is obtained.

FIG. 6 shows examples of SWT 21a ′ and SWT 22a and their sign inversions on the fourth stage, and examples of switching states S31a and S32a on the fifth and sixth stages. When the switching state S31a is 1, the potential P3a1 is connected to the output terminal T2a, and when the switching state S31a is 0, the potential P3a2 is connected. Similarly, the potential P3a1 is connected to the output terminal T1a when the switching state S32a is 1, and the potential P3a2 is connected when the switching state S32a is 0. Then, the second power conversion means 32a applies a voltage as shown in the seventh stage of FIG. 6 between the output terminals T2a and T1a. As a result, the second power conversion unit 32a outputs a voltage between the output terminals T2a and T1a in which the average potential for each sampling period Ts matches the difference between the voltage command value V2a ^* and the average voltage value V1a ′. Accordingly, a voltage at which the average potential value for each sampling period Ts matches the voltage command value V2a ^* is output to the output terminal T2a.
The operation of outputting S31b, S32b, S31c, and S32c from the voltage command values V2b ^* and V2c ^* and the average voltage values V1b ′ and V1c ′ is the same.

In order to show the effect of operating so that the average potential matches the voltage command value V2a ^* , FIG. 7 shows an example of the operation by the PWM method of instantaneous value comparison. The first row of FIG. 7 shows a triangular wave comparison carrier signal and voltage command value V2a ^* for controlling the first power conversion means 2. The second stage is a pulsed voltage output from the first power conversion means 2 generated by a pulse generated by comparing the carrier signal and the voltage command value.
The voltage command value of the second power conversion means group 3 is the difference between the voltage command value V2a ^{* at} the second stage in FIG. 7 and the pulse voltage, and corresponds to the waveform at the third stage. The fourth-stage pulse is generated by the carrier signal for PWM of the second power conversion means 32a and the voltage command value (V2a ^* −V1a). In the fourth-stage pulse, the average value in the switching period is indicated by a solid line in the fourth stage, but the broken line is the voltage command value (V2a ^* −V1a), and there is a difference. Since the voltage generated by PWM is generated as an average voltage during the switching period, the deviation from the command value can be reduced by operating the average potential to match V2a ^* as shown in the present embodiment.

By operating as described above, the second power conversion means group 3 operates so as to correct the potential output by the first power conversion means 2, and the voltage command value V2a ^* is applied to the output terminals T2a, T2b, T2c ^. , V2b ^* and V2c ^* are outputted, and a voltage can be supplied to the load.
The fundamental wave component of the voltage output from the first power conversion means 2 to the terminals T1a, T1b, and T1c substantially matches the fundamental wave component required by the load, and the main energy is derived from the first DC potential group 1. Supplied to the load. Therefore, the energy required by the second DC potential groups 31a, 31b, 31c can be kept to a minimum.

According to the first embodiment of the present invention, the average voltage between the sampling periods of the output terminals T2a, T2b, and T2c can be made to coincide with the voltage command values V2a ^* , V2b ^* , and V2c ^*. Although it is suitable for realization by a processor, the same contents can also be realized by a continuous time system represented by an analog control circuit.

The relationship between the repetition period T of the reference signal SWT0a and the sampling period Ts is arbitrary. However, the number of switch operations is related to the number of switch operations of the first power conversion unit 2 and the number of switch operations of the second power conversion unit group 3. By adding a difference to the above, appropriate power conversion means can be selected for each.
For example, the potential difference of the second DC potential group is made smaller than the potential difference of the first DC potential group 1, and the first power conversion means 2 is a power conversion means suitable for a switching frequency with a high voltage and a low switching frequency. The power conversion means group 3 can obtain an optimum system configuration such as selecting a power conversion means suitable for the switching frequency with a low voltage. Further, since the second power conversion means group 3 operates so as to correct the voltage of the first power conversion means 2, it is more preferable to operate in a relationship of T> Ts, and the output terminals T2a, T2b, T2c. Can be accurately controlled to voltage command values V2a ^* , V2b ^* , V2c ^* .

Further, the reference signal SWT0a of the first potential selection unit 4 may have another signal waveform. For example, the reference signal SWT0a of the second potential selection unit 6 is a triangular wave and the switching pattern is SEQa = (0, 1 , 0), the same effect can be obtained.
In addition, the cycle of the reference signal SWT20a does not necessarily need to be the sampling cycle Ts, and operates in a different cycle and has the same effect.
In addition, the method in which the first power conversion unit 2 outputs the potential of the first DC potential group 1 to the output terminals T1a, T1b, and T1c may be controlled by the switching states S21, S22, and S23. A power semiconductor such as a transistor, a thyristor, or a diode can be used.
Further, in the present embodiment, an example of three phases is shown, but as is apparent from the configuration diagram, the same control means is configured for each phase, so the invention is not limited to three phases and is not limited to three phases. It can be easily configured.

Embodiment 2. FIG.
FIG. 8 is a configuration diagram for explaining a power converter according to Embodiment 2 of the present invention. In the second embodiment, a control using a known so-called instantaneous space voltage vector theory is applied. Therefore, here, a well-known part in the details of the theory will be omitted as appropriate.

  The first DC potential group 1 has two potentials P11 and P12 (P11> P12) and is connected to the first power conversion means 2. The DC side of the first power conversion means 2 is connected to the first DC potential group 1, and the AC side is connected to the second power conversion means group 3 via the first output terminals T1a, T1b, T1c. The voltage is output from the second power conversion means group 3 to the second output terminals T2a, T2b, and T2c. For example, a load such as an electric motor is connected to the second output terminals T2a, T2b, and T2c and driven.

The voltage command vectors (V2x ^* , V2y ^* ) representing the multiphase voltage command values V2a ^* , V2b ^* , V2c ^* to be generated by the second output terminals T2a, T2b, T2c as quadrature two-phase vectors The first potential selection unit 4A outputs the switching states S21, S22, and S23 of the first power conversion unit 2 and also outputs the switching sequence SEQ and the switching period signal SWT to the voltage estimation unit 5A. Output to.
The relationship between the polyphase AC signal and the orthogonal two-phase is, for example, the following expression in complex number expression.

V2xy ^* = Kc (V2a ^* + V2b ^* exp (j2π / 3) + V2c ^* exp (j4π / 3))

  If the real part is x and the imaginary part is y, it can be defined by the following equation.

V2x ^* = Kc (V2a ^* -V2b ^* / 2-V2c ^* / 2)
V2y ^* = Kc (√3) (V2b ^* −V2c ^* ) / 2

Here, Kc is a coefficient, and when 2 / √3 (V2x ^* , V2y ^* ), the magnitude of the AC signals V2a ^* , V2b ^* , V2c ^* is √3 (peak value of interphase signal). Equivalent to.

The voltage estimation means 5A outputs vectors (V1x ′, V1y ′) representing the average voltage values output to the first output terminals T1a, T1b, T1c in quadrature two-phase, and voltage command values V2x ^* , V2y ^*. The subtraction means 7 takes the deviation and inputs it to the second potential selection means 6A. The second potential selection unit 6A outputs the switching states S31a, S32a, S31b, S32b, S31c, and S32c of the second power conversion unit group 3, and the second power conversion units 32a, 32b, and 32c The potentials P3a1> P3a2, P3b1> P3b2, and P3c1> P3c2 of the second DC potential groups 31a, 31b, and 31c are selected to output a voltage, and the first power is supplied to the second output terminals T2a, T2b, and T2c. A voltage in which the voltage output from the second power conversion means group 3 is superimposed on the voltage output from the conversion means 2 is output.

FIG. 9 is a configuration diagram for explaining the details of the first potential selection unit 4A according to the second embodiment of the present invention. The vector (V2x ^* , V2y ^* ) representing the command value of the voltage to be generated by the second output terminals T2a, T2b, T2c in quadrature two-phase is calculated by the amplitude calculation means 409, and the division means 402 The signal is divided by a signal obtained by multiplying the potential difference between the potentials P11 and P12 of the first DC potential group 1 by a gain 415, and is input to the switching period calculation means 413.
The voltage command value vector (V2x ^* , V2y ^* ) is calculated by the phase calculation means 410 and input to the switching period calculation means 413 via the phase interval calculation means 412 and the interval phase calculation means 411. The switching period calculation means 413 calculates the switching period signals SWT1a, SWT1b, and SWT1c and inputs them to the subtraction means 404a, 404b, and 404c via the sample hold means 407a, 407b, and 407c.

  Switching period signals SWT1a, SWT1b, SWT1c and reference signal generation by subtracting means 404a, 404b, 404c and comparison means composed of function means 405a, 405b, 405c that becomes 0 when the input is negative and 1 otherwise. As a result of comparison with the reference signal SWT0 generated by the means 401, SW1a, SW1b, and SW1c are input to the switching pattern selection means 406. In the switching pattern selection unit 406, the switching states S21 and S22 of the first power conversion unit 2 based on the switching pattern SEQ generated by the switching pattern generation unit 414 and the comparison results SW1a, SW1b, and SW1c according to the phase interval calculation unit 412. , S23 is output. The reference signal SWT0 is sampled and held by the sampler 408, and is output to the voltage estimating means 5 together with the switching periods SWT1a ', SWT1b', and SWT1c 'similarly sampled and held (a signal indicated as signal SWT' in the figure).

FIG. 10 is a configuration diagram for explaining the details of the voltage estimating means 5A according to the second embodiment of the present invention. The voltage matrix Vabc is multiplied by the voltage vector conversion means 509a, 509b, 509c, 509d for each sequence of the switching pattern SEQ to obtain the voltage vectors V1xy, V2xy, V3xy, V4xy. The switching period signals SWT1a ′, SWT1b ′ and SWT1c ′ are subtracted from the reference signal SWT0 ′ by the subtracting means 501a, 501b and 501c and limited by the limiter means 503a, 503b and 503c. The limited signals are multiplied by the subtracting means 501d, 501e, 501f and the multiplying means 505a, 505b, 505c, 505d, subtracted, synthesized by the adding means 507, and periods TV1xy ′, TV2xy ′, TV3xy ′ and TV3xy ′ are calculated.
Then, normalization is performed by the dividing unit 508 to calculate an average vector (SSx ′, SSy ′) for a predetermined period, and the signal obtained by multiplying the potential difference P11-P12 of the first DC potential group 1 by the gain 510 is multiplied by the multiplying unit 51. The average potential vector (V1x ′, V1y ′) is output.

FIG. 11 is a block diagram for explaining the details of the second potential selecting means 6A according to the second embodiment of the present invention. A difference vector between the voltage command value vector (V2x ^* , V2y ^* ) and the average potential value vector (V1x ′, V1y ′) is input to the amplitude calculation means 608 and the phase calculation means 609. The output of the amplitude calculation means 608 is divided by a signal obtained by adding the difference between the potentials P3a1 and P3a2 of the second DC potential groups 31a, 31b, and 31c, P3b1 and P3b2, and P3c1 and P3c2 by the adding means 611 and then multiplying by the gain 610. Divided by means 612 and input to switching period calculation means 615.
The output of the phase calculation means 609 is input to the switching period calculation means 615 via the phase interval calculation means 614 and the interval phase calculation means 613. The switching period calculation means 615 calculates the switching period signals SWT21a, SWT21b, SWT21c, SWT21d, SWT21e, SWT21f, and through the sample hold means 607a, 607b, 607c, 607d, 607d, 607f (SWT21a ′, SWT21b in the figure). ', SWT21c', SWT21d ', SWT21e', SWT21f ') and the subtracting means 604a, 604b, 604c, 604d, 604e, 604f.

  By the subtracting means 604a, 604b, 604c, 604d, 604e, 604f and the comparing means constituted by the function means 605a, 605b, 605c, 605d, 605e, 605f which becomes 0 when the input is negative and 1 otherwise. As a result of comparing the sampled and held switching period signals SWT21a ′, SWT21b ′, SWT21c ′, SWT21d ′, SWT21e ′, and SWT21f ′ with the reference signal SWT20 generated by the reference signal generating means 601, SW21a, SW21b, SW21c, SW21d, SW21e , SW21f is input to the switching pattern selection means 617. In the switching pattern selection unit 617, the phase pattern calculation unit 614, the phase calculation unit 613, and the switching pattern SEQ2 generated by the switching pattern generation unit 616 according to the voltage command amplitude V2k and the comparison results SW21a, SW21b, SW21c, SW21d, SW21e, Based on SW21f, the switching states S31a, S32a, S31b, S32b, S31c, and S32c of the second power conversion means group 3 are output.

Next, the operation of each unit will be described. First, the switching states S21, S22, S23 are output from the voltage command value vector (V2x ^* , V2y ^* ), and the first power conversion means 2 outputs an electric potential to the first output terminals T1a, T1b, T1c. explain.
V2x ^* and V2y ^* are orthogonal AC signals, and can be given by the following equation, for example.

V2x ^* = V ^* cos (θ ^* )
V2y ^* = V ^* sin (θ ^* )

The amplitude calculation means 409 calculates the square root of the square sum of V2x ^* and V2y ^* . As a result, the output of the amplitude calculation means 409 becomes V ^* . Then, the division means 402 divides by K (P11-P12) and outputs V2k. Here, K is a constant set according to the level of the voltage command value vector. For example, the maximum value of V ^* is the fundamental wave line of the AC voltage output to the first output terminals T1a, T1b, T1c. If the inter-peak value is set, the maximum value is P11-P12, and if K = 1, the maximum value of V2k is 1.0.
The phase calculation means 410 calculates the arc tangent of V2y ^* / V2x ^* , and the output is a phase θ ^{* in} the range of 0 to 2π. For the two potential differences P11-P12 of the first DC potential group 1, depending on the state of the switches S21, S22, S23 of the first power conversion means 2, the first output terminals T1a, T1b, T1c Eight voltage vectors v0, v1, v2, v3, v4, v5, v6, v7 are output.

According to the switching state of S21, in the first power conversion means 2, when S21 is 0, the low potential P12 of the first DC potential group 1 is set, and when S21 is 1, the high potential of the first DC potential group 1 is set. P11 is output to the first output terminal T1a. Similarly, the potential of P11 or P12 is output to the first output terminals T1b and T1c, respectively, according to the switching states of S22 and S23.
Considering a plane in which the potentials of the first output terminals T1a, T1b, T1c are P1a, P1b, P1c, (2P1a-P1b-P1c) / √3 is the horizontal axis, and (P1b-P1c) is the vertical axis, the switch In this state (S21, S22, S23), eight points are drawn as shown in FIG. The switch state of each voltage vector is v0: (0, 0, 0), v1: (1, 0, 0), v2: (0, 1, 0), v3: (1, 1, 0), v4: (0, 0, 1), v5: (1, 0, 1), v6: (0, 1, 1), v7: (1, 1, 1), and v0 and v7 are the same on the plane. (Origin). On this plane, the voltage command value vector is a value with V2x ^* as the horizontal axis and V2y ^* as the vertical axis. When the amplitude of the AC signal is constant, the locus on the plane is a circle.

The phase interval calculation means 412 outputs a phase interval of every π / 3 as an integer of 0, 1, 2,... 5 according to the phase θ ^* . That is, Nth2 = 0 when 0 ≦ θ ^* <π / 3, and Nth2 = 1 when π / 3 ≦ θ ^* <2π / 3. The section phase calculation means 411 outputs V2th by limiting the phase for each phase section to 0 to π / 3. Therefore, the relationship of phase θ ^* = V2th + Nth2π / 3 is established. The switching pattern generator 414 outputs a switching pattern for each phase interval. When the phase θ ^* is 0 to π / 3, (v0, v1, v3, v7), (v0, v2, v3, v7) for π / 3 to 2π / 3, (v0, v2 for 2π / 3 to π) , V6, v7) (v0, v4, v6, v7) for 3π / 3-3π / 3 (v0, v4, v5, v7) (v0, v4, v5, v7) for 5π / 3-3π (v0 , V1, v5, v7) are output to SEQ.

  The switching period calculation means 413 outputs switching period signals SWT1a, SWT1b, and SWT1c in relation to the switching pattern SEQ representing the transition of the vectors output to the first output terminals T1a, T1b, and T1c. If the switching pattern SEQ is completed in the T period, SWT1a is a ratio of the T period of the period in which the first element vector of the switching pattern is continued, and SWT1b is a period in which the vector of the second element of the pattern continues in addition to SWT1a. The ratio of the T period, SWT1c, further outputs the ratio of the T period of the period in which the vector of the third element of the pattern continues. Since the switching pattern when the phase interval is 0 is (v0, v1, v3, v7), the origin (v0 and v7) and the two points v1, v3 are selected on the plane described above, and these three A time distribution in which each point (vector) continues is given according to the amplitude V2k, the phase V2th, and the phase interval Nth2 of the voltage command value so that the time average by the points becomes the voltage command value vector. When the periods of the voltage vectors v0, v1, v3, and v7 are Tv0, Tv1, Tv3, and Tv7, the time average v ′ of the voltage vectors can be expressed by the following equation.

  v ′ = (v0 · Tv0 + v1 · Tv1 + v3 · Tv3 + v7 · Tv7) / T

  The switching period signal SWT1a is converted into a signal SWT1a ′ having a constant Ts period by the sample-and-hold means 407a having the period Ts, and the difference from the triangular wave SWT0 output from the reference signal generating means 401 is obtained by the subtracting means 404a, and the function means 405a. Is converted into a signal SW1a having a magnitude of 0 or 1. Thus, SW1a is 0 when SWT1a 'is smaller than the reference signal SWT0, and SW1a is 1 when it is larger or equal. Similarly, SWT1b and SWT1c are compared with the reference signal SWT0 by the sample and hold means 407a and 407c, the subtraction means 404b and 404c, and the function means 405b and 405c to obtain signals SW1b and SW1c having a magnitude of 0 or 1.

  Then, the switching pattern selection means 406 selects the voltage vector of the switching pattern SEQ according to SW1a, SW1b, and SW1c and outputs the switching states S21, S22, and S23. (SW1a, SW1b, SW1c) changes as (0, 0, 0) → (1, 0, 0) → (1, 1, 0) → (1, 1, 1) as the reference signal SWT0 increases. , (0,0,0) is the first voltage vector of SEQ, (1,0,0) is the second, (1,1,0) is the third, (1,1,1) Select the fourth voltage vector. The period from (0,0,0) to (1,0,0) transitions to SWT1a ', and the period from (1,0,0) to (1,1,0) transitions to SWT1b'-SWT1a The period until transition from (1,1,0) to (1,1,1) depends on SWT1c'-SWT1b ', which corresponds to the period in which the SEQ voltage vector should last.

When the reference signal SWT0 decreases, on the contrary, (1,1,1) → (1,1,0) → (1,0,0) → (0,0,0) and the fourth of the SEQ To the first voltage vector. Then, a switching state is output according to the selected voltage vector. As a result, the first output terminals T1a, T1b, and T1c operate so that the average voltage vector during the ½ cycle of the reference signal SWT0 becomes the voltage command value vector. This method is known as the instantaneous space voltage vector PWM as described above.
A signal SWT0 ′ obtained by sampling the switching period signals SWT1a ′, SWT1b ′, SWT1c ′ and the reference signal SWT0 at the sampling period Ts by the sampling unit 408 is output to the voltage estimation unit 5A (a signal indicated as SWT ′ in the figure).

Next, the operation of the voltage estimation unit 5A will be described. Subtracting means 501a subtracts SWT0 ′ sampled from the reference signal from switching period signal SWT1a ′. Then, the limit means 503a limits the minimum value 0 and the maximum value Δ. Δ is the ratio between the period Ts and the half period of the triangular wave of the reference signal SWT0, and is equal to the magnitude that SWT0 ′ changes in the Ts period.
When SWT1a′−SWT0 ′ is equal to or greater than Δ, the voltage vector does not change within the Ts period, and the first voltage vector of SEQ is output. When SWT1a′-SWT0 ′ is 0 or less, it means that the first voltage vector of SEQ is not output in the Ts period. When SWT1a′−SWT0 ′ is larger than 0 and smaller than Δ, the first voltage vector of SEQ is output during a part of the Ts period, and another voltage vector is output during the remaining period. Further, the switching period signal SWT1b ′ is calculated by the subtraction unit 501b and the limit unit 503b, and when SWT1b′−SWT0 ′ is larger than Δ, the remaining period outputs the second voltage vector, and is subtracted. The period is calculated by means 501d. Similarly, the subtracting means 501e and 501f output the period during which the third and fourth voltage vectors are output.

On the other hand, the voltage vector conversion means 509a converts the first voltage vector, which is the first element of SEQ, into orthogonal coordinates. V1xy is (0,0) when the first element is v0 or v7, (2 / √3,0) when v1 is, (−1 / √3,1) when v2 is, and when v1 is v3 In the case of (1 / √3, 1), v4, (−1 / √3, −1), in the case of v5, (1 / √3, −1), in the case of v6, (−2 / √3, 0) )
Similarly, V2xy, V3xy, and V4xy become the coordinates of the second, third, and fourth voltage vectors by the vector conversion units 509b, 509c, and 509d. Then, the output of the limit means 503a corresponding to the period of the first voltage vector and V1xy, the output of the subtraction means 501d corresponding to the period of the second voltage vector, V2xy, and the period of the third voltage vector. After the output of the subtracting means 501e and V3xy and the output of the subtracting means 501f corresponding to the period of the fourth voltage vector and V4xy are multiplied by the multiplying means 505a, 505b, 505c and 505d, respectively, and added by the adding means 507 When the division means 508 divides by Δ, the coordinate values (SSx ′, SSy ′) of the average voltage value vector in the Ts period are obtained.
Further, the multiplication means 51 multiplies K (P11−P12) to calculate the average voltage value vector (V1x ′, V1y ′) in the Ts period. The value of the gain 510 is the same value as the gain 415.

  FIG. 14 shows a waveform example until the coordinate values (SSx ′, SSy ′) of the average voltage value vector are calculated from the switching period signals SWT1a ′, SWT1b ′, SWT1c ′. Here, SWT1a ', SWT1b', and SWT1c 'calculated by the switching period calculation means 413 are constant and have values of 0.1, 0.3, and 0.9, respectively. The figure shows the phase interval 0, and the switching pattern is (v0, v1, v3, v7). Further, Ts indicates a case of ¼ of the half cycle of SWT0. The vector changes at the intersection of SWT1a ', SWT1b', SWT1c 'and SWT0, and switching states S21, S22, and S23 are determined.

In the first Ts period, since SWT1a ′ is 0.1, TV1xy ′ = 0.1 during the period in which the voltage vector v0 is selected, and SWT1b ′ is ¼ of the magnitude 1.0 of SWT0. Therefore, TV2xy ′ = 0.25−0.1 = 0.15 is obtained during the period when v1 is selected in this control period.
In the next control cycle, TV2xy ′ = 0.05, TV3xy ′ = 0.2, next is TV3xy ′ = 0.25, and in the fourth control cycle, TV3xy ′ = 0.15, TV4xy ′ = 0.1. It becomes. Thereby, the coordinate values of the average voltage value vector are calculated as shown in FIG. Then, average potential value vectors (V1x ′, V1y ′) are obtained, an example of which is shown in FIG.
(V1x ′, V1y ′) in FIG. 15 is calculated from the voltage command value vectors (V2x ^* , V2y ^* ) through the processing as shown in FIG. Then, these differences are input to the second potential selection means 6A, the voltage corresponding to the command value is output from the second power conversion means group 3, and the voltage command is supplied to the second output terminals T2a, T2b, T2c. A voltage matching the value vector is output.

Next, the operation of the second potential selection unit 6A will be described. The basic operation is the same as that of the potential selection means 4A, but the first output terminals T1a, T1b, T1c and the second output terminal T2a, depending on the switching state of (S31a, S31b, S31c, S32a, S32b, S32c) There are 64 voltage vectors output between T2b and T2c as shown in FIG.
The potential difference between the first output terminals T1a, T1b, T1c and the second output terminals T2a, T2b, T2c is V12a, V12b, V12c, and (2V12a-V12b-V12c) / √3 is the horizontal axis, (V12b-V12c ) Is a vertical axis, and when the DC potential differences P31a-P32a, P31b-P32b, and P31c-P32c are equal, the 64 voltage vectors have a plurality of identical points on the plane and 19 points. Become. From the difference vector between the voltage command value vector (V2x ^* , V2y ^* ) and the average potential value vector (V1x ′, V1y ′), the amplitude calculation means 608, the phase calculation means 609, the gain 610, the division means 612, and the section phase calculation means 613 The operation for obtaining the amplitude V21k, the phase V21th, and the interval Nth21 by the phase interval calculation unit 614 is the same as the operation for obtaining the amplitudes V2k, V2th, and Nth2 of the potential selection unit 4A.
The second power conversion means group 3 has three independent potential groups P31a and P32a, P31b and P32b, and P31c and P32b. Therefore, if the potential difference between the potential groups is added by the adding means 611 and the gain 610 is set to K = (1/3) · (1/2), V2th is π / 6 and V21k is 1.0 at the maximum.

  The switching period calculation means 615 outputs switching period signals SWT21a, SWT21b, SWT21c, SWT21d, SWT21e, and SWT21f in relation to the switching pattern SEQ2 representing the transition of the output voltage vector. The switching pattern SEQ2 is completed in the Ts period, the SWT 21a is the ratio of the period of continuing the first element vector of the switching pattern SEQ2 to the Ts period, and the SWT 21b is of the period of continuing the second element vector of the switching pattern SEQ2. A signal obtained by adding a ratio to the SWT 21a, and a SWT 21c is a signal obtained by adding a ratio of the period of continuing the third element vector of the switching pattern SEQ2 to the Ts period. Thus, SWT21a to SWT21f are determined for seven voltage vectors.

The switching pattern is set for four regions for each phase interval. V21k <1 / (2sin (π / 3 + V21th)) in region 0, 1 / (2sin (π / 3−V21k)) ≦ V21k <1 / (sin (π / 3 + V21th)) in region 1, 1 / (2sin ( V21k)) ≦ V21k <1 / (sin (π / 3 + V21th)) in region 3, 1 / (2sin (π / 3 + V21th)) ≦ V21k <1 / (2sin (π / 3−V21k)) and V21k <1 / Let (2sin (V21k)) be region 2.
For example, when the phase interval Nth21 is 0 and the region is 0, the switching pattern SEQ2 is (x0, x1, x3, x7, x3, x1, x0), and the region 1 is (x48, x49, x51, x55, x51, x49, x48), area 2 is (x32, x33, x37, x39, x37, x33, x32), area 3 is (x32, x33, x35, x39, x35, x33, x32), and each area is on a plane. It is surrounded by three points. Then, the time distribution at which each point continues is determined so that the time average of these three points becomes the voltage command value vector (V12x ^* , V12y ^* ). Each point uses a plurality of voltage vectors or the same voltage vector a plurality of times, and the time distribution of each point is further distributed in a period in which each voltage vector continues.

  The switching period signal SW21a is converted into a signal having a constant Ts period by the sample and hold means 607a having the cycle Ts, the difference from the reference signal SWT20 generated by the reference signal generating means 601 is obtained by the subtracting means 603a, and the function means 605a. The signal is converted into a signal SW21a having a magnitude of 0 or 1. As a result, when the SWT 21a is smaller than the SWT 20, the SW 21a is 0, and conversely, when the SWT 21a is larger or equal, the SW 21a is 1. Similarly, the SWTs 21b to SWT21f are compared with the reference signal SWT20 by the sample and hold means 607b to 607f, the subtraction means 603a to 603f, and the function means 605a to 605f and converted to signals SW21b to SW21f having a magnitude of 0 or 1.

  Then, the switching pattern selection unit 617 selects the voltage vector of the switching pattern SEQ2 according to SW21a to SW21f and outputs the switching states S31a to S32c. (SW21a, SW21b, SW21c, SW21d, SW21e, SW21f) is (0, 0, 0, 0, 0, 0) → (1, 0, 0, 0, 0, 0) → as the reference signal SWT20 increases. (1,1,0,0,0,0) → (1,1,1,0,0,0) → (1,1,1,1,0,0) → (1,1,1,1 , 1, 0) → (1, 1, 1, 1, 1, 1), and when (0, 0, 0, 0, 0, 0), the first voltage vector of SEQ2, (1, 0 , 0, 0, 0, 0) selects the second voltage vector, and (1, 1, 1, 1, 1, 1) selects the seventh voltage vector.

The transition time from (0, 0, 0, 0, 0, 0) to (1, 0, 0, 0, 0, 0) is changed to SW21a, from (1, 0, 0, 0, 0, 0) to ( The time for transitioning to (1, 1, 0, 0, 0, 0) is proportional to the period in which the corresponding voltage vector should last, such as proportional to SW21b-SW21a.
For example, when the phase interval Nth21 is 0 and the region is 0, (S31a, S31b, S31c, S32a, S32b, S32c) is (0, 0, 0, 0, 0, 0) → (1, 0, 0, 0 , 0,0) → (1,1,0,0,0,0) → (1,1,1,0,0,0) → (1,1,0,0,0,0) → (1 , 0, 0, 0, 0, 0) → (0, 0, 0, 0, 0, 0) and the switching state is output to the second power conversion means group 3.
In the second power conversion means group 3, for example, when S31a is 1 and S32a is 0, the potential difference P3a1-P3a2 is set between the output terminals T2a and T1a, and when S31a is 0 and S32a is 1,-( P3a1-P3a2) and 0 otherwise. Thus, the average voltage value vector in the Ts period becomes the voltage command value vector (V12x ^* , V12y ^* ) between the second output terminals T2a, T2b, T2c and the first output terminals T1a, T1b, T1c. To work.

By operating as described above, the second power conversion means group 3 operates so as to correct the potential output from the first power conversion means 2, and the second output terminals T2a, T2b, and T2c have voltage commands. Potentials corresponding to the values V2a ^* , V2b ^* , and V2c ^* are output, and a voltage can be supplied to the load.
The range that can be output by the first power conversion means 2 is the range shown in FIG. 12, and the range that can be output by the second power conversion means group 3 is the range shown in FIG. 13, which is controlled on these planes. A sinusoidal voltage that can be output to the maximum with respect to the first DC potential group 1 and the second DC potential groups 31a, 31b, 31c can be obtained.
The fundamental wave component of the voltage output from the first power conversion means 2 to the first output terminals T1a, T1b, T1c substantially matches the fundamental wave component required by the load, and the main energy is the first DC power. Supplied from the position group 1 to the load. Therefore, the energy required by the second DC potential groups 31a, 31b, 31c can be kept to a minimum.

In this embodiment, the switching pattern SEQ2 is composed of seven voltage vectors. However, if a voltage vector including three points surrounding the voltage command value vector V12x ^* is selected on the plane of FIG. Accordingly, it can be realized by configuring the number of signals (SWT21a to SWT21f, SW21a to SW21f) related to the switching period.
The first DC potential group 1 and the second DC potential groups 31a, 31b, 31c can have two or more potentials, and the first potential selection means 4A, second This can be realized by configuring the potential selection means 6A. For example, when the potential of the first DC potential group 1 is three, the number of switching states is different in place of FIG. 12, but the voltage vector exists at the same point as on the plane of FIG. Similar to 6A, the switching period and switching pattern of the first potential selection means 4A can be configured.

Embodiment 3 FIG.
FIG. 16 is a configuration diagram for explaining the second potential selection unit 6B of the power conversion device according to the third embodiment of the present invention. Except for the potential selection means 6B, the control means is the same as the control means of the power conversion apparatus according to the second embodiment, and a description thereof will be omitted.
The section phase V21th is input to the function unit 619 and becomes the upper limit value of the upper limit unit 618. The amplitude V21k is input to the upper limit means 618, and the subtraction means 620 obtains an amplitude deviation dV21k between the input and output of the upper limit 618. Multiplication means 622 multiplies the output of subtraction means 620 and the output of gain means 610, and outputs voltage deviation dV21. The output of the multiplication unit 622 and the output of the phase calculation unit 609 are input to the coordinate conversion unit 621 to obtain the orthogonal coordinate components dV21x and dV21y of the voltage deviation.
The outputs dV21x and dV21y of the coordinate conversion means 621 are delayed by the Ts period by one sample delay means 624a and 624b and added to the voltage command values V12x ^* and V12y ^* by the addition means 623a and 623b, respectively.

Next, the operation will be described. FIG. 12 and FIG. 13 are diagrams showing voltages that can be output by the first power conversion means 2 and the second power conversion means group 3 on an orthogonal coordinate plane. The potentials of the second output terminals T2a, T2b, and T2c are obtained by adding the potentials of the first power conversion unit 2 and the second power conversion unit group 3. The vector diagram which shows the operation example in case the potential difference P3a2-P3a2, P3b2-P3b2, P3c2-P3c2 of the 2nd DC potential group is 1/2 or less with respect to the potential difference P11-P12 of the 1st DC potential group 1. As shown in FIG.
For example, as shown in FIG. 17, when the voltage command values (V2x ^* , V2y ^* ) are at point A and the average voltage values (V1x ′, V1y ′) of the first power conversion means 2 during the Ts period are at point B. Then, the voltage to be output by the second power conversion means group 3 is the difference between them, but is within the outputable range. However, when the voltage command value is at the point A ′, it is out of the range in which the second power conversion means group 3 can output, and the potential applied to the load cannot match the voltage command value.

In the third embodiment shown in FIG. 16, the function means 619 calculates the amplitude that can be output from the section phase V21th. This signal represents the outer periphery represented by a hexagon on the voltage vector plane shown in FIG. Therefore, the deviation dV21k between the signal limited by the upper limit means 618 and the amplitude V21k represents a magnitude exceeding the range that can be output by the second power conversion means group 3. It is clear that the amplitude deviation dV21k is 0 when the amplitude V21k is less than or equal to the output of the function means 619. When the amplitude deviation is not 0, the output is multiplied by the output of the gain unit 610 and the multiplication unit 622 to be converted into a voltage level.
Then, the voltage deviation dV21 is converted into a rectangular coordinate value by the coordinate conversion means 621. That is, it is expressed by the following expression from the output θ21 of the phase calculation means 609 and the voltage deviation dV21.

dV21x = dV21 cos θ21
dV21y = dV21sin θ21

The voltage deviations (dV21x, dV21y) are added to the voltage command values (V12x ^* , V12y ^* ) with a delay of one sample in the sample period Ts. Therefore, the component which cannot be output by adding the excess in the next sample is corrected, and even when the second power conversion means group 3 is saturated, the voltage command value (V2x ^* , V2y ^* ) and the second output terminal are immediately It operates so that the output potentials of T2a, T2b, and T2c coincide.

FIG. 18 is a voltage vector diagram showing how voltage deviations (dV21, dV21y) are added, and FIG. 19 shows a waveform example showing an example of how the voltage deviation is eliminated over time. In FIG. 18A, voltage command value vectors (V2x ^* , V2y ^* ) move on a circle and indicate the current voltage vector and the voltage vector one control cycle before. A vector from an average voltage value (V1x ′, V1y ′) with respect to a voltage command value vector one control cycle before is a command value vector (V12x ^* , V12y ^* ) given to the second potential selection means 6B.
Then, the deviation of two control cycles before is added to obtain an actual command value vector (V12x2 ^* , V12y2 ^* ) of one control cycle. FIG. 18B shows the voltage vector of the second power conversion means group 3, and the actual command value vector (V12x2 ^* , V12y2 ^* ) before one control cycle exceeds the output possible range and is a deviation vector. (DV21, dV21y) is generated. In FIG. 18A, the deviation vector is added to the command value vector for the current average voltage (V1x ′, V1y ′) to calculate the current actual command value vector (V12x2 ^* , V12y2 ^* ). .

The operation is performed by sequentially adding the deviation vectors as described above, and FIG. 19 shows the temporal transition as a waveform example. The three waveforms in FIG. 19A are comparative examples when the deviation vector is not corrected, and correspond to those obtained by the method of the second embodiment. In this figure, in addition to the voltage command value vector (V2x ^* , V2y ^* ) and the average voltage value vector (V1x ′, V1y ′), the average voltage (V2x, V2y) of the second output terminal is shown. In addition, the third waveform shows the magnitude of the deviation vector. Comparing the voltage command value vectors (V2x ^* , V2y ^* ) with the average voltage values (V2x, V2y), deviations occur at two locations, V2x on the negative side and V2y on the positive side.

  On the other hand, the three waveforms in FIG. 19B are waveform examples according to the third embodiment. However, after a negative deviation occurs in V2x, it shifts to a positive deviation and the average value is a command value. It is working to match the vector. Similarly for V2y, deviations occur on both the positive and negative sides to suppress average fluctuation. FIG. 20 shows, as an example of the effect, the second output terminal (first stage) when the second output terminal is connected to a three-phase load, the load terminal voltage (second stage), and the frequency analysis result ( The third stage) is shown. In this example, compared to the case (a) of the second embodiment, the effect of reducing harmonics of 100 to 1000 Hz can be confirmed in the case (b) of the third embodiment.

According to the definition of the spatial voltage vector shown above,
V2x ^* = Kc (V2a ^* -V2b ^* / 2-V2c ^* / 2) = Kc ((V2a ^* -V2b ^* )-(V2c ^* -V2a ^* )) / 2
V2y ^* = Kc (√3) (V2b ^* −V2c ^* ) / 2
Therefore, since the operation is performed with the line voltage of the output voltage command value, the same component (zero phase) included in each phase is not controlled. On the other hand, in the case of control in each phase, there is a possibility that a zero-phase component is included depending on how the command value is given. When the control is performed in each phase, saturation by the zero-phase component occurs when the second power conversion means group 3 is saturated. However, in the present embodiment, the component is controlled by the spatial voltage vector and effectively contributes to the multiphase load. Only the second power conversion means group 3 can be used effectively.

  By operating as described above, even if the second power conversion means group 3 is temporarily saturated, it can be corrected to output a potential, even when the potential difference of the second DC potential group is low. An output with small distortion can be obtained.

Embodiment 4 FIG.
FIG. 21 is a voltage vector diagram for explaining the second potential selecting means 6B of the power conversion device according to the fourth embodiment of the present invention. The circuit configuration of this embodiment is the same as that in FIG. FIG. 21 shows a voltage vector output by the second power conversion means group 3 when the potential differences P3a1-P3a2, P3b1-P3b2, and P3c1-P3c2 of the second DC potential groups 31a, 31b, 31c are substantially the same potential difference. Is shown. In the present embodiment, in the voltage vector diagram shown in FIG. 13, the second power conversion means group 3 outputs between the second output terminals T2a, T2b, T2c and the first output terminals T1a, T1b, T1c. The voltage vector which selected the combination from which the value which added the electric potential difference of each phase to become substantially zero is shown.

Even using these voltage vectors, the second power conversion means group 3 can operate to correct the potential output from the first power conversion means 2. For example, when the load is a motor, the voltage (zero-phase voltage) proportional to the voltage applied to the load is the voltage applied to the floating capacitance existing between the winding and the ground. However, this may adversely affect other devices as conduction noise.
And this conduction noise becomes large when the switching frequency of the 1st power conversion means 2 and the 2nd power conversion means group 3 is high, or when the electric potential change per switching is large. In the present embodiment, the switching frequency of the first power conversion means 2 is lowered, the switching frequency of the second power conversion means group 3 is increased to supply a highly accurate voltage to the load, and the switching frequency is high. The voltage that affects the conduction noise of the second power conversion means group 3 can be made zero, and the conduction noise can be reduced. The method of selecting and outputting three vectors for the voltage command value is the same as in the second embodiment.

Embodiment 5 FIG.
FIG. 22 is a voltage vector diagram for explaining the second potential selecting means 6B of the power conversion device according to the fifth embodiment of the present invention. The circuit configuration of this embodiment is the same as that in FIG. FIG. 22 shows the voltage vector output by the second power conversion means group 3 when the potential differences P3a1-P3a2, P3b1-P3b2, and P3c1-P3c2 of the second DC potential groups 31a, 31b, 31c are substantially the same potential difference. Is shown. In this embodiment, in the vector diagram shown in FIG. 13, in addition to the voltage vectors of the fourth embodiment shown in FIG. 21, the voltage vectors x14, x21, x28, x35, x42, and x49 are selected. These six voltage vectors are obtained by adding the potential difference of each phase output by the second power conversion means group 3 between the second output terminals T2a, T2b, T2c and the first output terminals T1a, T1b, T1c. A voltage vector whose value is close to zero. There are seven levels of voltage (zero phase voltage) proportional to the added value of the potential difference of each phase output by the second power conversion means group 3. For example, in FIG. 13, in order of increasing potential, an example is x7>x3>x35>x0>x49>x48> x56. Therefore, the zero-phase voltage output by the second power conversion means group 3 in this embodiment is limited to zero and the next step, and the voltage vector that can be selected as an output while minimizing the influence on conduction noise. Can be maximized.

Embodiment 6 FIG.
FIG. 23 is a configuration diagram for explaining second potential selection means 6C of the power conversion device according to the sixth embodiment of the present invention. Except for the second potential selection means 6C, the control means of the power converter according to Embodiment 1 is the same as that of the control means of the power conversion apparatus according to the first embodiment, so that the description thereof is omitted. The deviation between the voltage command value V2a ^* and the average voltage value V1a ′ is input to the adding means 623a and added to the deviation signal dV21a2, and V21a2 ^* corresponding to the voltage command value of the second power conversion means group 3 is output. V21a2 ^* is input to the sample hold means 607a, and its output SWT21a ′ generates a deviation signal dV21a from the limit means 618a and the subtraction means 620a, and is delayed by the Ts period by the one sample delay means 624a. Other configurations are the same as those of the first embodiment.

Next, the operation will be described. The maximum output possible voltage of the second power conversion means 32a, 32b, 32c is limited by the potentials P3a1, P3a2, P3b1, P3b2, P3c1, P3c2 of the DC potential group. That is, in the case of the second power conversion means 32a, a voltage having a maximum amplitude of ± (P3a1-P3a2) is output between the output terminals T1a and T2a.
When the difference between the voltage command value V2a ^* and the average voltage value V1a ′ exceeds this range, the output of the second power conversion means 32a is saturated and a desired voltage can be output to the second output terminal T2a. Can not. The limit unit 618a outputs a signal in which the input SWT 21a ′ is limited to a range of ± (P3a1-P3a2), and the subtracting unit 620a subtracts it from the SWT 21a ′ so that the second power conversion unit 32a can output a magnitude that can be output. The excess deviation dV21a is calculated.
Then, the sample is delayed by the Ts period by the one sample delay means 624a and added to V2a ^* −V1a ′ to be corrected. As a result, an operation is performed so that the amount of SWT 21a ′ that is temporarily saturated is corrected in the next and subsequent cycles, and on average, the voltage of the second output terminal T2a matches the voltage command value V2a ^* .

  FIG. 24 shows an example of operation waveforms. This is an example in which the P3a1-P3a2 level is lower than the operation waveform example of FIG. 6, and the SWT 21a 'temporarily exceeds the SWT 20a. The second stage of FIG. 24 shows the deviation dV21a, which corresponds to the excess amount. Then, the saturation is eliminated at the third control cycle (Ts) after the occurrence of excess. In the case where the load connected to the second output terminal T2a has an inductance or in the case of an electric motor, if the fluctuation in voltage integration (magnetic flux) is suppressed, the current fluctuation is suppressed. The second power conversion means group 3 operates so that the integration of the voltage deviation caused by the saturation becomes zero, and has an effect of suppressing load fluctuation. The same operation is performed for the other phases.

  By operating as described above, even if the second power conversion means group 3 is temporarily saturated, it can be corrected to output a potential, and even if the potential difference of the second DC potential group is low, distortion is caused. A small output can be obtained.

  Moreover, in each modification of this invention, since a 1st power conversion means outputs a 1st output voltage by pulse width modulation control for every predetermined repetition period, it is a 1st output voltage by simple structure operation | movement. I can definitely get it.

  In addition, since the second power conversion means outputs the second output voltage by pulse width modulation control at the same period as the sampling period, the second output voltage can be reliably obtained with a simple configuration operation. .

  In addition, since the voltage of the first DC power supply is made larger than the voltage of the second DC power supply and the repetition period is longer than the sampling period, a highly accurate and efficient power conversion device is realized utilizing the characteristics of the switching element. I can do it.

  Further, the second power conversion means determines the deviation when the deviation between the voltage command value and the average voltage value exceeds the upper limit set value set corresponding to the output voltage upper limit value of the second power conversion means. Since the limit means for subtracting the output up to the upper limit set value is provided and the subtraction is added to the deviation input in the next sampling period, the accuracy of the output voltage even if the output of the second power conversion means is insufficient Can be minimized.

  The voltage command value is set by a voltage vector, and the first voltage conversion unit and the second power conversion unit are set in advance according to the switching state of the switching element based on the voltage command value set by the voltage vector. The voltage vector selection means for selecting the voltage vector to be controlled from the plurality of voltage vectors is output and the three-phase voltage is output, so that the conversion control of the three-phase voltage becomes simple.

Further, the voltage vector selection means of the second power conversion means is a control target from among a plurality of voltage vectors, the value obtained by adding the second output voltages of each phase being zero or the next largest voltage vector after zero. Therefore, the zero-phase component of the three-phase output voltage can be effectively suppressed, and the influence on the conduction noise in the load can be minimized.

It is a block diagram for demonstrating the power converter device by Embodiment 1 of this invention. It is a block diagram for demonstrating the detail of the 1st electric potential selection means 4 of FIG. It is a block diagram for demonstrating the detail of the voltage estimation means 5 of FIG. It is a block diagram for demonstrating the detail of the 2nd electric potential selection means 6 of FIG. It is a wave form diagram explaining an example of the operation | movement by Embodiment 1 of this invention. It is a wave form diagram explaining an example of the operation | movement by Embodiment 1 of this invention. It is a wave form diagram explaining the effect of the operation | movement by Embodiment 1 of this invention. It is a block diagram for demonstrating the power converter device by Embodiment 2 of this invention. It is a block diagram for demonstrating the detail of the 1st electric potential selection means 4A of FIG. It is a block diagram for demonstrating the detail of the voltage estimation means 5A of FIG. It is a block diagram for demonstrating the detail of the 2nd electric potential selection means 6A of FIG. It is a voltage vector diagram which shows an example of the operation | movement by Embodiment 2 of this invention. It is a voltage vector diagram which shows an example of the operation | movement by Embodiment 2 of this invention. It is a wave form diagram which shows an example of the operation | movement by Embodiment 2 of this invention. It is a wave form diagram which shows an example of the operation | movement by Embodiment 2 of this invention. It is a block diagram for demonstrating the 2nd electric potential selection means 6B of the power converter device by Embodiment 3 of this invention. It is a voltage vector diagram which shows an example of the operation | movement by Embodiment 3 of this invention. It is a voltage vector diagram which shows an example of the operation | movement by Embodiment 3 of this invention. It is a wave form diagram which shows an example of the operation | movement by Embodiment 3 of this invention. It is a wave form diagram which shows an example of the operation | movement by Embodiment 3 of this invention. It is a voltage vector diagram for demonstrating the 2nd electric potential selection means 6B of the power converter device by Embodiment 4 of this invention. It is a voltage vector diagram for demonstrating the 2nd electric potential selection means 6B of the power converter device by Embodiment 5 of this invention. It is a block diagram for demonstrating the 2nd electric potential selection means 6C of the power converter device by Embodiment 6 of this invention. It is a wave form diagram which shows an example of the operation | movement by Embodiment 6 of this invention.

Explanation of symbols

1 first DC potential group, 2 first power conversion means, 3 second power conversion means group,
4, 4A first potential selection means, 5, 5A voltage estimation means,
6, 6A, 6B, 6C second potential selection means, 31a to 31c second DC potential group,
32a to 32c Second power conversion means.

Claims (7)

A first DC power source, a first power converter for outputting a first output voltage based on the first DC power source so as to follow a voltage command value which is an AC signal by an on / off operation of the switching element, a predetermined sampling Voltage estimation for calculating an average value of the first output voltage waveform output from the first power conversion means for each period, and estimating and outputting an average voltage value of a waveform obtained by connecting the average value for each sampling period A second output voltage based on the second DC power supply so as to follow the deviation between the voltage command value and the average voltage value by the on / off operation of the means, the second DC power supply, and the switching element. Power conversion means,
The power converter which outputs the voltage which superimposed the said 2nd output voltage on the said 1st output voltage as a voltage which responds to the said voltage command value. 2. The power conversion apparatus according to claim 1, wherein the first power conversion means outputs the first output voltage by pulse width modulation control for each predetermined repetition period. 3. The power conversion apparatus according to claim 2, wherein the second power conversion means outputs the second output voltage by pulse width modulation control for each cycle that is the same as the sampling cycle. 4. The power conversion device according to claim 3, wherein the voltage of the first DC power supply is made larger than the voltage of the second DC power supply, and the repetition period is made longer than the sampling period. When the deviation between the voltage command value and the average voltage value exceeds the upper limit set value set corresponding to the output voltage upper limit value of the second power conversion means, the second power conversion means 5. The apparatus according to claim 1, further comprising a limit unit that subtracts a deviation up to the upper limit set value and outputs the subtraction, and adds the subtraction to the deviation input in a next sampling period. The power converter device described in 1. The voltage command value is set by a voltage vector, and the first voltage conversion unit and the second power conversion unit are responsive to the switching state of the switching element based on the voltage command value set by the voltage vector. 6. The voltage vector selecting means for selecting a voltage vector to be controlled from a plurality of preset voltage vectors, and outputting a three-phase voltage, according to any one of claims 1 to 5, Power conversion device. The voltage vector selection means of the second power conversion means is a control object from among the plurality of voltage vectors, the value obtained by adding the second output voltages of each phase being zero or the next largest voltage vector after zero. 7. The power conversion apparatus according to claim 6, wherein the voltage vector is selected.

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