JP4963194B2 - Filter processing device, multiplier, and motion compensation processing device - Google Patents

Description

  The present invention relates to a filter processing device and a multiplier suitable for executing a filter operation in a motion compensation process used for compression coding / decoding of a moving image, and a motion compensation processing device including these.

  H. has been decided to be adopted for the next generation DVD (Digital Versatile Disk) and DTV (digital television). There are new codecs such as H.264 / AVC and VC-1. In these decoding apparatuses, the filter operation of the motion compensation prediction filter in the motion compensation unit may be configured by a multiplier to which Booth's algorithm is applied.

  The operation time of the multiplier is the sum of the time required to add the partial products and the time required to absorb the carry signal. In order to increase the operation speed, the processing time can be shortened. It becomes a problem. As a countermeasure, it is necessary to reduce the number of partial products in order to reduce the number of adder circuits. For this purpose, partial products can be reduced by grouping together a plurality of bits having consecutive multipliers and generating a partial product corresponding to this group. Therefore, the secondary booth is used to reduce the partial product number. The secondary booth is a partial product reduction technique to which an algorithm is applied in which a multiplier is divided every 2 bits, and a total of 3 bits of the most significant bits of each group and the lower group are combined.

  However, when the codec filter operation as described above is performed by a multiplier to which the Booth algorithm is applied, a large number of multipliers are required and the circuit scale increases. Similarly, H. When the filter operation used to generate a predicted image in the H.264 intra-screen prediction is applied by a multiplier to which the Booth algorithm is applied, the circuit scale increases.

  This is because of H.C. This is because standards such as H.264 and VC-1 require extremely complicated calculations as compared to conventional MPEG (Moving Picture Experts Group) 2 and the like. Table 1 below shows MPEG2, H.264. H.264, VC-1 functional comparison.

Conventionally, a technique for reducing the scale of a motion compensation filter arithmetic circuit is disclosed in Patent Document 1. FIG. 12 is a block diagram showing a cumulative addition filter (digital filter) in the image processing apparatus described in Patent Document 1. As shown in FIG. 12, the conventional digital filter measures the number of pixel lines of the input image signal, and the counter modulo thereof is selectively switched according to the enlargement / reduction ratio, and the coefficient value of the counter 503 is set. A coefficient data memory 502 that outputs the corresponding filter coefficient, a multiplier 501 that multiplies the input image signal by the filter coefficient, a cumulative addition memory 506 that holds the output of the multiplier 501 or a cumulative addition value, and a multiplier 501 An adder 504 that adds the content held in the cumulative addition memory 506 to the output, and a selector 505 that selectively transmits the output of the multiplier 501 or the adder 504 to the cumulative addition memory 506 in accordance with the coefficient value of the counter 503. The required hardware amount is reduced by using one multiplier 501 and one adder 504 and obtaining a filter output by cumulative calculation.
JP 2001-160140 A

  However, as in Patent Document 1, even if an attempt is made to reduce the amount of hardware by cumulative calculation, the number of steps increases and the processing speed becomes slow, which is not realistic. In particular, H.C. When the number of taps of a filter such as H.264 or VC-1 is large, the calculation becomes complicated, and thus there is a problem that the processing speed is further reduced.

  A filter processing apparatus according to the present invention is a filter processing apparatus that performs a product-sum operation on a plurality of filters using a Booth algorithm for a plurality of input data and a plurality of filter coefficients constituting the filter. And one or more sets of data composed of filter coefficients associated with the input data are input and generated by a plurality of partial product generation units that generate one or more partial products and the plurality of partial product generation units An addition unit that generates a sum of partial products, and a partial product generation unit selection unit that selects one or more of the plurality of partial product generation units and inputs the set data according to the set data.

  In the present invention, when a partial product to be generated from one set of data cannot be generated by one partial product generation unit, a partial product is generated using two or more partial product generation units. The calculation capability or circuit scale of each partial product generation unit can be kept low.

  According to the present invention, it is possible to provide a filter processing device, a multiplier, and a motion compensation processing device using the same, which use a Booth algorithm that can reduce the amount of hardware without reducing the processing speed.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a filter processor (multiplier) that executes different types of filter operations. In this embodiment, the filter operation unit using the Booth algorithm pays attention to the function of the partial product generation unit and the filter coefficient to be a multiplier, and reduces the amount of hardware by omitting redundant circuits. In this embodiment, although described as a filter computing unit, a multiplier that multiplies a plurality of types of predetermined multiplier groups and an arbitrary multiplicand group may be used.

(1) Multiplier to which Booth's algorithm is applied The filter arithmetic unit according to the present embodiment is a filter arithmetic unit that performs multiplication using the Booth's algorithm. Here, first, in order to facilitate understanding of the present invention, a multiplier using a second order Booth algorithm will be described.

Multiplier Y is a signed 8-bit integer Y = −y [7] · 2 ⁷ + y [6] · 2 ⁶ + y [5] · 2 ⁵ + y [4] · 2 ⁴ + y [3] · 2 ³ + y [2]・ 2 ² + y [1] ・ 2 ¹ + y [0] ・ 2 ⁰
Then, the product P = X × Y with the multiplicand X, which is an arbitrary integer, is as follows.

What calculates (−2 · y [2i + 1] + y [2i] + y [2i-1]) is a booth decoder, X × (−2 · y [2i + 1} + y [2i] + y [2i-1]) × 2 ²ⁱ is called partial product. In this specification, the decode value (−2 · y [2i + 1] + y [2i] + y [2i−1]) obtained by the Booth decoder is referred to as code data. In addition, a circuit for generating X × (−2 · y [2i + 1} + y [2i] + y [2i−1]) × 2 ²ⁱ (partial product) is a partial product generation unit, and X × (−2 · y [2i + 1} + Y [2i] + y [2i-1]) × 2 ²ⁱ , a circuit that generates a partial product corresponding to each i is represented by a partial product generation unit, code data (−2 · y [2i + 1] + y [2i] + y [ 2i-1]) is a booth decoder, a circuit that performs an operation consisting of code data × multiplicand to obtain a partial product is a multiplication unit, and a portion of the partial product that is to execute an operation of × 2 ²ⁱ is a bit shift unit. And

Here, as shown in Table 2 below, there are only eight combinations of values of the code data (−2 · y [2i + 1] + y [2i] + y [2i−1]), and 0, ± 1, ± 2 Takes only a value. Therefore, the multiplier can calculate a value (partial product) obtained by multiplying 0, ± X, ± 2X by 2 ²ⁱ and write it as a correspondence (truth table) of combinations of values to be added. Here, since there are only eight values of the code data, the booth decoder can be obtained by a simple combinational logic circuit.

Of 0, ± X, and ± 2X, 2X can be generated by a 1-bit shift. On the other hand, since the multiplicand X is expressed in the complement of 2 when generating the negative number, it is only necessary to invert each bit of X and add 1 to the least significant bit. In order to realize this, for example, a circuit (Booth decoder) that generates code data (−2 · y [2i + 1] + y [2i] + y [2i−1]) Three signals including two signals for selecting an absolute value (0, X, 2X) and one signal for selecting inversion are generated. Further, the multiplication unit receives these three signals, and when the absolute value is 0, it is 0, and when it is X, the multiplicand X In the case of 2X, the multiplicand X shifted by 1 bit is selected, and if the inversion is necessary, the value can be inverted to generate a partial product. Furthermore, the bit shift unit that executes x2 ²ⁱ may simply shift the bit line by 2i.

  FIG. 1 is a block diagram illustrating a multiplier that performs multiplication according to such a second order Booth algorithm. The multiplier 400 includes a register F0 that outputs a multiplicand X and a register F7 that outputs a multiplier Y. Furthermore, a partial product generation unit 401 that receives a multiplier Y and a multiplicand X and generates a partial product, and an adder 450 that adds the partial products generated by the partial product generation unit 401 are provided. The partial product generation unit 401 includes four partial product generation units 410, 420, 430, and 440.

  As described above, each partial product generator receives a predetermined bit of the multiplier Y, generates a code data (0, ± 1, ± 2) according to Booth's algorithm, and the obtained code data It is assumed that a multiplication unit that outputs a multiplication result with the multiplicand X and a bit shift unit that performs a bit shift of a calculation result of the multiplication unit.

Each partial product generator corresponds to “i” of X × (−2 · y [2i + 1} + y [2i] + y [2i−1]) × 2 ²ⁱ . For example, the multiplier Y is 8 bits. (Y _{0 to} y ₇ ), i = 0 to 3, and X × (−2 · y ₁ + y ₀ +0) × 2 ⁰ and X × (−2 · y ₃ + y ₂ + y _{1, respectively.} ) × 2 ² , X × (−2 · y ₅ + y ₄ + y ₃ ) × 2 ⁴ , and X × (−2 · y ₇ + y ₆ + y ₅ ) × 2 ⁶ are obtained. In FIG. 1, the partial product generation units for obtaining these partial products are 410, 420, 430, and 440, respectively. In the present embodiment, the multiplier X decoded by the Booth decoder will be described by taking 8 bits as an example, but it is needless to say that the multiplier X may be less than or more than this. In that case, what is necessary is just to adjust the number of partial product production | generation parts suitably.

Next, the operation of the multiplier 400 will be described using an actual calculation as an example. The 8-bit multiplier Y can be expressed as shown in FIG. The multiplier is divided every 2 bits, and the code data is obtained from the data of a total of 3 bits (however, y ₋₁ = 0) of the most significant bit of each group and the lower group. A partial product can be generated by multiplying these by a multiplicand and calculating a corresponding bit shift (× 2 ⁱ ). For this reason, as shown in FIG. 2B, the register F7 is composed of a shift register that outputs 8 bits, and outputs a multiplier Y {y _{0 to} y ₇ }. At this time, the partial product generator 410 has the lower two bits {y ₀ , y ₁ } of the multiplier Y, and the partial product generators 420, 430, and 440 have {y ₁ , y ₂ , y ₃ }, { Enter y ₃ , y ₄ , y ₅ }, {y ₅ , y ₆ , y ₇ }. The partial product generation unit 410 generates a code data from these inputted predetermined bits, a booth decoder 411, a multiplication unit 412 that multiplies the obtained code data and the multiplicand X, and shifts the multiplication result by a predetermined bit. A bit shift unit 413. The other partial product generation units 420, 430, and 440 are similarly configured. Here, the multiplication of the multiplicand X = 358 (166H) and the multiplier Y = 123 (7BH) will be described. Table 2 below shows each output value in the calculation process.

× Y = 358 × 123 = 44034 (AC02H)
Y = 123 (7BH)
= (-2 ・ 0 + 1 + 1) ・ 2 ⁶
+ (− 2 · 1 + 1 + 1) · 2 ⁴
+ (-2 · 1 + 0 + 1) · 2 ²
+ (-2 · 1 + 1 + 0) · 2 ⁰
= 2 · 2 ⁶ + 0 · 2 ⁴ + (− 1) · 2 ² + (− 1) · 2 ⁰
Therefore, it becomes the following.
X × Y = {(2 × 356) × 2 ⁶ }... Operation in partial product generation unit 410 + {(0 × 356) × 2 ⁴ }... Operation in partial product generation unit 420 + {( −1 × 356) × 2 ² }... Operation in partial product generation unit 430 + {(− 1 × 356) × 2 ⁰ }... Operation in partial product generation unit 440

First, “358” is input to each partial product generation unit 410, 420, 430, 440 from the multiplicand input unit F0. From the multiplier input unit F7, each partial product generation unit 410, 420, 430, 440 receives {y ₀ , y ₁ } = {1, 1}, {y ₁ , y ₂ , y ₃ } = {1, 0, 1}, {y ₃ , y ₄ , y ₅ } = {1, 1, 1}, {y ₅ , y ₆ , y ₇ } = {1, 1, 0} are input. The booth decoders 411, 421, 431, and 441 respectively receive (−2 · y [2i + 1} + y [2i] + y [2i−1]) = (− 2 · y ₁ + y ₀ +0), ( Code data corresponding to the calculation of (−2 · y ₃ + y ₂ + y ₁ ), (−2 · y ₅ + y ₄ + y ₃ ), (−2 · y ₇ + y ₆ + y ₅ ) is output. From the above equation, in this example, each booth decoder 411, 421, 431, 441 outputs “−1”, “−1”, “0”, “2”, respectively.

  Each of the multipliers 412, 422, 432, 442 calculates the code data × the multiplicand X and inputs them to the bit shift units 413, 423, 433, 443, respectively. The bit shift unit 413 outputs it to the adder 450 as it is. In this example, the bit shift unit 413 is provided for clarity of explanation, but it is not necessary to provide it. Bit shift sections 423, 433, and 443 shift the received results by 2 bits, 4 bits, and 6 bits, respectively, and input the result to adder 450.

  The adder 450 of this example includes full adders (full adders) 451 and 452, half adders (half adders) 453, and a register 454 for receiving the result. The values input from the bit shift units 413, 423, 433, and 443 are added by the adder 450 and output as the multiplication result P.

In this way, when the second-order Booth algorithm is used, the multiplier is set to 0, ± 1, ± 2 code data × 2 ²ⁱ and the calculation is performed with the multiplicand, so that the number of partial products is substantially halved. Therefore, the number of partial products to be added by the adder can be substantially halved, so that the multiplier can be reduced in size.

Here, the function of the partial product generation unit will be described. Although the partial product generation unit constituting the filter arithmetic unit includes a plurality of partial product generation units, the configuration of the partial product generation unit may be different depending on the calculation capability. That is, the partial product generation unit shown in FIGS. 1 and 2 includes four partial product generation units, and i = (X × (−2 · y [2i + 1} + y [2i] + y [2i−1]) × 2 ²ⁱ ) It has a computing capacity of up to 3 and up to x64. On the other hand, if the multiplier X can be represented by 6 bits, the partial product generation unit only needs to have three computing powers, that is, up to × 16, and if the multiplier X can be represented by 4 bits, these sets are two. That is, it only needs to have a computing capacity of x4.

  In this way, the partial product generation unit differs in the maximum number of digits that can be calculated by the partial product generation unit according to the multiplier X. Therefore, the number of partial products that can be generated is different. Further, depending on the input filter coefficient, for example, it is possible to configure such that only the x16 partial product generation unit 430 is excluded from x1, x4, x16, and x64. That is, it is possible to adopt a configuration capable of performing calculations up to x64 even with only three partial product generation units. Furthermore, the bit shift unit of the partial product generation unit corresponding to × 1 can be omitted. Further, as will be described later, the configuration of the partial product generation unit can be varied depending on the code data. That is, a partial product generation unit in which the generated code data is always “0, 1” is only required to support the code data “0, 1”. Therefore, a multiplication unit that multiplies at least the code data and the input data is unnecessary. Furthermore, the partial product generation unit in which the generated code data is always “0” only needs to support only the code data “0”. In this case, since the output is always “0”, the multiplication unit and the bit shift unit are unnecessary. As described above, when the filter coefficient input to the filter arithmetic unit is determined in advance and the code data to be generated is determined in advance, the partial product generation unit according to the code data can be configured.

  In this way, the partial product generation unit differs in the number of partial product generation units constituting it, the maximum number of digits that can be calculated, the number of partial products that can be generated, the types of code data that can be handled, etc. Can be different. Therefore, as will be described later, if a partial product generation unit having a minimum computing capacity is used in accordance with input filter coefficients, code data obtained from the filter coefficients, and the like, the circuit scale can be reduced.

(2) Principle of Hardware Reduction As described above, the filter arithmetic unit according to the present embodiment is hardware based on the calculation capability and filter coefficient (multiplier) of the partial product generation unit constituting the partial product generation unit. Reduce the amount of wear. The filter arithmetic unit according to the present embodiment is, for example, an H.264 described later. H.264 and VC-1 motion compensation processing, By applying to a computing unit that executes a filter calculation used for H.264 intra-screen prediction processing or the like, the hardware reduction effect is greatly increased. This is because these operations are performed by a filter having a large number of taps, are extremely complicated, and require a very large arithmetic circuit. Note that the present invention is not limited to the above filter calculation, and can be applied to a filter calculator that executes a plurality of filter calculations. Further, the present invention is not limited to the filter operation, and can be applied to a multiplier that multiplies a predetermined multiplier and an arbitrary multiplicand.

First, the principle of the hardware reduction of the filter arithmetic unit to which the Booth algorithm is applied will be described using a simple filter arithmetic example. FIG. 3 is a diagram showing filter coefficients and their code data. As shown in FIG. 3, the filter operation # 1 is
G1 = 20 * f0-8 * f1 + 1 * f2
Shall be executed. Here, f0, f1, and f2 are input data (multiplicands) to be input, and the filter coefficients (multipliers) corresponding thereto are 20, -8, and 1, respectively. Also, the filter operation # 2 is
G2 = 9 * f0-1 * f1 + 16 * f2
Shall be executed. That is, the filter coefficients in the filter calculation # 2 are 9, -1, and 16, respectively.

  FIG. 4 is a diagram showing a normal filter arithmetic unit in which the above-described multipliers are combined to perform this filter operation. The filter computing unit 500 includes a coefficient data memory 502, registers F0, F1, and F2 for inputting input data as multiplicands f0, f1, and f2, and a filter coefficient associated with the input data and the input data. It has three partial product generation units 510, 520, and 530 to which data is input, and an adder 540.

The partial product generation unit 510 receives the input data f0 and the filter coefficient “20” in the filter operation # 1 and the input data f0 and the filter coefficient “9” in the filter operation # 2 as the set data. And X × (−2 · y [2i + 1} + y [2i] + y [2i−1]) × 2 ²ⁱ (X is a multiplier) i = 0, 1, 2, ie, x1, x4, x16 513, 512, and 511 are respectively obtained for corresponding partial products.

  Similarly, the partial product generation units 520 and 530 receive the input data f1 and the filter coefficient “−8”, the input data f2 and the filter coefficient “1” in the filter operation # 1, and the input data f1 in the filter operation # 2. The filter coefficient “−1”, the input data f2, and the filter coefficient “16” are input. Also, partial product generation units 523, 522, and 521 and partial product generation units 523, 522, and 521, respectively. The adder 540 includes eight full adders 541, registers 542 and 543, and a half adder 544.

  The coefficient data memory 502 corresponds to the register F7 in FIG. 2, and can be configured as three registers. From the coefficient data memory 502, in the case of the filter calculation # 1, 20, -8, and 1 are input to the partial product generation units 510, 520, and 530, respectively. In the case of filter calculation # 2, 9, -1, and 16 are input, respectively.

  Next, the operation of the filter calculator 500 will be described. For example, in the filter operation # 1, 2 or 3 bits corresponding to the filter coefficient “20” are input to the partial product generation units 510 to the partial product generation units 513, 512, and 511. Input data (multiplicand) to be multiplied is input from the register F0. In the present embodiment, the multiplier is described as being serially input to the registers F0, F1, and F2, but may be input to the registers F0 to F2 in parallel.

  As shown in FIG. 3, the partial product generation units 511, 512, and 513 generate code data obtained by decoding the input predetermined bits according to Booth's algorithm. Then, the code data and the input data from the register F0 are multiplied, and the partial product generation unit 511 shifts the calculation result by 4 bits and outputs the result to the adder 540. The partial product generation unit 512 shifts the calculation result by 2 bits and outputs the result to the adder 540. The partial product generation unit 513 outputs the calculation result to the adder 540 as it is. The other partial product generation units 520 and 530 perform the same calculation.

  By the way, the respective code data in the filter operations # 1 and # 2 are as shown in FIG. Here, the partial product generation units 511 to 513, 521 to 523, and 531 to 533 have booth decoders (Booth Decoder: BTD) B00 to B02, B10 to B12, and B20 to B22, respectively.

  The code data (−2 · y [2i + 1] + y [2i] + y [2i−1]) calculated by each booth decoder is as shown in FIG. 5. Here, the booth decoder of the partial product generator 532 In B21, the code data is "0" in any filter operation, and there is no need to generate a partial product. In the filter operation # 1, when the code data of the booth decoder B22 of the partial product generation unit 533 is “1”, the code data of the booth decoder B02 of the partial product generation unit 513 is “0” and the partial product is There is no need to generate. On the contrary, in the filter operation # 2, the code data of the booth decoder B22 of the partial product generation unit 533 is “0”, and it is not necessary to generate a partial product, whereas the booth decoder B02 of the partial product generation unit 513 The code data is “1”, and it is necessary to generate a partial product. Similarly, in the filter operation # 2, the code data of the booth decoder B20 of the partial product generation unit 531 is “1”, the code data of the booth decoder B00 of the partial product generation unit 511 is “0”, and a partial product is generated. There is no need to do.

  Here, the partial product generation units 513 and 533 have the same function. The partial product generation unit 513 does not need to be used in the filter calculation # 1, and the partial product generation unit 533 does not need to be used in the filter calculation # 2. Further, the partial product generation units 521 and 531 have the same function, and it is not necessary to use the partial product generation unit 521 in the filter operation # 1, and it is necessary to use the partial product generation unit 531 in the filter operation # 2. Absent. Therefore, in the present embodiment, by sharing these two partial product generators 511, 531 and 521, 531, the number of partial product generators is reduced and the number of inputs to the adder at the subsequent stage is reduced. To reduce the circuit scale of the adder.

  FIG. 6 is a diagram showing a filter arithmetic unit according to the embodiment of the present invention. As shown in FIG. 6, the filter arithmetic unit 1 includes a coefficient data memory 2, registers F <b> 0 to F <b> 2 for inputting input data f <b> 0, f <b> 1, f <b> 2, partial product generation units 3, 4, and an adder 10. . Furthermore, it has selectors 5-8.

The partial product generation units 3 and 4 receive one or more set data including input data f0 to f2 and filter coefficients associated with the input data f0 to f2, and generate one or more partial products. The partial product generating units 3 and 4 respectively have X = 0 (−2 · y [2i + 1} + y [2i] + y [2i−1]) × 2 ²ⁱ (where X is a multiplier and a filter coefficient), i = 0, 1, 2, that is, partial product generation units 33, 32, and 31, and partial product generation units 43, 42, and 41 that calculate partial products corresponding to x1, x4, and x16, respectively.

  The partial product generation unit 31 includes a booth decoder B00, a multiplication unit M00, and a 4-bit shift unit S00. The partial product generation unit 32 includes a Booth decoder B01, a multiplication unit M01, and a 2-bit shift unit S01. The partial product generation unit 33 includes a booth decoder B02 and a multiplication unit M02. Similarly, in the configuration of the partial product generation unit 4, the partial product generation units 41, 42, and 43 include Booth decoders B10, B11, and B12, multiplication units M10, M11, and M12, and bit shift units S10 and S11. . The partial product generation unit 43 does not need a bit shift unit.

  The selectors 7 and 8 function as a partial product generation unit selection unit that selects a partial product generation unit to which the input data f0 to f2 are to be input. The selectors 5 and 6 function as a partial product generation unit selection unit that selects a partial product generation unit to which a filter coefficient is to be input. That is, these selectors 5 to 8 input the set data to any one or more of the partial product generation units 3 and 4. For example, the partial product generation unit 3 generates the set data from one set data. When a part of the power partial product cannot be generated, the partial product generation unit 3 inputs the set data to the partial product generation unit of the partial product generation unit 4 to generate the partial product. In other words, one set of data is calculated by a plurality of partial product generation units, not by one partial product generation unit. Thus, the filter computing unit 1 can perform the same computation as the above-described filter computing unit 500, and can reduce the partial product generation unit by one to two.

  Thus, the filter computing unit 1 according to the present embodiment does not have a partial product generation unit corresponding to the register F2 (input data f0) shown in FIG. Of the operations of the input data f2 shown in FIG. 5, the filter operation # 1 to be performed using the Booth decoder B22 is performed by the partial product generation unit 33 as a substitute partial product generation unit. That is, since the code data generated from the predetermined bits of the filter coefficient corresponding to the input data f0 of the partial product generation unit 33 is “0”, there is no need to generate a partial product, and this is used instead. For this reason, a selector 7 for selecting and outputting the data f0 from the register F0 and the data f2 from the register F2 is provided at the input of the partial product generator 33. In addition, a selector 5 is provided for switching the input of filter coefficients to the booth decoder B02 of the partial product generator 33 at this time. Since all the other operations of the input data f2 in the filter operation # 1 have the code data “0”, it is not necessary to calculate the partial product. Therefore, by providing the selectors 5 and 7, the input data f0 to f2 input to the registers F0 to F2 and the filter coefficients 20, -8, and 1 can be multiplied.

  Similarly, of the operations of the input data f2 shown in FIG. 5, the filter operation # 2 to be performed using the Booth decoder B20 is performed by the partial product generation unit 41 as the substitute partial product generation unit. That is, since the code data generated from the predetermined bits of the filter coefficient corresponding to the input data f1 of the partial product generation unit 41 is “0”, it is not necessary to generate a partial product, and this is used instead. Therefore, a selector 8 that selectively outputs data f1 from the register F1 and data f2 from the register F2 is provided at the input of the partial product generation unit 41. Further, a selector 6 is provided for switching the input of filter coefficients to the booth decoder B10 of the partial product generation unit 41 at this time. In all the other operations of F2 in the filter operation # 2, the code data becomes “0”, so there is no need to calculate the partial product. Therefore, by providing the selectors 6 and 8, multiplication of the multiplicand input to the registers F0 to F2 and the filter coefficients 9, -1, and 16 can be executed.

  In the present embodiment, the partial product generation units 3 and 4 generate partial products using inactive partial product generation units that are not used for the filter operation. At this time, set data consisting of two or more types of input data and filter coefficients associated with the input data is input to the partial product generation units 3 and 4 by the selectors 5 to 8 as necessary. The partial product generation units 3 and 4 generate partial products corresponding to the set data. In this way, in this example, the partial product generation unit can be reduced by one compared to FIG. 4 by performing another filter coefficient calculation using the inactive partial product generation unit during the filter calculation. it can.

  In particular, when executing the filter operation, if the partial products generated by the partial product generating unit having the same function in the plurality of partial product generating units are always 1 or more and 0, one partial product generating unit having the same function is provided. In summary, a partial product generation unit can be shared among a plurality of partial product generation units, and the number of partial product generation units and the number of inputs to the adder can be reduced, thereby reducing the circuit scale of the adder. be able to.

  That is, in the present embodiment, three sets of data are calculated by two partial product generation units. Usually, one set data operation is performed by one partial product generation unit. However, in this embodiment, by providing selectors 5 to 8 as partial product generation unit selection units, one set data is set. And a configuration in which two sets of data can be calculated in one partial product generation unit. As a result, in the same partial product generation unit, in the case of including a partial product generation unit in which the inactive (unused) or code data becomes “0” during the calculation of a certain set of data, the calculation of the other set data is substituted It can be used as a partial product generator. In this way, the partial product generation unit can be shared between the partial product generation units, and the number of partial product generation units can be reduced by effectively using the partial product generation unit as a whole.

(3) Specific Example Next, a specific example to which the present invention is applied will be described. Here, a case will be described in which the present invention is applied to a filter arithmetic unit that executes a filter operation in motion compensation processing in both the H.264 and VC-1 standards. In addition, this invention is H.264. A motion compensation circuit capable of performing a filter operation in both H.264 and VC-1 standards will be described. Of course, the present invention is also applicable to a motion compensation circuit that performs a filter operation of only H.264 and a motion compensation circuit that performs a filter operation of only VC-1.

(3-1) Image Decoding Device Here, first, an H.264, VC-1 image decoding device will be described. 7 and 8 are block diagrams illustrating a decoding device that decodes a compressed image encoded in accordance with H.264 and VC-1. H. H.264 is also referred to as MPEG4 AVC (Advanced Video Coding), and is a compression encoding method that can make the data compression rate more than twice that of MPEG-2 and 1.5 times that of MPEG-4. VC-1 (Windows Media Video (WMV) 9) (registered trademark) is a video compression technology developed by Microsoft Corporation. The data compression rate is about the same as H.264. These advanced codecs (high compression codecs) are applied to next-generation DVD standards such as HD DVD (High Definition DVD) or Blu-ray Disc.

  As shown in FIG. 7, the H.264 image decoding apparatus 170 includes a variable length decoding unit 172, an inverse quantization unit 173, an inverse Hadamard transform unit 174, an adder 175, a deblocking filter 176, a motion compensation unit 182 and a weighting. A prediction unit 181, an intra-screen prediction unit 180, and a monitor 179 that displays a decoded image 178 are included.

  The variable-length decoding unit 172 performs variable-length decoding on the compressed data that is input with the compressed data 171 and is variable-length encoded based on the conversion table. Then, the decoded data subjected to variable length decoding is inversely quantized by the inverse quantization unit 173, subjected to inverse Hadamard transform by the inverse Hadamard transform unit 174, and sent to the adder 175. The output of the adder 175 is subjected to block distortion removal by the deblocking filter 176 to obtain a decoded image 178, which is displayed via the monitor 179.

  Here, the output of the adder 175 is also input to the in-screen prediction unit 180, and a predicted image 183 is generated. Also, the motion compensation unit 182 performs motion compensation processing on the decoded image, and the weighted prediction unit 181 weights the decoded image to generate a predicted image 183. The adder 175 adds the prediction error to the prediction image 183 from the intra-screen prediction unit 180 and outputs it when performing the I frame processing. On the other hand, in the P and B frame processing, switching is performed by the switching unit 177, and a prediction error is added to the prediction image 183 sent from the weighted prediction unit 181 and output.

  As shown in FIG. 8, the VC-1 image decoding apparatus 190 is also configured in substantially the same manner as the image decoding apparatus 170, and includes a variable length decoding unit 192, an inverse quantization unit 193, an inverse DCT conversion unit 194, and an adder. 195, a loop filter 196, a weighted prediction unit 199, a motion compensation unit 200, and a monitor 198 for displaying a decoded image 197. The VC-1 image decoding apparatus 190 is different in that intra-screen prediction is not performed, motion compensation processing is performed after weighted prediction, and a loop filter 196 is used instead of the deblocking filter 176.

(3-2) Motion Compensation Unit FIG. 9 is a block diagram showing a motion compensation (MC) unit that executes a motion compensation process including a filter operation based on the standards of H.264 and VC-1. This motion compensation unit 150 is an H.264 standard. H.264 and VC-1 motion compensators can be used. That is, it can be shared by both standards. The motion compensation unit 150 includes filter operation units 1 c and 1 d, selectors 151, 154, 157, 160 and 161, multipliers 152 and 159, adders 153, 155 and 158, and a line memory 156.

H. In H.264, after the filter operation is performed by the filter operation units 1c and 1d, a weighted interpolation signal with an offset is obtained using the above-described weighting coefficient, and a predicted image 183 is obtained. Here, the pixel value of the reference picture R0 input from the input IN is subjected to a filter operation using a vertical filter in the filter operation unit 1c, and a filter operation using a horizontal filter is performed in the filter operation unit 1d. The generated filter-calculated data is stored in the line memory 156. Next, when the pixel value of the reference picture R1 is input from the input IN, similarly, the filter operation is performed by the filter operation units 1c and 1d, and the weighted coefficient is multiplied by the multiplier 152 by the multiplier 152 Then, the adder 153 adds the offset value. On the other hand, the data stored in the line memory is multiplied by the weighted coefficient by the multiplier 159 via the selector 160, and these are added by the adder 155, and the weighted interpolation signal W ₀ X ₀ + W ₁ X with offset is added. ₁ + D is generated. The generated data is output from the output OUT via the line memory 156.

In the case of VC-1, the data from the input IN is input to the filter arithmetic units 1c and 1d via the selector 160 and the selector 157, further from the selector 151 through the multiplier 152 and the adder 153, and via the selector 161. The The result of the filter operation unit 1d is directly stored in the line memory 156 via the selector 151 and the selector 154, and is output from the output OUT. The multiplier 159, the adder 158, the multiplier 152, and the adder 153 perform the following weighting.
H = (iScale × F + iShift + 32) >> 6
Here, F is an input value, and iScale and iShift are weighting factors.

  The motion compensator 150 configured in this way is selected by the selectors 161, 151, 154, 160 so that the inputs and outputs to the filter arithmetic units 1c, 1d are appropriately selected. Even if it is H.264, even if it is VC-1 which performs weighting before a filter calculation, it is applicable to any calculation.

(3-3) Filter computing unit The filter operation units 1c and 1e capable of performing filter operations of both H.264 and VC-1 standards will be described in more detail. FIG. 10 is a diagram showing details of the filter arithmetic units 1c and 1e, and is a block diagram showing the filter arithmetic unit according to the present embodiment. Table 4 below shows H.264. The filter coefficients for the luminance signal Gy and the color difference signal Gc in H.264 and VC-1 are shown. Further, FIG. 2 is a diagram illustrating code data generated by each partial product generation unit when the filter arithmetic unit 100 executes H.264 and VC-1 filter operations.

  As shown in Table 4, H. In H.264, the luminance signal Gy is a 6-tap filter, and the color difference signal Gc is a 2-tap filter. The luminance signal Gy of VC-1 is a 4-tap filter, and the color difference signal Gc is a 2-tap filter. The filter computing unit 1 is a hardware resource reduced by the above-mentioned method while enabling all these filter computations.

  As shown in FIG. 10, the filter arithmetic unit 1 includes registers F0 to F5 that store input pixel values (input data f0 to f5), a partial product generation unit selection unit 102, a coefficient data memory 103, a partial data Product generation units 110, 120, 130, 140, 140, 160 and an adder 104 are included. The partial product generation unit selection unit 102 selects one or more partial product generation units capable of calculating input data f0 to f5 and filter coefficients to be multiplied by the input data f0 to f5, and inputs the input data f0 to f5. The coefficient data memory 103 inputs filter coefficients corresponding to the input data f0 to f5 to each partial product generation unit. In this case, as described above, two or more sets of input data and corresponding filter coefficients are input to one partial product generation unit as necessary.

  The partial product generation unit 110 generates code data from the filter coefficients and obtains a multiplication result with input data input through any of F0 to F5, and a circuit unit (BTD · A multiplication unit) 114. The partial product generation unit 120 includes BTD / multipliers 123 and 124 corresponding to x4 and x1. In this figure, the x4, 16, and 64 bit shift units are not shown.

  The partial product generation unit 130 includes BTD / multipliers 132 and 133 corresponding to x4 and x1, respectively. The partial product generation unit 140 includes BTD / multipliers 141, 142, and 143 corresponding to x64, x16, and x4, respectively. The partial product generation unit 150 includes BTD / multipliers 153 and 154 corresponding to x4 and x1, respectively. The partial product generation unit 60 includes a BTD / multiplication unit 164 corresponding to × 1.

  In these partial product generation units, the filter coefficients input in each filter calculation are as shown in FIG. Here, for example, the partial product generation units 120, 140, 150, and 160 are not used in the calculation of the color difference signal Gc of H.264.

  By the way, in the case of the calculation of the luminance signal Gy of VC-1, the filter coefficients are −4, 53, 18, and −3, and the partial product of the filter coefficient “53” is generated regardless of which partial product generation unit is used. Can not do it. Therefore, the partial product generation unit selection unit 102 causes the partial product generation units 140 and 110 to be used in the case of the calculation of the filter coefficient “53”. The calculation of the filter coefficient “53” requires a partial product generation unit corresponding to x64, x16, x4, and x1, but the partial product generation unit 140 generates a partial product corresponding to x1. There is no part. Therefore, the partial product generation unit selection unit 102 uses the BTD / multiplication unit 114 capable of calculating x1 of the partial product generation unit 110 together with the partial product generation unit 140 to calculate the filter coefficient “53” (FIG. 11 A1).

  Further, for the calculation of the filter coefficient “18”, partial product generation units corresponding to × 1 and × 16 are required, but none of the partial product generation units has both calculation functions. Therefore, the partial product generation unit selection unit 102 uses the BTD / multiplication unit 164 of the partial product generation unit 160 as the partial product generation unit corresponding to x1, and the partial product generation unit as the partial product generation unit corresponding to x16. 130 BTD / multipliers 132 (see A2 in FIG. 11) are used.

  Thus, the filter coefficient is input by selecting one or more partial product generation units suitable for multiplying the input data and the filter coefficient, and the input data corresponding to the filter coefficient is input to the partial product generation unit. By causing the selection unit 102 to input the partial product generation unit, it is possible to perform an operation that exceeds the operation function of the partial product generation unit, and to minimize the number of partial product generation units.

  In the present embodiment, a case has been described in which an operation can be performed by using a partial product generation unit that is not used. However, as described above, the partial product in which the generated code data is “0”. It is also possible to perform calculation using the generation unit. In the present embodiment, the case where the partial product generation unit selection unit 102 that appropriately selects input data and inputs the input data to the partial product generation unit has been described. However, the partial product generation unit similarly applies to the filter coefficient. A selection unit may be provided and input to the selected partial product generation unit.

  In any case, in the filter operation, when one partial product generation unit cannot generate a part of a partial product to be generated from one set data, one set data is generated using two or more partial product generation units. Is calculated. In this case, a partial product generation unit in which the generated partial product is “0” or a partial product generation unit including an inactive (unused) partial product generation unit that is not used in the filter operation is selected and cannot be generated. To generate a partial product. This makes it possible to effectively use a partial product generation unit having a partial product of “0” or an inactive partial product generation unit, and to minimize the number of partial product generation units.

  For example, in the example of FIG. 11, the partial product generation unit 140 needs to include four partial product generation units of × 1, × 4, × 16, and × 64 in order to calculate the filter coefficient “53”. However, when the partial product generation unit corresponding to the × 1 is omitted and the operation of “53” is performed, two partial products of the partial product generation unit 140 and the unused partial product generation unit 110 at this time are used. Let the generation unit perform the operation. That is, the partial product generation unit 110 is a substitute for the partial product generation unit that the partial product generation unit 140 lacks. In the example of FIG. 11, the partial product to be generated from the set data composed of the filter operation “53” and the corresponding input data cannot be generated by any partial product generation unit. If a product generation unit is used, an operation can be performed. As described above, the filter calculator 100 includes the partial product generation unit selection unit 102 that selects one or more partial product generation units for calculating the set data in accordance with the set data. Even if it does not have a corresponding partial product generation unit that can calculate them, the combination data can be operated by a combination of partial product generation units or partial product generation units constituting the partial product generation unit. The number of generation units can be reduced.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, although the present embodiment has been described as an image decoding device, it can also be used as a motion compensation unit in image encoding. Further, by applying the present invention not only to the filter operation exemplified above but also to a multiplier to which a predetermined multiplier is input, redundant circuits can be reduced and hardware can be reduced.

  In the present embodiment, the multiplier (filter arithmetic unit) to which the second-order Booth algorithm is applied has been described. However, the present invention is not limited to this. That is, even a third-order or higher-order booth algorithm can be similarly applied.

FIG. 3 is a block diagram illustrating a multiplier that performs multiplication according to a second order Booth algorithm. (A) is a figure explaining the bit used for code | cord | chord data generation by Booth's algorithm, (b) is a figure which shows the detail of the partial product production | generation unit of the multiplier shown in FIG. It is a figure which shows a filter coefficient and its code | symbol data. It is a figure which shows the normal filter arithmetic unit which combined the multiplier shown in FIG. 2 in order to perform the said filter calculation. It is a figure which shows each code | symbol data in filter calculation # 1 and # 2. It is a figure which shows the filter computing unit concerning this Embodiment. It is a block diagram which shows the decoding apparatus which decodes the compressed image encoded based on H.264. It is a block diagram which shows the decoding apparatus which decodes the compressed image encoded based on VC-1. It is a block diagram which shows the motion compensation part which performs the motion compensation process concerning embodiment of this invention. It is a block diagram which shows the specific example of the filter arithmetic unit concerning embodiment of this invention. It is a figure which shows the value of the filter coefficient and code | symbol data input into the same filter arithmetic unit. 10 is a block diagram showing a cumulative addition filter (digital filter) in the image processing apparatus described in Patent Document 1. FIG.

Explanation of symbols

1, 1c, 1d, 100 Filter operation unit 2, 103, 502 Coefficient data memory 3, 4, 110, 120, 130, 140, 150, 160, 401, 510, 520, 530 Partial product generation units 5-8, 154 157, 160, 161, 505 Selector 10, 104, 153, 155, 158, 175, 450, 540 Adders 31-33, 41-43, 410, 420, 430, 511-513, 521-523, 531 533 Partial product generation unit 102 Partial product generation unit selection unit 114, 123, 124, 132, 133, 141, 142, 143, 153, 154, 164 BTD / multiplication unit 150 Motion compensation unit 151 Selector 152, 159 Multiplier 156 Line Memory 160 Partial product generation unit 170 Image decoding device 171 Compressed data 172 Variable length decoding unit 173 Inverse quantization unit 174 Inverse Hadamard transform unit 176 Deblocking filter 177 Switching unit 178 Decoded image 179 Monitor 180 In-screen prediction unit 181 Weighted prediction unit 182 Compensation unit 183 Predicted image 190 Image decoding device 192 Variable length decoding unit 193 Inverse quantization unit 194 Conversion unit 195 Adder 196 Loop filter 197 Decoded image 198 Monitor 199 Prediction unit 200 Compensation unit 400, 501 Multiplier 411, 421, 431, 441 Booth decoder 412, 422, 432, 442 Multiplication unit 413, 423, 433, 443 Bit shift units 454, 542 Register 500 Filter calculator 503 Counter 506 Cumulative addition memory 541 Full adder 544 Half adder

Claims (17)

For a plurality of filters, a filter processing device that performs a sum of products operation using a Booth algorithm with a plurality of input data and a plurality of filter coefficients constituting the filter,
A plurality of partial product generation units that receive one or more set data including the input data and filter coefficients associated with the input data, and generate one or more partial products;
An adding unit for generating a sum of partial products generated by the plurality of partial product generating units;
A filter processing apparatus comprising: a partial product generation unit selection unit that selects one or more of the plurality of partial product generation units and inputs the set data according to the set data. The partial product generation unit selection unit generates one partial product generation unit and another partial product generation when a partial product to be generated from the one set data cannot be generated by one partial product generation unit. The filter processing apparatus according to claim 1, wherein the set data is input to the unit to generate a partial product. The filter processing apparatus according to claim 1, wherein the number of the partial product generation units is smaller than a maximum number of filter coefficients constituting the plurality of filters. 4. The filter processing device according to claim 1, wherein at least one of the plurality of partial product generation units has a different computing ability from the others. 5. The filter processing apparatus according to claim 4, wherein the plurality of partial product generation units include a largest partial product that can be generated and having a different number of digits. The filter processing apparatus according to claim 4, wherein the plurality of partial product generation units include ones having different numbers of partial products that can be generated. The filter processing apparatus according to claim 1, wherein the partial product generation unit includes a plurality of partial product generation units corresponding to i of 2 ²ⁱ (i ≧ 0). The partial product generation unit selection unit generates one partial product generation unit and another partial product generation when a partial product to be generated from the one set data cannot be generated by one partial product generation unit. A substitute partial product generation unit included in a unit is selected, and the set data is input to generate a partial product,
8. The substitute partial product generation unit is one in which code data decoded according to Booth's algorithm from a predetermined bit of a filter coefficient input to the other partial product generation unit becomes zero. Filter processing device. The partial product generation unit selection unit generates one partial product generation unit and another partial product generation when a partial product to be generated from the one set data cannot be generated by one partial product generation unit. The filter processing apparatus according to claim 7, wherein an unused partial product generation unit included in the unit is selected, and the set data is input to generate a partial product. A booth decoder for obtaining code data decoded in accordance with Booth's algorithm from a predetermined bit of the filter coefficient, at least part of the plurality of partial product generators corresponding to i of 2 ²ⁱ (i ≧ 0); 10. The multiplier according to claim 7, further comprising: a multiplier that obtains a product of the Booth decoder and the input data; and a bit shift unit that shifts a selection result of the multiplier by a predetermined bit according to the i. The filter processing apparatus of Claim 1. The partial product generation unit includes only a bit shift unit that bit-shifts the input data when the code data decoded according to Booth's algorithm is 1 for the predetermined bit of the associated filter coefficient. The filter processing device according to claim 7, wherein the filter processing device is a filter processing device. The partial product generation unit obtains code data decoded according to the Booth algorithm from the predetermined bits of the filter coefficient when the code data decoded according to the Booth algorithm is 0 for the predetermined bit of the associated filter coefficient The filter processing apparatus according to claim 7, comprising only a booth decoder. The partial partial product generation unit is characterized in that one or more of code data decoded in accordance with Booth's algorithm is either −2, −1, or −1 for predetermined bits of associated filter coefficients. Item 11. The filter processing device according to any one of Items 7 to 10. One of the filters is a 6-tap filter,
H. The filter processing device according to any one of claims 1 to 13, wherein a filter operation in motion compensation processing and / or intra-screen prediction processing compliant with H.264 is executed. One of the filters is a 6-tap filter,
H. H.264 or H.264 The filter processing device according to any one of claims 1 to 13, wherein the filter processing device executes a filter operation in a motion compensation process based on H.264 and VC-1. A multiplier applying a booth algorithm that performs multiplication of multiple types of multiplier groups and multiplicand groups,
A plurality of partial product generation units that receive the set data including the multiplicand and a multiplier associated with the multiplicand and generate one or more partial products;
An adding unit for generating a sum of partial products generated by the plurality of partial product generating units;
A multiplier having a partial product generation unit selection unit that selects one or more of the plurality of partial product generation units according to the set data and inputs the set data. A motion compensation processing device for generating a predicted image,
A first filter operation unit that performs a filter operation on vertical input data;
A second filter operation unit that performs a filter operation according to horizontal input data;
A weighting calculation unit that performs weighting on calculation results of the first and second filter calculation units or input data input to the first and second filter calculations;
The first and second filter operation units are filter operation units that perform a product-sum operation on a plurality of filters using a Booth algorithm with each of the plurality of input data and a plurality of filter coefficients constituting the filter,
A plurality of partial product generation units that receive one or more set data including the input data and filter coefficients associated with the input data, and generate one or more partial products;
An adding unit for generating a sum of partial products generated by the plurality of partial product generating units;
A motion compensation processing device comprising: a partial product generation unit selection unit that selects one or more of the plurality of partial product generation units according to the set data and inputs the set data.

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