JP4952260B2 - Memory test equipment - Google Patents

Description

  The present invention relates to a memory test apparatus for testing a memory under test that is accessed using packetized addresses and transfers data as packets.

  In recent years, in order to improve the transfer rate of data and the like, a memory that is accessed using a packetized address and transfers data as a packet has been developed. One typical example of this memory is Direct RDRAM (Direct Rambus Dynamic Random Access Memory) (RDRAM is a registered trademark of Rambus, USA). This Direct RDRAM has a narrow bus width of 8 bits but an operating frequency as high as about 800 MHz, and realizes a maximum transfer speed of about 1.6 Gbps. With the advent of such a memory, a memory test apparatus that enables the test has been developed.

  FIG. 3 is a block diagram showing a main configuration of a conventional memory test apparatus. As shown in FIG. 3, a conventional memory test apparatus 100 includes a sequence control circuit 101, an instruction memory 102, an address generation circuit 103, a data generation circuit 104, a control signal generation circuit 105, selection units 106a to 106n, a waveform shaping circuit 107, And an expected value determination circuit 108, and a test is performed on the memory under test 120 that is accessed using a packetized address and transfers data as a packet.

  The sequence control circuit 101 outputs a program counter signal PC10 for controlling a test pattern generation sequence used for testing the memory under test 120 in accordance with a sequence control command described in a test program created by a user. The instruction memory 102 stores various instructions such as pattern generation instructions described in the test program. When the program counter signal PC10 is output from the sequence control circuit 101, the instruction memory 102 is designated by the program counter signal PC10. The instruction stored at the address to be read is output.

  The instructions stored in the instruction memory 102 include an address pattern generation instruction, a data pattern generation instruction, a control signal generation instruction, and a pin selection instruction. Here, the address pattern generation instruction is an instruction for generating an address pattern used for the test of the memory under test 120, and the data pattern generation instruction is an instruction for generating a data pattern used for the test of the memory under test 120. These instructions are a kind of pattern generation instructions.

  The control signal generation command is a command for generating various control signals (chip selection signal, write control signal, read control signal, etc.) used for testing the memory under test 120. The pin selection command is a command for selecting a predetermined pin from a plurality of pins (address pin, data pin, and control pin) provided in the memory under test 120. The address pattern generation command, data pattern generation command, control signal generation command, and pin selection command read from the instruction memory 102 are an address pattern generation command signal PG11, a data pattern generation command signal PG12, a control signal generation command signal PG13, And a pin selection command signal PG14.

  The address generation circuit 103 performs a predetermined operation according to the address pattern generation command signal PG11 output from the instruction memory 102 and outputs an address signal A11 to be given to the memory under test 120. The address signal A11 is a 48-bit signal, for example. The data generation circuit 104 performs a predetermined operation according to the data pattern generation command signal PG12 output from the instruction memory 102 and outputs a data signal D11 to be given to the memory under test 120. The data signal D11 is a 32-bit signal, for example. The control signal generation circuit 105 outputs a control signal C11 to be given to the memory under test 120 in accordance with the control signal generation command signal PG13 output from the instruction memory 102.

  The selectors 106a to 106n are provided for each of a plurality of pins included in the memory under test 120, and each of the address signal A11 has one bit, the data signal D11 has one bit, the control signal C11 has one bit, and a fixed logic level. One of the H (high) level signal and the L (low) level signal is selected in real time to packetize the test signal applied to the memory under test 120. The signals (bits) selected by the selection units 106a to 106n are not fixed in advance, and dynamically change for each selection unit 106a to 106n during the test of the memory under test 120.

  The selection units 106 a to 106 n include a pin output selection circuit 111 and a pin output selection memory 112. The pin output selection circuit 111 has the address signal A11, the data signal D11, and the control signal C11 as inputs. Based on the selection signal stored in the pin output selection memory 112, any one of these signals is output. One bit of the signal or a fixed logic level H level or L level is selected and output. The pin output selection memory 112 is a memory that stores in advance a selection signal for specifying a bit to be selected by the pin output selection circuit 111, and is stored at an address specified by the pin selection command signal PG14 output from the instruction memory 102. The selected signal is read and output to the pin output selection circuit 111.

  The waveform shaping circuit 107 shapes the waveform of the packetized test signal output from each of the pin output selection circuits 111 provided in the selection units 106 a to 106 n at a timing specified by the test program and applies the signal to the memory under test 120. Circuit. The expected value determination circuit 108 uses the packetized test signal output from each pin output selection circuit 111 included in the selection units 106 a to 106 n as an expected value, and uses the expected value and the signal output from the memory under test 120. It is a circuit that determines pass / fail by comparison.

  Next, the operation of the memory test apparatus 100 shown in FIG. 3 will be described. FIG. 4 is a timing chart showing an example of a test signal generated by the conventional memory test apparatus 100. When the test is started, various instructions such as a pattern generation instruction described in the test program are stored in the instruction memory 102 and a selection signal is stored in the pin output selection memory 112. When the above processing is completed, the sequence control circuit 101 executes the sequence control instruction described in the test program in synchronization with the reference clock CLK shown in FIG. 4 and outputs the program counter signal PC10.

  The instruction memory 102 reads out various instructions stored at the address indicated by the program counter signal PC10 in synchronization with the reference clock CLK. Thereby, the instruction memory 102 outputs an address pattern generation command signal PG11, a data pattern generation command signal PG12, and a control signal generation command signal PG13, which are generated by the address generation circuit 103, the data generation circuit 104, and the control signal generation. Each is input to the circuit 105. The instruction memory 102 also outputs a pin selection command signal PG14 together with the various signals described above, and this is input to the pin output selection memory 112 provided in each of the selection units 106a to 106n.

  In the address generation circuit 103, the address signal A11 shown in FIG. 4 is generated in accordance with the address pattern generation command signal PG11 from the instruction memory 102. Further, in data generation circuit 104, data signal D11 shown in FIG. 4 is generated in accordance with data pattern generation command signal PG12, and in control signal generation circuit 105, control signal C11 shown in FIG. 4 is generated in accordance with control signal generation command signal PG13. Generated. Here, as shown in FIG. 4, the address signal A11, the data signal D11, and the control signal C11 are signals that maintain the same value over a plurality of cycles (eight cycles in the example shown in FIG. 4) of the reference clock CLK. It is.

  The generated address signal A11, data signal D11, and control signal C11 are input to each of the selection units 106a to 106n. In each of the selection units 106a to 106n, one bit of any one of these signals. Or a fixed logic level, H level or L level, is selected. At this time, the pin output selection circuit 111 provided in each of the selection units 106a to 106n is based on the selection signal stored in the address (address of the pin output selection memory 112) specified by the pin selection command signal PG14. A signal (bit) or the like is selected for each reference clock CLK. Thereby, a packetized test signal is generated.

  When the memory under test 120 is a Direct RDRAM, a test signal shown in FIG. 4 is generated. In FIG. 4, “ROW” and “COL” indicate a row address and a column address of an address signal which is a kind of test signal, and “DQ” indicates a data signal which is a kind of test signal. CFM (Clock From Master: data reception clock) represents a data reception clock of the memory under test 120. Also, “ACT” in the figure indicates a command packet that activates the memory under test 120 by designating a row address, and “RD” in the figure designates a column address to execute reading. Indicates a command packet. Further, “PRE” in the drawing indicates a command packet for executing precharge, and “Q” in the drawing indicates a data packet.

  Here, as shown in FIG. 4, the row address “ROW” consists of 3 bits of “ROW0”, “ROW1”, and “ROW2”, and the “ACT” command packet is a packet in which the address signal A11 and the control signal C11 are mixed. is there. Now, as shown in FIG. 4, it is assumed that a plurality of bits of “Aa” address signal A11 is generated by the address generation circuit 103, and a plurality of bits of “RBa” control signal C11 is generated by the control signal generation circuit 105. . When the address signal A11 and the control signal C11 are selected by the selection units 106a to 106n, the 0th to 12th bits (“A0” to “A12”) of the address signal A11 and the 0th to 0th bits of the control signal C11 are selected. An “ACT” command packet in which 12 bits (“RB0” to “RB12”) are arranged as illustrated is generated. Other command packets are generated in the same manner.

  The packetized test signal is subjected to waveform shaping at a timing designated by the test program in the waveform shaping circuit 107 and applied to the memory under test 120. In this manner, the test signal is applied to the memory under test 120, and the data signal is written and read. The signal read from the memory under test 120 is compared with the expected value in the expected value determination circuit 108 to determine pass / fail.

For a conventional memory test apparatus for testing a memory that is accessed using packetized addresses and transfers data as packets, see, for example, Non-Patent Document 1 below.
Tadashi Kawarazaki, “Development of ALPG for high-speed memory”, ANDO Technical Report Vol. 69, Ando Electric Co., Ltd., April 20, 2000, p. 74-78

  Incidentally, in the conventional memory test apparatus 100 shown in FIG. 3, the sequence control circuit 101, the instruction memory 102, the address generation circuit 103, and the data generation circuit 104 are provided so that at least the maximum data transfer speed of the memory under test 120 can be secured. And the control signal generation circuit 105 must be operated at high speed. For example, as described above, the maximum transfer rate of the Direct RDRAM is about 1.6 Gbps. However, it is necessary to operate each of the above circuits at an operation speed that can secure this maximum transfer rate.

  In recent years, the memory has been increased in speed, and it is expected that the memory will be further increased in the memory that is accessed using the packetized address and transfers the data as a packet. In order to test such a memory capable of high-speed operation, each of the above circuits needs to be operated at a high speed as the maximum transfer speed of the memory under test is improved. Then, an expensive device must be used, and there is a problem that the cost of the memory test apparatus increases dramatically.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a memory test apparatus capable of performing a high-speed memory test while suppressing an increase in cost.

In order to solve the above problems, a memory test apparatus according to the present invention is a memory test apparatus (1) for testing a memory under test (40) which is accessed using packetized addresses and transfers data as packets. A test pattern generator (11-15) for generating at least an address composed of a plurality of bits for accessing the memory under test as a test pattern used for testing the memory under test; and for each pin of the memory under test A plurality of output selection units (31a to 31k) that select each of the bits of the test pattern according to a predetermined rule, and a first storage unit (19) that stores in advance the effective number of bits selected by the output selection unit A second storage unit (33) for temporarily storing bits selected by each of the selection units, and the second storage unit stored in the second storage unit A selection unit (34) for packetizing the test pattern by sequentially selecting the effective number stored in the first storage unit according to a predetermined rule, and the storage unit stored in the first storage unit A control unit (23) for controlling the operation of the test pattern generation unit, the output selection unit, and the second storage unit is provided according to the effective number.
According to the present invention, the test pattern output from the test pattern generator is input to each of a plurality of output selectors provided for each pin of the memory under test, and the bit is selected according to a predetermined rule, and the second is selected. It is temporarily stored in the storage unit. Then, the test pattern is packetized by sequentially selecting the bits temporarily stored by the selection unit according to a predetermined rule. The operations of the test pattern generation unit, the output selection unit, and the second storage unit are controlled by the control unit according to the effective number (the effective number of bits selected by the output selection unit) stored in the first storage unit. . Specifically, it is controlled to operate in synchronization with a signal obtained by thinning out the reference clock by an effective number.
Further, in the memory test apparatus of the present invention, the test pattern generator generates an address for generating an address for accessing the memory under test, and data for generating data to be transferred to the memory under test A generation circuit (14) and a control signal generation circuit (15) for generating a control signal for controlling the operation of the memory under test are provided.
In addition, the memory test apparatus of the present invention includes a counter (20) that counts the effective number stored in the first storage unit in synchronization with a reference clock that defines the operation of the memory test apparatus; An end detection circuit (22) for detecting the end, and when the end detection circuit detects the end of counting of the counter, the control unit includes the test pattern generation unit, the output selection unit, and Control for operating the second storage unit is performed.
The memory test apparatus of the present invention further includes a selection control circuit (21) for outputting a selection signal corresponding to the count value of the counter, and the selection unit outputs the selection signal output from the selection control circuit. Based on the above, the selection of the bit stored in the second storage unit is performed.
In addition, the memory test apparatus of the present invention includes a third storage unit (32a to 32k) that is provided corresponding to each of the output selection units and stores in advance a selection signal that defines a selection rule for each of the output selection units. It is characterized by providing.

  According to the present invention, the operations of the test pattern generation unit, the output selection unit, and the second storage unit depend on the effective number (the effective number of bits selected by the output selection unit) stored in the first storage unit. Since it is controlled by the control unit, there is no need for an expensive device for high-speed operation, and there is an effect that a high-speed memory test can be performed while suppressing an increase in cost.

  Hereinafter, a memory test apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a memory test apparatus according to an embodiment of the present invention. As shown in FIG. 1, the memory test apparatus 1 of this embodiment includes a sequence control circuit 11, an instruction memory 12, an address generation circuit 13, a data generation circuit 14, a control signal generation circuit 15 (hereinafter referred to as a test pattern generation unit), a selection. Units 16a to 16n, waveform shaping circuit 17, expected value determination circuit 18, cycle number memory 19 (first storage unit), counter 20, selection control circuit 21, end detection circuit 22, and clock enable control circuit 23 (control unit) And testing the memory under test 40 that is accessed using a packetized address and transfers data as a packet.

  The sequence control circuit 11 outputs a program counter signal PC for controlling a test pattern generation sequence used for testing the memory under test 40 in accordance with a sequence control instruction described in a test program created by a user. The instruction memory 12 stores various instructions such as a pattern generation instruction described in the test program. When the program counter signal PC is output from the sequence control circuit 11, the instruction memory 12 is designated by the program counter signal PC. The instruction stored at the address to be read is output.

  The instructions stored in the instruction memory 12 include an address pattern generation instruction, a data pattern generation instruction, a control signal generation instruction, and a pin selection instruction. Here, the address pattern generation instruction is an instruction for generating an address pattern used for the test of the memory under test 40, and the data pattern generation instruction is an instruction for generating a data pattern used for the test of the memory under test 40. These instructions are a kind of pattern generation instructions.

  The control signal generation command is a command for generating various control signals (chip selection signal, write control signal, read control signal, etc.) used for testing the memory under test 40. The pin selection command is a command for selecting a predetermined pin from a plurality of pins (address pin, data pin, and control pin) provided in the memory under test 40. An address pattern generation instruction, a data pattern generation instruction, a control signal generation instruction, and a pin selection instruction read from the instruction memory 12 are an address pattern generation instruction signal PG1, a data pattern generation instruction signal PG2, a control signal generation instruction signal PG3, And a pin selection command signal PG4.

  The address generation circuit 13 performs a predetermined operation according to the address pattern generation command signal PG1 output from the instruction memory 12 and outputs an address signal A1 to be given to the memory under test 40. The address signal A1 is a 48-bit signal, for example. The data generation circuit 14 performs a predetermined operation according to the data pattern generation command signal PG2 output from the instruction memory 12, and outputs a data signal D1 to be given to the memory under test 40. The data signal D1 is a 32-bit signal, for example. The control signal generation circuit 15 outputs a control signal C1 to be given to the memory under test 40 in accordance with the control signal generation command signal PG3 output from the instruction memory 12.

  The selectors 16a to 16n are provided for each of a plurality of pins included in the memory under test 40, and each of the address signal A1 has one bit, the data signal D1 has one bit, the control signal C1 has one bit, and a fixed logic level. One of the H (high) level signal and the L (low) level signal is selected in real time to packetize the test signal applied to the memory under test 40. The signals (bits) selected by the selectors 16a to 16n are not fixed in advance and change dynamically for each of the selectors 16a to 16n during the test of the memory under test 40.

  The selection units 16a to 16n include a plurality of pin output selection circuits 31a to 31k (output selection unit), a plurality of pin output selection memories 32a to 32k (third storage unit), and a FIFO (First-In First-Out). A memory 33 (second storage unit) and a selection circuit 34 (selection unit) are provided. Each of the pin output selection circuits 31a to 31k receives the address signal A1, the data signal D1, and the control signal C1 as input, and these signals are based on the selection signals stored in the pin output selection memories 32a to 32k. 1 bit of any of the signals, or H level or L level which is a fixed logic level is selected and output.

  The pin output selection memories 32a to 32k are provided corresponding to the pin output selection circuits 31a to 31k, respectively, and store in advance a selection signal for designating a bit to be selected by the pin output selection circuits 31a to 31k. The pin output selection memories 32a to 32k read the selection signal stored at the address specified by the pin selection command signal PG4 output from the instruction memory 12 and output it to the pin output selection circuits 31a to 31k. The number of pin output selection circuits 31a to 31k and the pin output selection memories 32a to 32k is about twice the maximum packet length (maximum number of cycles) given to the memory under test 40.

  The FIFO memory 33 is a memory that temporarily stores a bit or a logic level selected by each of the pin output selection circuits 31a to 31k. In addition, the number of cycles output from the cycle number memory 19 (the effective number of bits selected by the pin output selection circuits 31a to 31k) CY is also temporarily stored. The selection circuit 34 packetizes the test pattern by selecting bits or the like temporarily stored in the FIFO memory 33 in real time based on the selection signal S1 output from the selection control circuit 21. The packetized test pattern is output as a test signal E1.

  The waveform shaping circuit 17 is a circuit that shapes the waveform of the packetized test signal E1 output from each selection circuit 34 included in the selection units 16a to 16n at a timing specified by the test program and applies the signal to the memory under test 40. It is. The expected value determination circuit 18 uses the packetized test signal E1 output from each selection circuit 34 included in the selection units 16a to 16n as an expected value, and compares this expected value with the signal output from the memory under test 40. This is a circuit for determining pass / fail.

  The cycle number memory 19 is a memory that stores in advance a cycle number that is an effective number of bits selected by the pin output selection circuits 31a to 31k. The cycle number memory 19 reads the cycle number CY stored at the address specified by the pin selection command signal PG 4 output from the instruction memory 12 and outputs it to the FIFO memory 33. The number of cycles stored in the cycle number memory 19 is specified in the test program.

  The counter 20 reads the number of cycles CY temporarily stored in the FIFO memory 33, and counts (counts) this cycle number as an initial value. Specifically, the count value CT is output while counting down in synchronization with a reference clock that defines the operation of the memory test apparatus 1 with the number of cycles as an initial value. The selection control circuit 21 outputs a selection signal S1 corresponding to the count value CT output from the counter 20. Specifically, when the count value CT output from the counter 20 is the initial value of the number of cycles, the value “0” is output as the initial value, and the value is incremented by “1” each time the counter 20 counts down. An increasing (incrementing) selection signal S1 is output. The end detection circuit 22 is a circuit that detects the count end of the counter 20. Specifically, when the count value CT of the counter 20 becomes “1”, an end detection signal DT indicating that the count has ended is output.

  The clock enable control circuit 23 corresponds to the cycle number CY stored in the cycle number memory 19, and includes a test pattern generation unit including the sequence control circuit 11 to the control signal generation circuit 15, pin output selection circuits 31a to 31k, and pin output selection. The write operations of the memories 31a to 32k and the FIFO memory 33 are controlled. Specifically, when the detection signal DT is output from the end detection circuit 22, the reference for the test pattern generation unit, the pin output selection circuits 31 a to 31 k, the pin output selection memories 31 a to 32 k, and the FIFO memory 33. A clock enable signal CE for enabling the clock is output. That is, the clock enable control circuit 23 performs control to thin out the reference clock according to the cycle number CY stored in the cycle number memory 19. Thereby, the operating frequency of each said structure can be suppressed.

  Next, the operation of the memory test apparatus 1 shown in FIG. 1 will be described. FIG. 2 is a timing chart showing an example of a test signal generated by the memory test apparatus 1 according to an embodiment of the present invention. When the test is started, various instructions such as a pattern generation instruction described in the test program are stored in the instruction memory 12, and selection signals are stored in the pin output selection memories 32a to 32k. In addition, the cycle number specified in the test program is stored in the cycle number memory 19.

  When the above processing is completed, a clock enable signal CE is output from the clock enable control circuit 23, whereby a test pattern generation unit including the sequence control circuit to the control signal generation circuit 15, pin output selection circuits 31a to 31k, and pin output selection The operations of the memories 31a to 32k and the FIFO memory 33 are started. The sequence control circuit 11 executes a sequence control instruction described in the test program in synchronization with the clock enable signal CE and outputs a program counter signal PC.

  The instruction memory 12 reads various instructions stored at the address indicated by the program counter signal PC in synchronization with the clock enable signal CE. Thereby, the instruction memory 12 outputs an address pattern generation command signal PG1, a data pattern generation command signal PG2, and a control signal generation command signal PG3, which are generated by the address generation circuit 13, the data generation circuit 14, and the control signal generation. Each is input to the circuit 15. The instruction memory 12 also outputs a pin selection command signal PG4 together with the above-described various signals, which are input to the pin output selection memories 32a to 32k and the cycle number memory 19 provided in each of the selection units 16a to 16n. .

  In the address generation circuit 13, the address signal A1 shown in FIG. 2 is generated in accordance with the address pattern generation command signal PG1 from the instruction memory 12. Further, in data generation circuit 14, data signal D1 shown in FIG. 2 is generated in accordance with data pattern generation command signal PG2, and in control signal generation circuit 15, control signal C1 shown in FIG. 2 is generated in accordance with control signal generation command signal PG3. Generated. Here, the address signal A1, the data signal D1, and the control signal C1 are signals that maintain the same value over the period of the clock enable signal CE, as shown in FIG.

  The generated address signal A1, data signal D1, and control signal C1 are input to each of the pin output selection circuits 31a to 31k provided in each of the selection units 16a to 16n. The pin output selection circuits 31a to 31k are any one of the input signals based on the selection signal stored at the address specified by the pin selection command signal PG4 of the corresponding pin output selection memory 32a to 32k. One bit of the signal, or H level or L level, which is a fixed logic level, is selected and output. For example, in the example shown in FIG. 2, the pin output selection circuit 31a selects the fifth bit (“RB5”) of the control signal C1, and the pin output selection circuit 31c selects the ninth bit (“A9”) of the address signal A1. Is selected, and the pin output selection circuit 31j selects the L level ("LOW").

  In this manner, in each of the pin output selection circuits 31a to 31k provided in the selection units 16a to 16n, one bit of the input signal or a fixed logic level of H level or L level is selected, and the selection unit A FIFO memory 33 provided in each of 16a to 16n temporarily stores a signal composed of a plurality of bits. Note that the number of bits of the signal input from the pin output selection circuits 31a to 31k to the FIFO memory 33 is not fixed, but varies according to the length of the packet (number of cycles) given to the memory under test 40. As shown in FIG. 2, the signal input to the FIFO memory 33 is a signal that maintains the same value over the period of the clock enable signal CE.

  When the pin selection command signal PG4 output from the instruction memory 12 is input to the cycle number memory 19, the cycle number CY stored at the address specified by the pin selection command signal PG4 is read and the FIFO is read out. It is temporarily stored in the memory 33. Here, the case where the value of the cycle number CY read from the cycle number memory 19 is “18” as shown in FIG. 2 will be described as an example. The value of the cycle number CY being “18” means that the period T1 (see FIG. 2) of the clock enable signal CE is 18 periods of the reference clock.

  Note that there is actually a difference between the timing at which the bits selected by the pin output selection circuits 31 a to 31 k are input to the FIFO memory 33 and the timing at which the cycle number CY is input to the FIFO memory 33. In FIG. 2, for the sake of simplicity of illustration, the timing deviation is not considered.

  When the cycle number CY is stored in the FIFO memory 33, the counter 20 reads the cycle number CY, sets it to an initial value, and starts counting down in synchronization with the reference clock. The selection control circuit 21 outputs a selection signal S1 corresponding to the count value CT of the counter 20. Specifically, as shown in FIG. 2, when the count value CT output from the counter 20 is the initial value (“18”) of the number of cycles, the value “0” is output as the initial value, and the counter 20 Each time the countdown is performed, a selection signal S1 whose value increases (increments) by "1" is output.

  The selection circuit 34 packetizes the test pattern by selecting bits or the like temporarily stored in the FIFO memory 33 in real time based on the selection signal S1 output from the selection control circuit 21. In the example shown in FIG. 2, based on the selection signal S1, the bit selected by the pin output selection circuit 31a (“RB5”), the bit selected by the pin output selection circuit 31b (“RB2”), and the pin output selection circuit The bit selected in 31c (“A9”),... Is selected in the order of pin output selection circuit 31a to pin output selection circuit 31k.

  Here, when the test signal E1 output from the selection circuit 34 and the row address “ROW2” shown in FIG. 4 are compared, the arrangement of bits is the same, and “necessary for testing the memory under test 40” is shown. It can be seen that the “ACT” command packet has been generated. Although the illustration is simplified in FIG. 2, other bits “ROW0”, “ROW1”, column addresses, and the like of the other row addresses shown in FIG. 4 are similarly generated.

  When the count value CT of the counter 20 becomes “1”, the end of the counter 20 is detected by the end detection circuit 22, and the end detection circuit 22 outputs a detection signal DT. When this detection signal DT is input to the clock enable control circuit 23, a clock enable signal CE is output from the clock enable control circuit 23, so that a new test pattern generator comprising the sequence control circuit to the control signal generation circuit 15 generates a new one. A test pattern is output (see period T2 in FIG. 2). In this way, packetized test signals are sequentially generated.

  The packetized test signal is waveform-shaped at a timing specified by the test program in the waveform shaping circuit 17 and applied to the memory under test 40. In this way, the test signal is applied to the memory under test 40, and the data signal is written and read. The signal read from the memory under test 40 is compared with the expected value in the expected value determination circuit 18 to determine pass / fail.

  The memory test apparatus 1 of the present embodiment described above is synchronized with the clock enable signal obtained by thinning the reference clock by the number of cycles that is the effective number of bits selected by the pin output selection circuits 31a to 31k, The write operation of the test pattern generation unit including the control signal generation circuit 15, the pin output selection circuits 31a to 31k, the pin output selection memories 31a to 32k, and the FIFO memory 33 is controlled. Here, the maximum operation speed when the reference clock is thinned out is the minimum packet generation time of the memory under test 40. For example, when testing the memory under test 40, which requires time for eight cycles of the reference clock in order to generate the minimum packet, the above circuits are operated at an operating speed of 1/8 of the reference clock. If you let it. For this reason, an expensive device for high-speed operation is not required, and a high-speed memory test can be performed while suppressing an increase in cost.

  The memory test apparatus according to the embodiment of the present invention has been described above, but the present invention is not limited to the above-described embodiment, and can be freely changed within the scope of the present invention. For example, in the above-described embodiment, the configuration in which each of the selection units 16a to 16n includes the FIFO memory 33 has been described as an example. However, the FIFO memory 33 is not necessarily provided in all of the selection units 16a to 16n. The configuration may be such that one FIFO memory used in each of the units 16a to 16n is provided. In the above embodiment, the counter 20 counts down using the cycle number CY as an initial value. However, the counter 20 may count up from the value “1” to the cycle number CY. In addition, the 1st memory | storage part and the 3rd memory | storage part are not restricted to two independent memory | storage parts, The structure which shares one memory | storage part may be sufficient.

It is a block diagram which shows the principal part structure of the memory test apparatus by one Embodiment of this invention. It is a timing chart which shows an example of the test signal produced | generated with the memory test apparatus 1 by one Embodiment of this invention. It is a block diagram which shows the principal part structure of the conventional memory test apparatus. 6 is a timing chart showing an example of a test signal generated by a conventional memory test apparatus 100.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory test apparatus 11 Sequence control circuit 12 Instruction memory 13 Address generation circuit 14 Data generation circuit 15 Control signal generation circuit 19 Cycle number memory 20 Counter 21 Selection control circuit 22 Completion detection circuit 23 Clock enable control circuit 31a-31k Pin output selection circuit 32a to 32k pin output selection memory 33 FIFO memory 34 selection circuit 40 memory under test

Claims (5)

In a memory test apparatus for testing a memory under test that is accessed using a packetized address and transfers data as a packet,
A test pattern generating section for generating an address composed of a plurality of bits for accessing the memory under test as a test pattern used for testing the memory under test;
A plurality of output selection units provided for each pin of the memory under test, each of which selects a bit of the test pattern according to a predetermined rule;
A first storage unit that stores in advance the effective number of bits selected by the output selection unit;
A second storage unit that temporarily stores bits selected by each of the selection units;
A selection unit that packetizes the test pattern by sequentially selecting the bits stored in the second storage unit according to a predetermined rule by the effective number stored in the first storage unit;
A memory test comprising: a control unit that controls operations of the test pattern generation unit, the output selection unit, and the second storage unit according to the effective number stored in the first storage unit. apparatus. The test pattern generation unit includes an address generation circuit for generating an address for accessing the memory under test;
A data generation circuit for generating data to be transferred to the memory under test;
The memory test apparatus according to claim 1, further comprising: a control signal generation circuit that generates a control signal for controlling an operation of the memory under test. A counter that counts the effective number stored in the first storage unit in synchronization with a reference clock that defines the operation of the memory test device;
An end detection circuit for detecting the end of counting of the counter,
The control unit performs control to operate the test pattern generation unit, the output selection unit, and the second storage unit when the end detection circuit detects the count end of the counter. The memory test apparatus according to claim 1. A selection control circuit that outputs a selection signal corresponding to the count value of the counter;
The memory test apparatus according to claim 3, wherein the selection unit selects a bit stored in the second storage unit based on the selection signal output from the selection control circuit.   5. The storage device according to claim 1, further comprising a third storage unit that is provided corresponding to each of the output selection units and stores a selection signal that prescribes a selection rule for each of the output selection units in advance. A memory test apparatus according to claim 1.

Images