JP4946606B2 - DC voltage controller for inverters connected in series - Google Patents

Description

  The present invention relates to a DC voltage control device for inverters connected in series, and is particularly suitable for application to a method for eliminating an imbalance in DC voltage of each single-phase inverter.

In power converters that compensate reactive power in a power system, increasing the capacity by connecting single-phase inverters in series has been performed. In this case, an unbalance occurs in the DC voltage between the single-phase inverters due to a difference in device loss between the single-phase inverters connected in series, an output error of the AC output voltage, or the like.
Therefore, by changing the switching frequency of the single-phase inverter, it is possible to adjust the device loss that causes the DC voltage unbalance and to eliminate the DC voltage imbalance between the single-phase inverters connected in series. (Patent Document 1).

FIG. 4 is a voltage waveform diagram showing a method of eliminating the DC voltage imbalance of single-phase inverters connected in series by a conventional variable switching frequency system.
In FIG. 4A, the device loss between the single-phase inverters is compared, the switching frequency of the single-phase inverter having the larger device loss is lowered, and the device loss of the single-phase inverter having the larger device loss is reduced. Thus, the DC voltage of the DC capacitor in the single-phase inverter can be increased.

4B, the device loss between the single-phase inverters is compared, the switching frequency of the single-phase inverter having the smaller device loss is increased, and the device loss of the single-phase inverter having the smaller device loss is increased. By doing so, the DC voltage of the DC capacitor in the single-phase inverter can be reduced.
Further, in Patent Document 2, in a three-level power converter that outputs a three-level voltage for each phase, a terminal voltage of a capacitor that divides a DC power source into two is detected, and a short-circuit prevention period corresponding to the difference between the voltages A method is disclosed in which the on-timing of the switching element is delayed by an extension amount of the capacitor to equalize the capacitor voltage.
JP 2003-189475 A Japanese Patent Laid-Open No. 9-233850

However, in the method disclosed in Patent Document 1, the switching frequency differs between single-phase inverters connected in series. Therefore, the synthesized voltage obtained by synthesizing the AC output voltage Ed of each single-phase inverter has a switching frequency of There is a problem that beats due to the difference occur and harmonics included in the AC output voltage Ed increase.
Further, the method disclosed in Patent Document 2 is intended for a three-level power converter, and there is a problem that the DC voltage imbalance of single-phase inverters connected in series cannot be solved individually.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a DC voltage control device for inverters connected in series that can eliminate DC voltage imbalance between inverters without increasing harmonics contained in the output voltage. It is.

In order to solve the above-described problem, according to the DC voltage control device for serially connected inverters according to claim 1, the DC voltage in the inverter connected to the power system is individually connected to the AC output side in series. a DC voltage detection means detect, so that to increase the inverter DC voltage the smaller the smaller inverter on-delay time longer to the DC voltage of the said DC voltage than the larger of the inverter of the DC voltage On-delay time setting means for setting the on-delay time of the inverter, and gate pulse generation means for generating a gate pulse for driving the inverter based on the on-delay time set by the on-delay time setting means It is characterized by providing.

According to the DC voltage control apparatus for inverters connected in series according to claim 2, the on-delay time setting means delays the on-timing of the switching element provided in the inverter, thereby turning on the inverter. The delay time is set to be long.
According to the DC voltage control apparatus for inverters connected in series according to claim 3, the on-delay time setting means advances the off-timing of the switching element provided in the inverter, so that the on-delay of the inverter It is characterized in that the time is set longer.

  As described above, according to the present invention, the on-delay time of the inverter having the smaller DC voltage is made longer than that of the inverter having the larger DC voltage, whereby the DC capacitor in the inverter having the smaller DC voltage is supplied. The charging period can be lengthened, and the discharging period from the DC capacitor in the inverter having the smaller DC voltage can be shortened. Therefore, the DC voltage in the inverter with the smaller DC voltage can be increased, and even when the inverters are connected in series, the DC voltage imbalance between the inverters is not increased without increasing the harmonics contained in the output voltage. Can be eliminated.

Hereinafter, a DC voltage controller for inverters connected in series according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a schematic configuration of a power converter to which a DC voltage controller for single-phase inverters connected in series according to a first embodiment of the present invention is applied.
In FIG. 1, the power converter is provided with single-phase inverters INV1 and INV2 connected in series with each other, the AC output sides of the single-phase inverters INV1 and INV2 are connected in series, and connected to the power system Vs via the interconnection impedance L. It is connected.

  Here, the single-phase inverter INV1 is provided with switching elements U1, V1, X1, and Y1, and flywheel diodes E1, F1, G1, and H1 are connected in reverse parallel to the switching elements U1, V1, X1, and Y1, respectively. Has been. The switching elements U1 and X1 are connected in series with each other, and the switching elements V1 and Y1 are connected in series with each other. The switching elements U1, X1 connected in series are connected in parallel to the DC capacitor C1, and the switching elements V1, Y1 connected in series are connected in parallel to the DC capacitor C1.

  The single-phase inverter INV2 is provided with switching elements U2, V2, X2, and Y2, and flywheel diodes E2, F2, G2, and H2 are connected in reverse parallel to the switching elements U2, V2, X2, and Y2, respectively. ing. The switching elements U2 and X2 are connected in series with each other, and the switching elements V2 and Y2 are connected in series with each other. The switching elements U2, X2 connected in series are connected in parallel to the DC capacitor C2, and the switching elements V2, Y2 connected in series are connected in parallel to the DC capacitor C2. As the switching elements U1, V1, X1, Y1, U1, V2, X2, and Y2, for example, an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET, or the like can be used.

The connection point of the switching elements U1 and X1 is connected to the connection point of the switching elements V2 and Y2 via the interconnection impedance L and the power system Vs, and the connection point of the switching elements V1 and Y1 is the connection point of the switching elements U2 and X2. Connected to a point.
Further, the power converter is provided with a DC voltage detecting means 11, an on-delay time setting means 12, and a gate pulse generating means 13. Here, the DC voltage detecting means 11 can detect the voltages across the terminals of the DC capacitors C1 and C2. The on-delay time setting means 12 is configured to increase the on-delay time of the inverters INV1 and INV2 so that the on-delay time of the inverters INV1 and INV2 having a smaller voltage between the terminals of the DC capacitors C1 and C2 is smaller. You can set the time. Based on the on-delay time set by the on-delay time setting unit 12, the gate pulse generating unit 13 can generate a gate pulse for driving the inverters INV1 and INV2.

  Then, the DC voltage detection means 11 detects the voltage between the terminals of the DC capacitors C1 and C2, and sends the voltage between the terminals of the DC capacitors C1 and C2 to the on-delay time setting means 12. The on-delay time setting means 12 causes the on-delay time of the inverter INV1 to be longer than the on-delay time of the inverter INV2 when the voltage between the terminals of the DC capacitor C1 is smaller than the voltage between the terminals of the DC capacitor C2. Are set to ON delay times of the inverters INV1 and INV2, and the set ON delay times are transmitted to the gate pulse generating means 13. When the ON delay time of the inverter INV1 is set to be longer than the ON delay time of the inverter INV2, the gate pulse generating means 13 turns on the switching elements U1, V1, X1, and Y1 provided in the inverter INV1. The inverter INV1 is driven so that the timing is delayed between the upper and lower arms.

  When the on-delay time of the inverter INV1 becomes longer than the on-delay time of the inverter INV2, the charging period to the DC capacitor C1 in the inverter INV1 becomes longer and the discharging period from the DC capacitor C1 becomes shorter, and the DC in the inverter INV1 becomes shorter. The voltage between the terminals of the capacitor C1 can be increased.

  On the other hand, the on-delay time setting means 12 causes the on-delay time of the inverter INV2 to be longer than the on-delay time of the inverter INV1 when the voltage between the terminals of the DC capacitor C2 is smaller than the voltage between the terminals of the DC capacitor C1. Are set to ON delay times of the inverters INV1 and INV2, and the set ON delay times are transmitted to the gate pulse generating means 13. When the ON delay time of the inverter INV2 is set to be longer than the ON delay time of the inverter INV1, the gate pulse generating means 13 turns on the switching elements U2, V2, X2, Y2 provided in the inverter INV2. The inverter INV2 is driven so that the timing is delayed between the upper and lower arms.

When the on-delay time of the inverter INV2 becomes longer than the on-delay time of the inverter INV1, the charging period to the DC capacitor C2 in the inverter INV2 becomes longer and the discharging period from the DC capacitor C2 becomes shorter, and the DC in the inverter INV2 becomes shorter. The voltage between the terminals of the capacitor C2 can be increased.
As a result, even when the inverters INV1 and INV2 are connected in series, the DC voltage imbalance between the inverters INV1 and INV2 can be eliminated without increasing the harmonics included in the output voltages of the inverters INV1 and INV2. Thus, the capacity of the power conversion device can be increased while suppressing the increase in size and price of the power conversion device.

FIG. 2 is a diagram showing the relationship between the on / off operation of the switching element of the single-phase inverter and the charging / discharging of the DC capacitor according to one embodiment of the present invention. In the example of FIG. 2, the case where the AC output current I flows from the arm composed of the switching elements V1, Y1 to the arm composed of the switching elements U1, X1 in the inverter INV1 will be described as an example.
In FIG. 2A, when the switching elements U1 and V1 are turned on (mode 1), a current I flows through a path of flywheel diode F1 → switching element U1. In this mode 1, since the current I circulates between the switching elements U1 and V1, there is no charge / discharge of the DC capacitor C1.

In FIG. 2B, when the switching elements U1 and Y1 are turned on (mode 2), the current I flows through the path of the switching element Y1 → the DC capacitor C1 → the switching element U1. In this mode 2, since the current I flows from the negative electrode to the positive electrode of the DC capacitor C1, the DC capacitor C1 is discharged.
In FIG. 2C, when the switching elements X1 and V1 are turned on (mode 3), the current I flows through a path of flywheel diode F1 → DC capacitor C1 → flywheel diode G1. In this mode 3, since the current I flows from the positive electrode to the negative electrode of the DC capacitor C1, the DC capacitor C1 is charged.

In FIG. 2D, when the switching elements X1 and Y1 are turned on (mode 4), the current I flows through the path of the switching element Y1 → the flywheel diode G1. In this mode 4, since the current I circulates between the switching elements Y1 and X1, there is no charge / discharge of the DC capacitor C1.
In FIG. 2E, when the switching element V1 is turned on during the on-delay period of the switching elements U1 and X1 (mode 5), the current I flows through the path of flywheel diode F1 → DC capacitor C1 → flywheel diode G1. . In mode 5, since the current I flows from the positive electrode to the negative electrode of the DC capacitor C1, the DC capacitor C1 is charged.

In FIG. 2F, when the switching element Y1 is turned on during the on-delay period of the switching elements U1 and X1 (mode 6), the current I flows through the path of the switching element Y1 → the flywheel diode G1. In this mode 6, since the current I circulates between the switching elements Y1 and X1, there is no charge / discharge of the DC capacitor C1.
In FIG. 2G, when the switching element U1 is turned on during the on-delay period of the switching elements Y1 and Y1 (mode 7), a current I flows through a path of flywheel diode F1 → switching element U1. In this mode 7, since the current I circulates between the switching elements U1 and V1, there is no charge / discharge of the DC capacitor C1.

  In FIG. 2H, when the switching element X1 is turned on during the on-delay period of the switching elements V1 and Y1 (mode 8), the current I flows through the path of the flywheel diode F1 → DC capacitor C1 → flywheel diode G1. . In this mode 8, since the current I flows from the positive electrode to the negative electrode of the DC capacitor C1, the DC capacitor C1 is charged.

In the case where the polarity of the AC output current I is reversed, the relationship between the arm composed of the switching elements V1 and Y1 and the arm composed of the switching elements U1 and X1 is only reversed, and the description is omitted.
Here, in the single-phase inverters INV1 and INV2, in order to prevent a short circuit between the upper and lower arms, an on-delay time is provided for the ON signals of the switching elements U1, V1, X1, Y1, U2, V2, X2, and Y2. Yes.

FIG. 3 is a timing chart showing an on-delay time control method in the switching element of the single-phase inverter according to the embodiment of the present invention.
In FIG. 3A, for example, when the switching elements U1, V1 on the upper arm side of the inverter INV1 are turned off, the switching elements X1, Y1 on the lower arm side of the inverter INV1 are turned on with a delay of the on-delay time T.
When the voltage between the terminals of the DC capacitor C1 is smaller than the voltage between the terminals of the DC capacitor C2, the on-delay time T of the switching elements X1, Y1 on the lower arm side of the inverter INV1 can be increased by ΔT. When the switching elements U1 and V1 on the upper arm side of the inverter INV1 are turned off, the switching elements X1 and Y1 on the lower arm side of the inverter INV1 can be turned on with a delay of the on-delay time T + ΔT.

  Thereby, the ON period of the switching elements U1, V1, X1, and Y1 in the inverter INV1 can be shortened, the charging period to the DC capacitor C1 in the inverter INV1 is lengthened, and the discharging period from the DC capacitor C1 is shortened. be able to. As a result, the voltage across the terminals of the DC capacitor C1 in the inverter INV1 can be increased, and the DC voltage imbalance between the inverters INV1 and INV2 can be eliminated.

  Specifically, the on-delay time T is increased by ΔT, and the on-periods of the switching elements U1, V1, X1, and Y1 are shortened, so that the period of mode 1 in FIG. The period increases. When the mode 1 period decreases, the feedback feedback of the current I without charging / discharging the DC capacitor C1 decreases, and when the mode 5 period increases, the charging period of the DC capacitor C1 increases. The voltage across the terminals of the DC capacitor C1 at INV1 can be increased.

  Further, the on-delay time T is increased by ΔT, and the ON periods of the switching elements U1, V1, X1, and Y1 are shortened, so that the period of mode 2 in FIG. 2 is decreased and the period of mode 6 or mode 7 is increased. To do. When the mode 2 period decreases, the discharge period of the DC capacitor C1 decreases. When the modes 6 and 7 increase, the feedback feedback of the current I without charging / discharging the DC capacitor C1 increases. The voltage across the terminals of the DC capacitor C1 in the inverter INV1 can be increased.

  Further, the on-delay time T is increased by ΔT, and the ON period of the switching elements U1, V1, X1, and Y1 is shortened, so that the period of mode 3 in FIG. 2 is decreased and the period of mode 5 or mode 8 is increased. To do. Since the mode 3, the mode 5 and the mode 8 are modes for charging the DC capacitor C1, in this case, there is no increase in the voltage across the terminals of the DC capacitor C1 in the inverter INV1.

Further, the on-delay time T is increased by ΔT, and the ON period of the switching elements U1, V1, X1, and Y1 is shortened, so that the period of mode 4 in FIG. 2 is decreased and the period of mode 6 or mode 8 is increased. To do. When the mode 4 period decreases, the feedback feedback of the current I without charging / discharging the DC capacitor C1 decreases, and when the mode 8 period increases, the charging period of the DC capacitor C1 increases. The voltage across the terminals of the DC capacitor C1 at INV1 can be increased.
The operation for increasing the on-delay time T can be performed regardless of the AC output voltage of the single-phase inverter INV1, so that the single-phase can be changed without changing the value of the on-delay time T that is increased depending on the output voltage or current polarity. The DC voltage at the inverter INV1 can be increased.

  Further, in the above-described embodiment, the on-delay time of the inverters INV1 and INV2 is increased so that the on-delay time of the inverters INV1 and INV2 that are smaller than the inverters INV1 and INV2 that are larger in voltage between the terminals of the DC capacitors C1 and C2 is longer. In order to set the time, the inverters INV1 and INV2 are driven so that the ON timing of the switching elements provided in the inverters INV1 and INV2 having the smaller voltage between the terminals of the DC capacitors C1 and C2 is delayed between the upper and lower arms. However, the inverters INV1 and INV2 are driven so that the OFF timing of the switching elements provided in the inverters INV1 and INV2 having the smaller voltage between the terminals of the DC capacitors C1 and C2 is advanced between the upper and lower arms. Good.

It is a figure which shows schematic structure of the DC voltage control apparatus of the single phase inverter connected in series which concerns on one Embodiment of this invention. It is a figure which shows the relationship between ON / OFF operation | movement of the switching element of the single phase inverter which concerns on one Embodiment of this invention, and charging / discharging of a DC capacitor. It is a timing chart which shows the control method of the on-delay time in the switching element of the single phase inverter which concerns on one Embodiment of this invention. It is a voltage waveform diagram which shows the cancellation method of the imbalance of the DC voltage of the single phase inverter connected in series by the conventional switching frequency variable system.

Explanation of symbols

INV1, INV2 Single-phase inverter Vs Power system L Linkage impedance C1, C2 DC capacitors U1, V1, X1, Y1, U2, V2, X2, Y2 Switching elements E1, F1, G1, H1, E2, F2, G2, H2 Flywheel diode 11 DC voltage detection means 12 On-delay time setting means 13 Gate pulse generation means

Claims (3)

DC voltage detection means for individually detecting the DC voltage in the inverter connected in series on the AC output side and linked to the power system ;
The on-delay time of the inverter so that increases the inverter DC voltage the smaller the smaller inverter on-delay time longer to the DC voltage of the said DC voltage than the larger of the inverter of the DC voltage On-delay time setting means for setting,
A DC voltage control apparatus for inverters connected in series, comprising: gate pulse generation means for generating a gate pulse for driving the inverter based on the on-delay time set by the on-delay time setting means .   The serial connection according to claim 1, wherein the on-delay time setting means sets the on-delay time of the inverter to be longer by delaying an on-timing of a switching element provided in the inverter. Inverter DC voltage control device.   3. The series according to claim 1, wherein the on-delay time setting means sets the on-delay time of the inverter to be longer by advancing the off timing of the switching element provided in the inverter. DC voltage controller for connected inverter.

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