JP4140169B2 - Non-contact power transmission device - Google Patents

Description

【００３１】
このように、ＦＥＴＱ１に流れる電流を検出し、前記検出信号に同期した信号でＦＥＴ素子Ｐ１を駆動すれば、ＦＥＴＱ１の寄生ダイオードＤ１に電流が流れる時間を短くすることができ、ＦＥＴＱ１での損失を低減できる。その結果、放熱板のサイズを小さくできるため、２次側回路Ｇ２を小型化できる。
【００３２】
（参考例２）
図３は参考例２の回路構成を示す。電源部Ａ、インバータ部Ｂ、トランスＴ１の１次コイルＬ１からなる１次側回路Ｇ１の構成、動作は参考例１と同様なので省略する。
【００３３】
トランスＴ１の２次コイルＬ２は出力端子が３つあるセンタータップ方式となっており、２次コイルＬ２両端の端子１及び３とセンタータップ端子２の３つの端子を有し、２次コイルＬ２の端子１−端子３間に並列に負荷整合用のコンデンサＣ１を接続する。２次コイルＬ２の端子１に直列に電流検知部Ｈ１を介して同期整流要素を構成するＦＥＴＱ１のドレインを接続し、２次コイルＬ２の端子３に直列に電流検知部Ｈ３を介して同期整流要素を構成するＦＥＴＱ２のドレインを接続する。ＦＥＴＱ１、Ｑ２の各ソースは互いに接続し、平滑コンデンサＣ８の負極側に接続し、２次コイルＬ２の端子３は、チョークコイルＬ３を介して平滑コンデンサＣ８の正極側に接続する。
【００３４】
次に、本参考例の動作について説明する。ＦＥＴＱ１は、ＦＥＴ素子Ｐ１とＦＥＴ素子Ｐ１に並列に逆方向の接続された寄生ダイオードＤ１とからなっている。ＦＥＴＱ１に直列に接続された電流検知部Ｈ１はＦＥＴＱ１に流れる電流を検出し、前記検出信号を駆動信号生成部Ｅ１に出力する。駆動信号生成部Ｅ１は、電流検知部Ｈ１からの検出信号が所定のしきい値以上であればＦＥＴ素子Ｐ１をオンにする駆動信号を出力し、電流検知部Ｈ１からの信号が所定のしきい値以下であればＦＥＴ素子Ｐ１をオフにする駆動信号を出力する。
【００３５】
同様にＦＥＴＱ２は、ＦＥＴ素子Ｐ２とＦＥＴ素子Ｐ２に並列に逆方向の接続れた寄生ダイオードＤ２とからなっている。ＦＥＴＱ２に直列に接続された電流検知部Ｈ２はＦＥＴＱ２に流れる電流を検出し、前記検出信号を駆動信号生成部Ｅ２に出力する。駆動信号生成部Ｅ２は、電流検知部Ｈ２からの検出信号が所定のしきい値以上であればＦＥＴ素子Ｐ２をオンにする駆動信号を出力し、電流検知部Ｈ２からの信号が所定のしきい値以下であればＦＥＴ素子Ｐ２をオフにする駆動信号を出力する。
【００３６】
電磁誘導によって１次コイルＬ１から２次コイルＬ２の端子２−１間に誘導される起電力の極性が、ＦＥＴＱ１の寄生ダイオードＤ１の順方向と合致した時に寄生ダイオードＤ１に順方向電流が流れ、前記順方向電流を電流検知部Ｈ１にて検出し、駆動信号生成部Ｅ１は電流検知部Ｈ１の検出信号が前記しきい値を超えるとＦＥＴ素子Ｐ１にオン信号を出力してＦＥＴ素子Ｐ１はオンする。
ＦＥＴ素子Ｐ１がオンすると当初寄生ダイオードＤ１を流れていた電流は寄生ダイオードＤ１に比べてＦＥＴ素子Ｐ１のほうが抵抗が小さいので、ＦＥＴ素子Ｐ１のオン抵抗を介してＦＥＴＱ１のソースからドレイン方向に流れる。この時、参考例１同様、ＦＥＴＱ１に整流電流が流れるサイクル中にＦＥＴ素子のオン時間をできるだけ長くしたほうが、ＦＥＴＱ１での損失を小さくでき、整流損失を減らすことができる。
【００３７】
電磁誘導によって１次コイルＬ１から２次コイルＬ２に誘導される起電力が変化して２次コイルＬ２に誘導される起電力が小さくなると電流検知部Ｈ１から出力される検出信号も小さくなり、駆動信号生成部Ｅ１は電流検知部Ｈ１からの検出信号が前記しきい値より下がるとＦＥＴ素子Ｐ１にオフ信号を出力してＦＥＴ素子Ｐ１はオフする。
【００３８】
さらに、２次コイルＬ２に誘導された起電力の極性が反転するとＦＥＴ素子Ｐ１の寄生ダイオードＤ１には逆方向の電圧がかかるため、再び２次コイルＬ２に誘導された起電力の極性が反転するまで寄生ダイオードＤ１には電流は流れない。
【００３９】
一方この時、電磁誘導によって１次コイルＬ１から２次コイルＬ２の端子２−３間に誘導された起電力の極性は、ＦＥＴＱ２の寄生ダイオードＤ２の順方向と合致しているため、寄生ダイオードＤ２に順方向電流が流れ、ＦＥＴＱ２、ＦＥＴ素子Ｐ２、寄生ダイオードＤ２、電流検知部Ｈ２、駆動信号生成部Ｅ２は前記ＦＥＴＱ１、ＦＥＴ素子Ｐ１、寄生ダイオードＤ１、電流検知部Ｈ１、駆動信号生成部Ｅ１と同様の前記動作を行う。
【００４０】
前記動作を繰り返して、ＦＥＴＱ１、Ｑ２のソースと２次コイルＬ２の端子２間の電圧には全波整流された電圧が生じ、チョークコイルＬ３と平滑コンデンサＣ８とで平滑される。
【００４１】
図４は、２次コイルＬ２の端子１−３間の誘導起電力波形Ｓ２と、２次コイルＬ２を流れる電流波形Ｓ３と、ＦＥＴＱ１、Ｑ２のオンしきい値Ｋとを示している。負荷整合用のコンデンサＣ１の影響で、２次コイルＬ２の電流波形Ｓ３は歪んだ波形になり、２次コイルＬ２の端子１−３間に誘起する電圧波形Ｓ２は一定区間０Ｖである区間を挟んで正負に振動した波形となる。そのため、従来の補助巻線や２次コイル間電圧を利用したＦＥＴの駆動方式ではＦＥＴＱ１、Ｑ２のオンしきい値Ｋと前記電圧波形Ｓ２とを比較すると、ＦＥＴの駆動信号は波形Ｓ４のようになり、ＦＥＴＱ１及びＱ２をオンする時間が短いため整流効率が上がらない。
【００４２】
しかし、図５に示す様にＦＥＴＱ１を流れる電流波形Ｓ５とＦＥＴＱ１、Ｑ２のオンしきい値Ｋとを比較し、またＦＥＴＱ２を流れる電流波形Ｓ６とＦＥＴＱ１、Ｑ２のオンしきい値Ｋとを比較することで、ＦＥＴＱ１、Ｑ２の駆動信号は各々波形Ｓ７、Ｓ８のようになり、図４の波形Ｓ４に比べてＦＥＴＱ１、Ｑ２のＦＥＴ素子Ｐ１、Ｐ２のオン時間が長くなる。したがって、ＦＥＴ素子Ｐ１、Ｐ２に整流電流が流れる時間が長くなり、整流効率が上がる。
【００４３】
また本参考例に示す２次コイルがセンタータップ方式であるトランスＴ１を用いた全波整流回路と参考例１に示す半波整流回路とを比較すると、同じ出力電流を流す場合、全波整流回路は半波整流回路に比べてＦＥＴに流す電流の最大値を小さくできる。ＦＥＴ素子Ｐ１，Ｐ２がオンした時の損失は電流の２乗に比例するので、本参考例では、ＦＥＴ素子Ｐ１，Ｐ２に流す電流を半波整流回路に比べて小さくでき、損失を減らすことができる。
【００４４】
なお、図６に示す回路構成の様に、負荷整合用のコンデンサＣ１を２次コイルＬ２の端子１−端子２間に並列に接続し、負荷整合用のコンデンサＣ９を２次コイルＬ２の端子２−端子３間に並列に接続した場合も図４の負荷整合用のコンデンサＣ１と同様の効果が得られる。さらに、前記コンデンサＣ１をＦＥＴＱ１に並列に接続し、前記コンデンサＣ９をＦＥＴＱ２並列に接続しても同様の効果が得られる。
【００４５】
なお、図１において負荷整合用コンデンサＣ１をＦＥＴＱ１に並列に接続しても同様の効果が得られる。
【００４６】
（参考例３）
図７は参考例３の回路構成を示し、交流電源を直流電源に変換する電源部Ａと電源部Ａからの直流入力を高周波電源に変換するインバータ部Ｂと、インバータ部Ｂの制御回路Ｊと、インバータ部Ｂから高周波電源を供給されるトランスＴ１の１次コイルＬ１とから１次側回路Ｇ１は構成され、トランスＴ１のセンタータップ式の２次コイルＬ２と、負荷整合用コンデンサＣ１と、電流検知部Ｈ１，Ｈ２と、駆動信号生成部Ｅ１，Ｅ２と、ＦＥＴＱ１，Ｑ２とチョークコイルＬ３と、平滑コンデンサＣ８とで構成される２次側回路Ｇ２とからなっている。
【００４７】
２次側回路Ｇ２の構成、動作は参考例２の図３と同様なので説明は省略する。
【００４８】
１次側回路Ｇ１の構成、動作について説明する。電源部Ａは、交流電源Ｖｓと交流電源Ｖｓを全波整流する整流器Ｄ３とから構成され、インバータ部Ｂは整流器Ｄ３の出力端に並列に接続されたコンデンサＣ２、Ｃ３の直列回路と、整流器Ｄ３の出力端に並列に接続されたスイッチング素子Ｑ３、Ｑ４の直列回路と、スイッチング素子Ｑ３、Ｑ４に各々並列に接続されたコンデンサＣ４，Ｃ５とからなるハーフブリッジインバータ回路で構成され、制御回路Ｊはスイッチング素子Ｑ３，Ｑ４のスイッチング動作を制御するための電子回路から構成され、トランスＴ１の１次コイルＬ１の一端はコンデンサＣ１、Ｃ２の中点に接続され、他端はスイッチング素子Ｑ１、Ｑ２の中点に接続される。
【００４９】
整流器Ｄ３で全波整流された電圧はコンデンサＣ２、Ｃ３で分圧され、スイッチング素子Ｑ３，Ｑ４は制御回路Ｊからの一定のデッドタイムを持った駆動信号により交互にオン・オフして１次コイルＬ１に高周波電圧を印加する。
【００５０】
また、スイッチング素子Ｑ３、Ｑ４に並列に接続されたコンデンサＣ４，Ｃ５により、スイッチング素子Ｑ３，Ｑ４のスイッチング動作をゼロ電圧スイッチング動作とすることができ、スイッチング素子Ｑ３、Ｑ４でのスイッチング損失を減少させることができる。
【００５１】
またスイッチング素子Ｑ３、Ｑ４の駆動信号は一定のデッドタイムを持っているので、トランスＴ１の２次コイルＬ２の端子１−端子３間の電圧は図４の波形Ｓ２のようになるため、参考例２と同様に電流検出回路Ｈ１、Ｈ２の検出信号から生成した駆動信号でＦＥＴＱ１、Ｑ２による同期整流を行えば、参考例２同様に２次側回路Ｇ２の整流損失も減少できる。
【００５２】
また、図８に示す回路構成のようにトランスＴ１の１次コイルＬ１に並列にコンデンサＣ４を接続した場合も、図７の回路同様にゼロ電圧スイッチングを行える。前記以外の図８の回路の構成、動作は図７の回路の構成、動作と同様なので説明は省略する。
【００５３】
このように本参考例によれば、２次側回路Ｇ２だけでなく、１次側回路Ｇ１での損失を減らして、回路全体の効率を上げて回路全体の小型化ができる。
【００５４】
（参考例４）
図９は参考例４の回路構成を示す。基本的な回路構成、動作は参考例３の図７と同様で、ＦＥＴ素子Ｐ１の駆動信号生成部Ｅ１の駆動信号を反転器ＩＮＶ１を介して反転させた信号をＦＥＴ素子Ｐ２の駆動信号とした点が図７に示す回路構成と異なる。前記以外の回路構成、動作については参考例３の図７と同様なので省略する。
【００５５】
図９に示す回路構成図のように、トランスＴ１の２次コイルＬ２にセンタータップ方式を用いた同期整流回路では、ＦＥＴＱ１、Ｑ２に交互に電流が流れるようにＦＥＴＱ１、Ｑ２の駆動信号を制御するため、ＦＥＴＱ１、Ｑ２の各駆動信号は、一方の駆動信号の反転信号となる。そこで、ＦＥＴＱ１の駆動信号生成部Ｅ１の駆動信号を反転器ＩＮＶ１を介して反転させた信号をＦＥＴＱ２の駆動信号としてＦＥＴＱ２を駆動することで、ＦＥＴＱ２の駆動回路の簡素化を図ることができ、低コスト化、小型化ができる。
【００５６】
なお、２次側回路Ｇ２の整流回路として、同期整流を用いたフォワード方式を採用した場合にも、２つの整流及び転流用スイッチング素子にたいしても同様に応用できる。
【００５７】
（参考例５）
図１０は参考例５の回路構成図を示す。基本的な回路構成、動作は参考例３の図７とほぼ同様で、図１０では、図７の電流検知部Ｈ１、Ｈ２を、各々ＦＥＴＱ１、Ｑ２に直列に接続した抵抗Ｒ１、Ｒ２からなる電流検知部Ｈ３、Ｈ４に置き換えた点が異なる。前記以外の回路構成、動作については参考例３の図７と同様なので省略する。
【００５８】
本参考例では、ＦＥＴＱ１、Ｑ２に各々直列に接続された抵抗Ｒ１、Ｒ２の両端には各々ＦＥＴＱ１、Ｑ２に流れる電流に比例した電圧が発生する。前記抵抗Ｒ１、Ｒ２の各両端電圧を駆動信号生成部Ｅ１、Ｅ２に各々入力し、駆動信号生成部Ｅ１、Ｅ２は、抵抗Ｒ１、Ｒ２の各両端電圧が所定のしきい値以上であればＦＥＴ素子Ｐ１、Ｐ２を各々オンにする駆動信号を出力し、抵抗Ｒ１、Ｒ２の各両端電圧が所定のしきい値以下であればＦＥＴ素子Ｐ１、Ｐ２を各々オフにする駆動信号を出力する。
【００５９】
このように本参考例によれば、簡単な方法でＦＥＴＱ１、Ｑ２の電流を検出でき、前記検出信号を用いてＦＥＴＱ１、Ｑ２の駆動信号を生成することで参考例２同様にＦＥＴＱ１、Ｑ２に電流が流れる各整流サイクル中にできるだけ長い間ＦＥＴ素子Ｐ１、Ｐ２をオンにして、整流損失を減らすことができる。
【００６０】
（参考例６）
図１１は本参考例６の回路構成図を示し、基本的な回路構成、動作は参考例５の図１０と同様で、図１１では、図１０の抵抗Ｒ１、Ｒ２を各々微小な抵抗値（例えば１０ｍΩ）を有する抵抗Ｒ３、Ｒ４からなる電流検出部Ｈ５、Ｈ６に置き換え、駆動信号生成部Ｅ１、Ｅ２を各々オペアンプＯＰ１、ＯＰ２からなる駆動信号生成部Ｅ３、Ｅ４に置き換えた点が異なる。前記以外の回路構成、動作については参考例５の図１０と同様なので省略する。
【００６１】
本参考例では、ＦＥＴＱ１、Ｑ２に各々直列に接続された抵抗Ｒ３、Ｒ４の抵抗値を微小な抵抗値（例えば１０ｍΩ）とすることで、参考例５に比べて抵抗Ｒ３、Ｒ４での損失を減らしている。しかし抵抗Ｒ３、Ｒ４の抵抗値を小さくしたことで抵抗Ｒ３、Ｒ４両端の電圧も小さくなるため、抵抗Ｒ３、Ｒ４両端の電圧を各々オペアンプＯＰ１、ＯＰ２の反転入力端子と非反転入力端子とに入力し、オペアンプＯＰ１、ＯＰ２で抵抗Ｒ３、Ｒ４の各両端電圧を、ＦＥＴＱ１、Ｑ２を十分駆動できる電圧にまで差動増幅し、前記差動増幅したオペアンプＯＰ１、ＯＰ２の出力をＦＥＴ素子Ｐ１、Ｐ２の駆動信号とする。
【００６２】
このように本参考例では、電流検知部Ｈ５、Ｈ６での損失を下げることができる。
【００６３】
（参考例７）
図１２は参考例７の回路構成図を示す。基本的な回路構成、動作は参考例３の図７とほぼ同様で、図１２では図７の電流検知部Ｈ１、Ｈ２を各々、１次コイルＬ４、Ｌ５と２次コイルＬ６、Ｌ７からなるカレントトランスＣＴ１、ＣＴ２の２次コイルＬ６、Ｌ７に並列に抵抗Ｒ５、Ｒ６を各々接続し、前記２次コイルＬ６、Ｌ７に直列にダイオードＤ３、Ｄ４を各々接続し、ダイオードＤ３、Ｄ４を介して抵抗Ｒ５、Ｒ６に並列にコンデンサＣ６、Ｃ７、抵抗Ｒ７、Ｒ８及び定電圧ダイオードＺＤ１、ＺＤ２を各々接続した電流検知部Ｈ７、Ｈ８に置き換えた点と、図７の駆動信号生成部Ｅ１、Ｅ２を各々ダイオードＤ３、Ｄ４に直列に接続した増幅器ＡＭＰ１、ＡＭＰ２からなる駆動信号生成部Ｅ５、Ｅ６に置き換えた点とが異なる。前記以外の回路構成、動作については参考例３の図７と同様なので省略する。
【００６４】
カレントトランスＣＴ１、ＣＴ２の各１次コイルＬ４、Ｌ５に流れる電流をカレントトランスＣＴ１、ＣＴ２の各２次コイルＬ６、Ｌ７で検出し、抵抗Ｒ５、Ｒ６の両端に各々電圧を発生させ、前記電圧はダイオードＤ３、Ｄ４で各々半波整流される。コンデンサＣ６、Ｃ７はノイズカット用であり、抵抗Ｒ７、Ｒ８はコンデンサＣ６、Ｃ７に蓄積された電荷を放出してＡＭＰ１、２の入力信号の立下りを急峻にする。また、定電圧ダイオードＺＤ１、ＺＤ２は増幅器ＡＭＰ１、２の入力に増幅器ＡＭＰ１、２の定格電圧を超えた電圧が入力されないように半波整流した電圧を一定電圧でクランプする。
【００６５】
そして、カレントトランスＣＴ１、ＣＴ２の２次コイルＬ６、Ｌ７の出力電流は小さいためにＦＥＴ素子Ｐ１、Ｐ２を駆動できないので、増幅器ＡＭＰ１、ＡＭＰ２で増幅し、前記増幅した駆動信号でＦＥＴＱ１、Ｑ２を駆動する。
【００６６】
このように本参考例によれば、ＦＥＴＱ１、Ｑ２を流れる電流を検出でき、前記検出信号を用いてＦＥＴＱ１、Ｑ２の駆動信号を生成することで参考例２同様にＦＥＴＱ１、Ｑ２に電流が流れる各整流サイクル中にできるだけ長い間ＦＥＴ素子Ｐ１、Ｐ２をオンにして、整流損失を減らすことができる。
【００６７】
（参考例８）
図１３の回路構成図を用いて参考例８を説明する。基本的な回路構成、動作は参考例７の図１２とほぼ同様で、図１３では、図１２の増幅器ＡＭＰ１、ＡＭＰ２を、比較器ＣＰ１、ＣＰ２と比較器ＣＰ１、ＣＰ２の反転入力端子に基準電圧源Ｅ１、Ｅ２を各々接続した比較回路に置き換えた点が異なる。前記以外の回路構成、動作については参考例７の図１２と同様なので省略する。
【００６８】
本参考例では、ダイオードＤ３、Ｄ４で半波整流されたカレントトランスＣＴ１、ＣＴ２の各２次コイルＬ６、Ｌ７の出力を各々比較器ＣＰ１、ＣＰ２の非反転入力端子に接続し、基準電圧源Ｅ１、Ｅ２を各々比較器ＣＰ１、ＣＰ２の反転入力端子に接続して、基準電圧源Ｅ１、Ｅ２の基準電圧を適切に設定することで、ＦＥＴＱ１、Ｑ２に電流が流れる各整流サイクル中にできるだけ長い間ＦＥＴ素子Ｐ１、Ｐ２をオンにして、整流損失を減らすことができる。
【００６９】
図１４は、本参考例におけるＦＥＴＱ１を流れる電流波形Ｓ９と、基準電圧源Ｅ１の基準電圧Ｍ１と、比較器ＣＰ１の出力波形Ｓ１０を示しており、前記波形Ｓ９が前記基準電圧Ｍ１を超えると前記波形Ｓ１０はＨレベルとなり、前記波形Ｓ９が前記基準電圧Ｍ１より下がると前記波形Ｓ１０はＬレベルとなる。したがって、基準電圧Ｍ１を適切に設定することで比較器ＣＰ１の出力波形Ｓ１０がＨレベルの区間を広くできる。ＦＥＴＱ２についても同様である。
【００７０】
即ちＦＥＴＱ１、Ｑ２に電流が流れる各整流サイクル中にできるだけ長い間ＦＥＴ素子Ｐ１、Ｐ２をオンにして、整流損失を減らすことができる。
【００７１】
（実施形態１）
図１３の回路構成図を用いて実施形態１を説明する。基本的な回路構成、動作については参考例８と同様なので省略する。
【００７２】
同期整流を行うためにオンしていたＦＥＴ素子Ｐ１を有するＦＥＴＱ１の電流は、負荷整合用コンデンサＣ６のために２次コイルＬ２に発生する誘導起電力に応じてなめらかに電流値が減少していく。また次の半サイクルの同期整流を行うためにオンするＦＥＴ素子Ｐ２を有するＦＥＴＱ２も同様にコンデンサＣ６のために、ＦＥＴＱ１に流れる電流がゼロになる前に寄生ダイオードＤ２を介して電流が流れ始める。そのため、ＦＥＴ素子Ｐ１、Ｐ２が同時にオンする可能性があり、整流が行われなくなる可能性がある。
【００７３】
そこで本実施形態では、ＦＥＴＱ１、Ｑ２に流れる各電流が等しくなった時にそれまでオンしていたＦＥＴ素子Ｐ１をオフにする駆動信号を比較器ＣＰ１から出力し、それまでオフしていたＦＥＴ素子Ｐ２をオンにする駆動信号を比較器ＣＰ２から出力する。また、逆の半サイクルも同様にＦＥＴＱ１、Ｑ２に流れる各電流が等しくなった時にそれまでオンしていたＦＥＴ素子Ｐ２をオフにする駆動信号を比較器ＣＰ２から出力し、それまでオフしていたＦＥＴ素子Ｐ１をオンにする駆動信号を比較器ＣＰ１から出力する。
【００７４】
このように、本実施形態によれば、ＦＥＴ素子Ｐ１、Ｐ２が同時にオンすることがなくなり、整流損失を減らせて放熱板を含む２次側回路Ｇ２を小型化できる。
【００７５】
（実施形態２）
図１３の回路構成図を用いて実施形態２を説明する。基本的な回路構成、動作については実施形態１と同様なので省略する。
【００７６】
実施形態１で説明したように、ＦＥＴＱ１、Ｑ２に流れる各電流が等しくなった時にそれまでオンしていたＦＥＴ素子Ｐ１をオフにする駆動信号を比較器ＣＰ１から出力し、それまでオフしていたＦＥＴ素子Ｐ２をオンにする駆動信号を比較器ＣＰ２から出力する。また、逆の半サイクルも同様にＦＥＴＱ１、Ｑ２に流れる各電流が等しくなった時にそれまでオンしていたＦＥＴ素子Ｐ２をオフにする駆動信号を比較器ＣＰ２から出力し、それまでオフしていたＦＥＴ素子Ｐ１をオンにする駆動信号を比較器ＣＰ１から出力すれば、ＦＥＴ素子Ｐ１、Ｐ２が同時にオンすることなくなり、整流損失を減らせる。
【００７７】
そこで、本実施形態では図１３の回路構成においてカレントトランスＣＴ１、ＣＴ２で検出した各検出信号をダイオードＤ３、Ｄ４で半波整流した出力電圧、即ち定電圧ダイオードＺＤ１、ＺＤ２の各出力電圧を比較器ＣＰ１、ＣＰ２の非反転入力端子に入力し、ＦＥＴＱ１、Ｑ２に流れる各電流が等しくなった時の定電圧ダイオードＺＤ１、ＺＤ２の各出力電圧を基準電圧とする基準電圧源Ｅ１、Ｅ２を比較器ＣＰ１、ＣＰ２の反転入力端子に入力に各々接続して、比較器ＣＰ１、ＣＰ２の出力をＦＥＴ素子Ｐ１、Ｐ２の各駆動信号とすることで、ＦＥＴ素子Ｐ１、Ｐ２が同時にオンすることがなくなり、整流損失を減らせて放熱板を含む２次側回路Ｇ２を小型化できる。
【００７８】
図１５は、本実施形態におけるＦＥＴＱ１を流れる電流波形Ｓ１１、基準電圧源Ｅ１の基準電圧Ｍ２、比較器ＣＰ１の出力波形Ｓ１２と、ＦＥＴＱ２を流れる電流波形Ｓ１３、基準電圧源Ｅ２の基準電圧Ｍ３、比較器ＣＰ２の出力波形Ｓ１４とを示す。ＦＥＴＱ１を流れる電流波形Ｓ１１の大きさとＦＥＴＱ２を流れる電流波形Ｓ１３の大きさとが等しくなる時間ｔ４において比較器ＣＰ１の出力をＬにしてＦＥＴ素子Ｐ１をオフにし、比較器ＣＰ２の出力をＨにしてＦＥＴ素子Ｐ２をオンにすることでＦＥＴ素子Ｐ１、Ｐ２が同時にオンすることがなくなり、整流損失を減らせて放熱板を含む２次側回路Ｇ２を小型化できる。
【００７９】
（実施形態３）
図１２の回路構成図を用いて実施形態３を説明する。基本的な回路構成、動作については参考例７と同様なので省略する。
【００８０】
実施形態１で説明したように、ＦＥＴＱ１、Ｑ２に流れる各電流が等しくなった時にそれまでオンしていたＦＥＴＱ１をオフにする駆動信号を比較器ＣＰ１から出力し、それまでオフしていたＦＥＴＱ２をオンにする駆動信号を比較器ＣＰ２から出力する。また、逆の半サイクルも同様にＦＥＴＱ１、Ｑ２に流れる各電流が等しくなった時にそれまでオンしていたＦＥＴＱ２をオフにする駆動信号を比較器ＣＰ２から出力し、それまでオフしていたＦＥＴＱ１をオンにする駆動信号を比較器ＣＰ１から出力すれば、ＦＥＴＱ１、Ｑ２が同時にオンすることがなくなり、整流損失を減らせる。
【００８１】
そこで、本実施形態では図１２の回路構成においてＦＥＴＱ１、Ｑ２に流れる電流が等しくなるときに、カレントトランスＣＴ１、ＣＴ２で検出した各検出信号をダイオードＤ３、Ｄ４で半波整流した出力電圧、即ち定電圧ダイオードＺＤ１、ＺＤ２の各出力電圧を増幅器ＡＭＰ１、２で各々増幅したＦＥＴ素子Ｐ１、Ｐ２の各駆動信号が、ＦＥＴ素子Ｐ１、Ｐ２を十分オンできる電圧になるように、カレントトランスＣＴ１の１次コイルＬ４と２次コイルＬ６との巻線比及び、カレントトランスＣＴ２の１次コイルＬ５と２次コイルＬ７との巻線比を設定する。
【００８２】
図１６は、本実施形態におけるＦＥＴ素子Ｐ１の駆動信号波形Ｓ１５、ＦＥＴＱ１を流れる電流波形Ｓ１６、定電圧ダイオードＺＤ１のクランプ電圧Ｎ１と、ＦＥＴ素子Ｐ２の駆動信号波形Ｓ１７、ＦＥＴＱ２を流れる電流波形Ｓ１８、定電圧ダイオードＺＤ２のクランプ電圧Ｎ２と、ＦＥＴ素子Ｐ１、Ｐ２を十分オンできる電圧Ｋとを示している。ＦＥＴＱ１を流れる電流波形Ｓ１６の大きさとＦＥＴＱ２を流れる電流波形Ｓ１８の大きさとが等しくなる時間ｔ５において、ＦＥＴ素子Ｐ１の駆動信号波形Ｓ１５がＦＥＴ素子Ｐ１、Ｐ２を十分オンできる電圧Ｋより下がってＦＥＴ素子Ｐ１はオフになり、ＦＥＴ素子Ｐ２の駆動信号波形Ｓ１７がＦＥＴ素子Ｐ１、Ｐ２を十分オンできる電圧Ｋを超えてＦＥＴ素子Ｐ２はオンになることでＦＥＴ素子Ｐ１、Ｐ２が同時にオンすることがなくなり、整流損失を減らせて放熱板を含む２次側回路Ｇ２を小型化できる。
【００８３】
なお、前記波形Ｓ１５、Ｓ１７は定電圧電圧ダイオードＺＤ１、ＺＤ２のクランプ電圧Ｎ１、Ｎ２にクランプされる。
【００８４】
（参考例９）
図１に示す回路構成図のように、１つの同期整流用ＦＥＴＱ１を用いて半波整流を行う場合、ＦＥＴＱ１での整流損失を小さくするためにはＦＥＴＱ１に電流が流れる整流サイクル中にできるだけ長い間ＦＥＴＱ１のＦＥＴ素子Ｐ１をオンにする必要がある。
【００８５】
図１の電流検出部Ｈ１と駆動信号生成部Ｅ１とを、図１３の電流検出部Ｈ９と駆動信号生成部Ｅ７に各々置き換えて、駆動信号生成部Ｅ７の比較器ＣＰ１の反転入力端子に接続している基準電圧源Ｅ１の基準電圧を０Ｖ付近にすることで、比較器ＣＰ１は前記整流サイクル中にできるだけ長い間ＦＥＴ素子Ｐ１をオンにする駆動信号を出力して、ＦＥＴＱ１での整流損失を減らせて放熱板を含む２次側回路Ｇ２を小型化できる。
【００８６】
上記以外の回路構成、動作については、参考例１及び８で説明しているので省略する。
【００８７】
（参考例１０）
図１に示す回路構成図のように、１つの同期整流用ＦＥＴＱ１を用いて半波整流を行う場合、ＦＥＴＱ１での整流損失を小さくするためにはＦＥＴＱ１に電流が流れる整流サイクル中にできるだけ長い間ＦＥＴＱ１のＦＥＴ素子Ｐ１をオンにする必要がある。
【００８８】
図１の電流検出部Ｈ１と駆動信号生成部Ｅ１とを、図１２の電流検出部Ｈ７と駆動信号生成部Ｅ５に各々置き換えて、電流検出部Ｈ７のカレントトランスＣＴ１の１次コイルＬ４と２次コイルＬ５の巻数比を大きくすることで、カレントトランスＣＴ１の１次コイルＬ４に流れる電流が小さい時でも２次コイルＬ５の誘起電圧が大きくなり、ＦＥＴＱ１のＦＥＴ素子Ｐ１をオンできる駆動信号が増幅器ＡＭＰ１から出力される。したがって、整流素子Ｐ１は前記整流サイクル中にできるだけ長い間オンになり、ＦＥＴＱ１での整流損失を減らせて放熱板を含む２次側回路Ｇ２を小型化できる。
【００８９】
上記以外の回路構成、動作については、参考例１及び７で説明しているので省略する。
【００９０】
【発明の効果】
請求項１の発明は、直流電源を供給する電源部と、前記直流電源を高周波電源に変換するインバータ部と、前記インバータ部から高周波電力を供給される１次コイルと１次コイルから受電した電力を出力する２次コイルとが分離可能なトランスの前記１次コイルとで構成される１次側回路と、前記２次コイルと、前記２次コイルに並列に接続される負荷整合用コンデンサ及び前記２次コイルの出力電圧を整流する整流部とで構成される２次側回路とを有する非接触電力伝達装置において、前記トランスの２次コイルはセンタータップを備え、スイッチング素子及び前記スイッチング素子に並列に逆接続されたダイオードとからなる第１，第２の同期整流要素を具備して、前記トランスの２次コイルのセンタータップではない両出力端に直列に且つ互いに逆方向に接続する前記第１，第２の同期整流要素の前記トランスの２次コイルに接続していない各他端同士を接続して全波整流部を構成した前記整流部と、前記第１，第２の同期整流要素に流れる電流を検出する電流検知部と、先に導通し整流を終了しつつある前記第１の同期整流要素を流れる電流値と、次の整流のために導通を行うべき前記第２の同期整流要素のダイオードに流れ始める電流値とが相等しくなる時刻に、前記第１の同期整流要素のスイッチング素子をオフにする駆動信号を出力する第１の駆動信号生成部と、前記第２の同期整流要素のスイッチング素子をオンにする駆動信号を出力する第２の駆動信号生成部とを有することを特徴とし、２次側回路の整流損失を減らして、整流部の放熱板のサイズを小さくでき、回路全体の効率を上げることができるという効果がある。また、全波整流することで半波整流よりも損失が少なく効率の良い整流を行えるという効果がある。さらに、２次側回路の整流損失を減らして、整流部の放熱板のサイズを小さくでき、回路全体の効率を上げることができるという効果がある。
【００９１】
請求項２の発明は、請求項１の発明において、一つの前記電流検知部の検出信号より前記第１の同期整流要素のスイッチング素子の駆動信号を生成し、前記第２の同期整流要素のスイッチング素子の駆動信号は前記第１の同期整流要素のスイッチング素子の駆動信号の反転信号とすることを特徴とし、駆動信号生成部の簡素化を図ることができ、低コスト化、小型化ができるという効果がある。
【００９２】
請求項３の発明は、請求項１または２の発明において、前記電流検知部は、前記同期整流要素に直列に接続した電流検出用抵抗からなり、前記電流検出用抵抗の両端に発生する電圧に基づいて前記駆動信号生成部にて前記同期整流要素のスイッチング素子の駆動信号を生成することを特徴とし、簡単な回路構成で電流検知部を構成できるという効果がある。
【００９３】
請求項４の発明は、請求項３の発明において、前記電流検出用抵抗の抵抗値は、前記電流検出用抵抗に流れる電流に対して発生する前記電流検出用抵抗の両端の電圧が前記駆動信号生成部にて前記同期整流要素のスイッチング素子を駆動できる電圧にまで増幅できる最小の電圧になる抵抗値であることを特徴とし、電流検知部での損失を減らすことができるという効果がある。
【００９４】
請求項５の発明は、請求項１または２の発明において、前記電流検知部は、前記同期整流要素に直列に接続した１次コイル及び２次コイルとからなるカレントトランスと、前記カレントトランスの２次コイルの両端に並列に接続した抵抗と、前記抵抗の両端間の電圧を整流するために前記カレントトランスの２次コイルに直列に接続した整流ダイオードとから構成され、前記整流ダイオードから出力される前記電流検知部の出力に基づいて駆動信号生成部にて前記同期整流要素のスイッチング素子の駆動信号を生成することを特徴とし、２次側回路の整流損失を減らすことができるという効果がある。
【００９５】
請求項６の発明は、請求項１乃至５いづれかの発明において、前記駆動信号生成部は、前記電流検知部の出力と基準電圧とを比較し、前記比較結果に基づいて前記同期整流要素のスイッチング素子の駆動信号を生成することを特徴とし、２次側回路の整流損失を減らして、整流部の放熱板のサイズを小さくでき、回路全体の効率を上げることができるという効果がある。
【００９６】
請求項７の発明は、請求項１乃至６いづれか記載の発明において、前記第１及び第２の駆動信号生成部は、先に導通し整流を終了しつつある第１の同期整流要素を流れる電流値と、次の整流のために導通を行うべき第２の同期整流要素のダイオードに流れ始める電流値とが相等しくなる時刻における前記電流検知部の出力電圧と同じ電圧である基準電圧と、前記電流検知部の検出信号とを比較し、前記比較結果に基づいて前記同期整流要素のスイッチング素子の駆動信号を生成することを特徴とし、２次側回路の整流損失を減らして、整流部の放熱板のサイズを小さくでき、回路全体の効率を上げることができるという効果がある。
【００９７】
請求項８の発明は、請求項１乃至６いづれか記載の発明において、前記第２の駆動信号生成部は、先に導通し整流を終了しつつある第１の同期整流要素を流れる電流値と、次の整流のために導通を行うべき第２の同期整流要素のダイオードに流れ始める電流値とが相等しくなる時刻に、前記第２の同期整流要素のスイッチング素子をオンにできる電圧にまで増幅した駆動信号を出力することを特徴とし、２次側回路の整流損失を減らして、整流部の放熱板のサイズを小さくでき、回路全体の効率を上げることができるという効果がある。
【００９８】
請求項９の発明は、請求項１乃至８いづれか記載の発明において、前記インバータ部は、スイッチング素子を有するハーフブリッジのインバータからなり、前記スイッチング素子はゼロボルトスイッチングを行うことを特徴とし、２次側回路の整流損失を減らして、整流部の放熱板のサイズを小さくでき、回路全体の効率を上げることができるという効果がある。
【図面の簡単な説明】
【図１】 本発明の参考例１，９，１０の回路構成を示す図である。
【図２】 本発明の参考例１のＦＥＴに流れる電流波形を示す図である。
【図３】 本発明の参考例２の回路構成を示す図である。
【図４】 本発明の参考例２の回路動作を示す図である。
【図５】 本発明の参考例２のＦＥＴ素子のスイッチング動作を示す図である。
【図６】 本発明の参考例２の回路構成を示す図である。
【図７】 本発明の参考例３の回路構成を示す図である。
【図８】 本発明の参考例３の回路構成を示す図である。
【図９】 本発明の参考例４の回路構成を示す図である。
【図１０】 本発明の参考例５の回路構成を示す図である。
【図１１】 本発明の参考例６の回路構成を示す図である。
【図１２】 本発明の実施形態３、参考例７の回路構成を示す図である。
【図１３】 本発明の実施形態１，２、参考例８の回路構成を示す図である。
【図１４】 本発明の参考例８のスイッチング動作を示す図である。
【図１５】 本発明の実施形態２のスイッチング動作を示す図である。
【図１６】 本発明の実施形態３のスイッチング動作を示す図である。
【符号の説明】
Ａ 電源部
Ｂ インバータ部
Ｃ１ コンデンサ
Ｄ１ 寄生ダイオード
Ｅ１ 駆動信号生成部
Ｆ 平滑部
Ｇ１ １次側回路
Ｇ２ ２次側回路
Ｈ１ 電流検知部
Ｌ１ １次コイル
Ｌ２ ２次コイル
Ｐ１ ＦＥＴ素子
Ｑ１ ＦＥＴ
Ｔ１ トランス[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a non-contact power transmission device.
[0002]
[Prior art]
  Examples that have been put into practical use by applying non-contact power technology are charging applications such as shavers and electric toothbrushes, and are limited to low outputs of about several watts. A diode rectification method has been used as a rectification method for the secondary circuit.
[0003]
[Problems to be solved by the invention]
  Non-contact / contactless power transmission technology using magnetic induction with a separate detachable transformer can take a fundamental measure of electric shock due to its feature of no metal contact, so its use as a power source around water is drawing attention. . In order to use it as a safe and reliable power supply, the output voltage is low and the efficiency of the equipment does not decrease. The power supply of about 12V, which has already been proven in automobiles, and more than 50W can be used. Higher output is required. However, as the output is increased at a lower voltage, the output current increases, and the diode rectification method used in the secondary side circuit of the conventional contactless power supply device increases the rectification loss and increases the size of the heat sink such as a diode. As a result, there was a problem that it could not fit in a practical size.
[0004]
  Therefore, the application of the synchronous rectification technique, which has been conventionally used for reducing the loss of the rectification unit of the switching power supply whose output voltage is 5 V or less, to the non-contact power transmission device was examined. Synchronous rectification technology uses FET switching elements and FET parasitic diodes as switching elements for synchronous rectification, switches the FET switching elements according to the rectification cycle, and allows the rectified current to flow through the FET switching elements. In this technique, the loss of the rectification unit is reduced by utilizing the low on-resistance of the FET. Of course, the same operation is performed even if a diode in the reverse direction is connected in parallel to the switching element instead of the FET incorporating the parasitic diode.
[0005]
  The non-contact power transmission device outputs power received from a power source that supplies DC power, an inverter that converts DC power to high frequency power, a primary coil that is supplied with high frequency power from the inverter, and a primary coil Primary circuit composed of a primary coil of a separate detachable transformer that can be separated from the secondary coil to be separated, a secondary coil, a load matching capacitor connected in parallel to the secondary coil, and a secondary coil And a secondary side circuit composed of a rectifying unit for rectifying the output voltage of the output. At this time, in order to maximize the effective power that can be extracted to the secondary side to increase the efficiency of the entire circuit and to reduce the size of the separation / removable transformer, the leakage magnetic flux between the primary coil and the secondary coil of the separation / removable transformer The power factor of the entire circuit is improved by the leakage inductance caused by the above and the load matching capacitor connected in parallel to the secondary coil.
[0006]
  However, when load matching is performed by the load matching capacitor, the output waveform of the secondary coil is different from the output waveform of the secondary coil of the switching power supply and becomes a sine wave shape or a more distorted waveform. In the conventional drive signal generation method for the synchronous rectification switching element using the voltage or the auxiliary winding, since the on-time of the synchronous rectification switching element is short, the rectification efficiency is poor, and the efficiency cannot be increased as compared with the diode rectification method.
[0007]
  This invention is made | formed in view of the said reason, The objective is to provide the non-contact electric power transmission apparatus which raised the rectification efficiency of the secondary side circuit.
[0008]
[Means for Solving the Problems]
  The invention according to claim 1 is a power supply section that supplies a DC power supply, an inverter section that converts the DC power supply to a high-frequency power supply, a primary coil that is supplied with high-frequency power from the inverter section, and power that is received from the primary coil A secondary side circuit configured to be separable from the primary coil of the transformer, the secondary coil, a load matching capacitor connected in parallel to the secondary coil, and the Non-contact power having a secondary side circuit composed of a rectifying unit that rectifies the output voltage of the secondary coilTransmissionIn the deviceThe secondary coil of the transformer includes a center tap, and includes first and second synchronous rectification elements including a switching element and a diode reversely connected in parallel to the switching element, and the secondary coil of the transformer Full-wave rectification by connecting each other end not connected to the secondary coil of the transformer of the first and second synchronous rectification elements connected in series and in opposite directions to both output ends which are not center taps The current flowing through the first synchronous rectification element that has been conducted earlier and has finished rectification, and the rectification section that constitutes a section, a current detection section that detects a current flowing through the first and second synchronous rectification elements The switching element of the first synchronous rectification element is turned off at a time when the value and the current value starting to flow through the diode of the second synchronous rectification element to be conducted for the next rectification become equal to each other That has a first drive signal generator for outputting a driving signal, and a second drive signal generator for outputting a driving signal to turn on the switching elements of the second synchronous rectifierThe rectification loss of the secondary side circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.Further, full-wave rectification enables efficient rectification with less loss than half-wave rectification. Furthermore, the rectification loss of the secondary circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0009]
  The invention of claim 2 is the invention of claim 1,A drive signal for the switching element of the first synchronous rectification element is generated from a detection signal of the one current detection unit, and the drive signal for the switching element of the second synchronous rectification element is the switching signal of the first synchronous rectification element. It is characterized in that it is an inverted signal of the drive signal of the element, and the drive signal generation unit can be simplified, and the cost and size can be reduced.
[0010]
  The invention of claim 3 is the invention of claim 1 or 2,The current detection unit includes a current detection resistor connected in series to the synchronous rectification element, and the drive signal generation unit switches the switching element of the synchronous rectification element based on a voltage generated at both ends of the current detection resistor. The current detection unit can be configured with a simple circuit configuration.
[0011]
  The invention of claim 4 is the invention of claim 3,The resistance value of the current detection resistor is such that the voltage across the current detection resistor generated with respect to the current flowing through the current detection resistor can drive the switching element of the synchronous rectification element in the drive signal generation unit The resistance value is a minimum voltage that can be amplified to a voltage, and loss in the current detection unit can be reduced.
[0012]
  The invention of claim 5 is the invention of claim 1 or 2, whereinThe current detection unit includes a current transformer including a primary coil and a secondary coil connected in series to the synchronous rectification element, a resistor connected in parallel to both ends of the secondary coil of the current transformer, and both ends of the resistor A rectifier diode connected in series with a secondary coil of the current transformer to rectify the voltage between the current transformer and the drive signal generator based on the output of the current detector output from the rectifier diode. A drive signal for the switching element of the synchronous rectification element is generated, and the rectification loss of the secondary side circuit can be reduced.
[0013]
  The invention of claim 6 is the invention according to any one of claims 1 to 5,The drive signal generation unit compares the output of the current detection unit with a reference voltage, and generates a drive signal of the switching element of the synchronous rectification element based on the comparison result. The rectification loss can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0014]
  The invention of claim 7 is the invention according to any one of claims 1 to 6,The first and second drive signal generation units include a current value flowing through the first synchronous rectification element that has been turned on and has finished rectification, and a second synchronous rectification that should be turned on for the next rectification. A reference voltage that is the same voltage as the output voltage of the current detection unit at a time when current values that start to flow through the element diodes are equal to each other, and a detection signal of the current detection unit are compared, and based on the comparison result, A drive signal for the switching element of the synchronous rectification element is generated, and the rectification loss of the secondary circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0015]
  The invention according to claim 8 is the invention according to any one of claims 1 to 6,The second drive signal generation unit includes a current value flowing through the first synchronous rectification element that has been turned on and finished rectification, and a diode of the second synchronous rectification element that should be turned on for the next rectification. And output a drive signal amplified to a voltage that can turn on the switching element of the second synchronous rectification element at a time when the current value starting to flow is equal to each other. By reducing the size, the size of the heat sink of the rectifying unit can be reduced, and the efficiency of the entire circuit can be increased.
[0016]
  The invention of claim 9 is the invention according to any one of claims 1 to 8,The inverter part is composed of a half-bridge inverter having a switching element, and the switching element performs zero volt switching, and the rectification loss of the secondary side circuit can be reduced and the size of the heat sink of the rectification part can be reduced. The efficiency of the entire circuit can be increased.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
    (Reference example 1)
  Figure 1Reference example 1The circuit configuration of is shown. The power supply unit A, the inverter unit B, and the primary coil L1 of the transformer T1 constitute a primary side circuit G1, and the secondary coil L2 of the transformer T1, the load matching capacitor C1, and the FET Q1 constituting a synchronous rectification element and current detection The part H1, the drive signal generation part E1, and the smoothing part F constitute a secondary circuit G2.
[0019]
  The power supply unit A supplies DC power to the inverter unit B and is converted into high-frequency power by the inverter unit B, and the high-frequency power is supplied to the primary coil L1 of the transformer T1. The secondary coil L2 of the transformer T1 receives power from the primary coil L1 by electromagnetic coupling. The voltage across the secondary coil L2 is half-wave rectified by the FET Q1, and the half-wave rectified voltage is smoothed by the smoothing unit F. Output a DC voltage.
[0020]
  The primary coil L1 and the secondary coil L2 of the transformer T1 are separated from each other by a predetermined gap length by an insulator, and can be separated and detached.
[0021]
  The capacitor C1 connected in parallel with the secondary coil L2 is for load matching, and maximizes the effective power that can be extracted by the secondary side circuit G2 to increase the efficiency of power transmission from the primary side circuit G1 to the secondary side circuit G2. Raised.
[0022]
  Next bookReference exampleThe synchronous rectification operation will be described.
[0023]
  The FET Q1 includes an FET element P1 and a parasitic diode D1 connected in parallel to the FET element P1 in the reverse direction. The current detection unit H1 connected in series with the FET Q1 detects the current flowing through the FET Q1, and outputs the detection signal to the drive signal generation unit E1. The drive signal generation unit E1 outputs a drive signal for turning on the FET element P1 if the detection signal from the current detection unit H1 is equal to or greater than a predetermined threshold, and the signal from the current detection unit H1 is a predetermined threshold. If the value is less than the value, a drive signal for turning off the FET element P1 is output.
[0024]
  When the polarity of the electromotive force induced from the primary coil L1 to the secondary coil L2 by electromagnetic induction matches the forward direction of the parasitic diode D1 of the FET Q1, a forward current flows through the parasitic diode D1, and the forward current is When detected by the current detection unit H1, the drive signal generation unit E1 outputs an ON signal to the FET element P1 when the detection signal from the current detection unit H1 exceeds the threshold value, and the FET element P1 is turned on.
[0025]
  When the FET element P1 is turned on, the current initially flowing through the parasitic diode D1 flows in the direction from the source of the FET Q1 to the drain via the ON resistance of the FET element P1 because the resistance of the FET element P1 is smaller than that of the parasitic diode D1. At this time, if the ON time of the FET element is made as long as possible during the cycle in which the rectified current flows in the FET Q1, the loss in the FET Q1 can be reduced and the rectified loss can be reduced.
[0026]
  When the electromotive force induced from the primary coil L1 to the secondary coil L2 is changed by electromagnetic induction and the electromotive force induced in the secondary coil L2 is reduced, the detection signal output from the current detection unit H1 is also reduced. When the detection signal from the current detection unit H1 falls below the threshold value, the signal generation unit E1 outputs an off signal to the FET element P1, and the FET element P1 is turned off.
[0027]
  Further, when the polarity of the electromotive force induced in the secondary coil L2 is inverted, a reverse voltage is applied to the parasitic diode D1 of the FET element P1, so that the polarity of the electromotive force induced in the secondary coil L2 is inverted again. Until this time, no current flows through the parasitic diode D1, and the input of the smoothing section F has a half-wave rectified waveform. The half-wave rectified output is smoothed by the smoothing unit F.
[0028]
  Figure 2 shows the bookReference exampleA current waveform S1 flowing through the FET Q1 is shown, and the current waveform S1 has a gently rising and distorted waveform.
[0029]
  The loss at the time of synchronous rectification is the time t1 when the current waveform S1 exceeds the ON threshold value K of the FET element P1 and the FET element P1 is turned on, and the current waveform S1 is the ON threshold of the FET element P1. The time when the FET element P1 falls below the value K is t2 is OFF, the time when the current waveform S1 is 0 is t3, the ON resistance of the FET element P1 during the synchronous rectification is Ron, and the current flowing through the FET Q1 is I, Assuming that the forward voltage of the parasitic diode D1 is Vf, the total loss W in one cycle is expressed by the following formula 1.
[0030]
[Expression 1]

[0031]
  Thus, if the current flowing through the FET Q1 is detected and the FET element P1 is driven by a signal synchronized with the detection signal, the time during which the current flows through the parasitic diode D1 of the FET Q1 can be shortened, and the loss in the FET Q1 is reduced. Can be reduced. As a result, since the size of the heat sink can be reduced, the secondary circuit G2 can be reduced in size.
[0032]
    (Reference example 2)
  Figure 3Reference example 2The circuit configuration of is shown. The configuration and operation of the primary side circuit G1 including the power source A, the inverter B, and the primary coil L1 of the transformer T1 are as follows.Reference example 1Since it is the same as that, it is omitted.
[0033]
  The secondary coil L2 of the transformer T1 has a center tap system with three output terminals, and has three terminals, terminals 1 and 3 at both ends of the secondary coil L2 and a center tap terminal 2, and the secondary coil L2. A load matching capacitor C1 is connected between the terminal 1 and the terminal 3 in parallel. The drain of the FET Q1 constituting the synchronous rectification element is connected in series to the terminal 1 of the secondary coil L2 via the current detection unit H1, and the synchronous rectification element is connected in series to the terminal 3 of the secondary coil L2 via the current detection unit H3. Is connected to the drain of the FET Q2. The sources of the FETs Q1 and Q2 are connected to each other and connected to the negative side of the smoothing capacitor C8, and the terminal 3 of the secondary coil L2 is connected to the positive side of the smoothing capacitor C8 via the choke coil L3.
[0034]
  Then bookReference exampleWill be described. The FET Q1 includes an FET element P1 and a parasitic diode D1 connected in parallel to the FET element P1 in the reverse direction. The current detection unit H1 connected in series with the FET Q1 detects the current flowing through the FET Q1, and outputs the detection signal to the drive signal generation unit E1. The drive signal generation unit E1 outputs a drive signal for turning on the FET element P1 if the detection signal from the current detection unit H1 is equal to or greater than a predetermined threshold, and the signal from the current detection unit H1 is a predetermined threshold. If the value is less than the value, a drive signal for turning off the FET element P1 is output.
[0035]
  Similarly, the FET Q2 includes an FET element P2 and a parasitic diode D2 connected in parallel to the FET element P2 in the reverse direction. The current detection unit H2 connected in series to the FET Q2 detects the current flowing through the FET Q2, and outputs the detection signal to the drive signal generation unit E2. The drive signal generation unit E2 outputs a drive signal for turning on the FET element P2 if the detection signal from the current detection unit H2 is equal to or greater than a predetermined threshold, and the signal from the current detection unit H2 is a predetermined threshold. If it is less than the value, a drive signal for turning off the FET element P2 is output.
[0036]
  When the polarity of the electromotive force induced between the primary coil L1 and the terminal 2-1 of the secondary coil L2 by electromagnetic induction matches the forward direction of the parasitic diode D1 of the FET Q1, a forward current flows through the parasitic diode D1, The forward current is detected by the current detection unit H1, and the drive signal generation unit E1 outputs an ON signal to the FET element P1 when the detection signal of the current detection unit H1 exceeds the threshold value, and the FET element P1 is turned on. To do.
When the FET element P1 is turned on, the current initially flowing through the parasitic diode D1 flows in the direction from the source of the FET Q1 to the drain via the on-resistance of the FET element P1 because the resistance of the FET element P1 is smaller than that of the parasitic diode D1. At this time,Reference example 1Similarly, the loss in the FET Q1 can be reduced and the rectification loss can be reduced by increasing the ON time of the FET element as much as possible during the cycle in which the rectification current flows in the FET Q1.
[0037]
  When the electromotive force induced from the primary coil L1 to the secondary coil L2 is changed by electromagnetic induction and the electromotive force induced in the secondary coil L2 is reduced, the detection signal output from the current detection unit H1 is also reduced. When the detection signal from the current detection unit H1 falls below the threshold value, the signal generation unit E1 outputs an off signal to the FET element P1, and the FET element P1 is turned off.
[0038]
  Further, when the polarity of the electromotive force induced in the secondary coil L2 is reversed, a reverse voltage is applied to the parasitic diode D1 of the FET element P1, so that the polarity of the electromotive force induced in the secondary coil L2 is reversed again. No current flows through the parasitic diode D1.
[0039]
  On the other hand, since the polarity of the electromotive force induced between the primary coil L1 and the terminal 2-3 of the secondary coil L2 by electromagnetic induction coincides with the forward direction of the parasitic diode D2 of the FET Q2, the parasitic diode D2 A forward current flows through the FET Q2, the FET element P2, the parasitic diode D2, the current detection unit H2, and the drive signal generation unit E2. The FET Q1, the FET element P1, the parasitic diode D1, the current detection unit H1, and the drive signal generation unit E1 The same operation is performed.
[0040]
  By repeating the above operation, a full-wave rectified voltage is generated between the sources of the FETs Q1 and Q2 and the terminal 2 of the secondary coil L2, and is smoothed by the choke coil L3 and the smoothing capacitor C8.
[0041]
  FIG. 4 shows an induced electromotive force waveform S2 between the terminals 1-3 of the secondary coil L2, a current waveform S3 flowing through the secondary coil L2, and an ON threshold value K of the FETs Q1 and Q2. Due to the influence of the load matching capacitor C1, the current waveform S3 of the secondary coil L2 becomes a distorted waveform, and the voltage waveform S2 induced between the terminals 1-3 of the secondary coil L2 sandwiches a section where the constant section is 0V. The waveform vibrates positively and negatively. For this reason, in the conventional FET driving method using the auxiliary winding or the voltage between the secondary coils, when the on threshold value K of the FETs Q1 and Q2 is compared with the voltage waveform S2, the driving signal of the FET is as shown by the waveform S4. Therefore, the rectification efficiency does not increase because the time for turning on the FETs Q1 and Q2 is short.
[0042]
  However, as shown in FIG. 5, the current waveform S5 flowing through the FET Q1 is compared with the ON threshold value K of the FETs Q1 and Q2, and the current waveform S6 flowing through the FET Q2 is compared with the ON threshold value K of the FETs Q1 and Q2. Thus, the drive signals of the FETs Q1 and Q2 have waveforms S7 and S8, respectively, and the on-time of the FET elements P1 and P2 of the FETs Q1 and Q2 becomes longer than the waveform S4 of FIG. Therefore, the time during which the rectified current flows through the FET elements P1 and P2 becomes longer, and the rectification efficiency increases.
[0043]
  Also bookReference exampleA full-wave rectifier circuit using a transformer T1 in which the secondary coil shown in FIG.Reference example 1When the same output current is passed, the full-wave rectifier circuit can reduce the maximum value of the current passed through the FET as compared with the half-wave rectifier circuit. Since the loss when the FET elements P1 and P2 are turned on is proportional to the square of the current,Reference exampleThen, the current flowing through the FET elements P1 and P2 can be made smaller than that of the half-wave rectifier circuit, and the loss can be reduced.
[0044]
  As in the circuit configuration shown in FIG. 6, the load matching capacitor C1 is connected in parallel between the terminal 1 and the terminal 2 of the secondary coil L2, and the load matching capacitor C9 is connected to the terminal 2 of the secondary coil L2. The same effect as the load matching capacitor C1 of FIG. Further, the same effect can be obtained by connecting the capacitor C1 in parallel to the FET Q1 and connecting the capacitor C9 in parallel to the FET Q2.
[0045]
  In FIG. 1, the same effect can be obtained by connecting the load matching capacitor C1 in parallel to the FET Q1.
[0046]
    (Reference example 3)
  FIG.Reference example 3The power supply unit A that converts the AC power source to the DC power source, the inverter unit B that converts the DC input from the power source unit A to the high frequency power source, the control circuit J of the inverter unit B, and the inverter unit B The primary side circuit G1 is composed of the primary coil L1 of the transformer T1 to which power is supplied, a center tap type secondary coil L2 of the transformer T1, a load matching capacitor C1, current detection units H1 and H2, The drive signal generators E1 and E2, a secondary circuit G2 including FETs Q1 and Q2, a choke coil L3, and a smoothing capacitor C8.
[0047]
  The configuration and operation of the secondary side circuit G2 are as follows:Reference example 2Since it is the same as that of FIG. 3, description is abbreviate | omitted.
[0048]
  The configuration and operation of the primary side circuit G1 will be described. The power supply unit A is composed of an AC power supply Vs and a rectifier D3 for full-wave rectification of the AC power supply Vs, and the inverter unit B is a series circuit of capacitors C2 and C3 connected in parallel to the output terminal of the rectifier D3, and a rectifier D3. And a half-bridge inverter circuit comprising a series circuit of switching elements Q3 and Q4 connected in parallel to the output terminals of the capacitors and capacitors C4 and C5 connected in parallel to the switching elements Q3 and Q4, respectively. An electronic circuit for controlling the switching operation of the switching elements Q3 and Q4 is configured. One end of the primary coil L1 of the transformer T1 is connected to the midpoint of the capacitors C1 and C2, and the other end is connected to the switching elements Q1 and Q2. Connected to a point.
[0049]
  The voltage that has been full-wave rectified by the rectifier D3 is divided by the capacitors C2 and C3, and the switching elements Q3 and Q4 are alternately turned on and off by a drive signal having a certain dead time from the control circuit J to turn on and off the primary coil. A high frequency voltage is applied to L1.
[0050]
  Further, the capacitors C4 and C5 connected in parallel to the switching elements Q3 and Q4 can make the switching operation of the switching elements Q3 and Q4 a zero voltage switching operation, thereby reducing the switching loss in the switching elements Q3 and Q4. be able to.
[0051]
  Further, since the drive signals of the switching elements Q3 and Q4 have a certain dead time, the voltage between the terminal 1 and the terminal 3 of the secondary coil L2 of the transformer T1 is as shown by the waveform S2 in FIG.Reference example 2As in the case of synchronous rectification by FETs Q1 and Q2 with the drive signal generated from the detection signals of the current detection circuits H1 and H2,Reference example 2Similarly, the rectification loss of the secondary side circuit G2 can be reduced.
[0052]
  Further, when the capacitor C4 is connected in parallel to the primary coil L1 of the transformer T1 as in the circuit configuration shown in FIG. 8, zero voltage switching can be performed as in the circuit of FIG. Except for the above, the configuration and operation of the circuit of FIG. 8 are the same as the configuration and operation of the circuit of FIG.
[0053]
  Book like thisReference exampleAccording to this, it is possible to reduce the loss not only in the secondary side circuit G2 but also in the primary side circuit G1, increase the efficiency of the entire circuit, and reduce the size of the entire circuit.
[0054]
    (Reference example 4)
  Figure 9Reference example 4The circuit configuration of is shown. Basic circuit configuration and operationReference example 37 differs from the circuit configuration shown in FIG. 7 in that a signal obtained by inverting the drive signal of the drive signal generation unit E1 of the FET element P1 through the inverter INV1 is used as the drive signal of the FET element P2. For circuit configurations and operations other than those described aboveReference example 3Since this is the same as FIG.
[0055]
  As shown in the circuit configuration diagram of FIG. 9, in the synchronous rectifier circuit using the center tap method for the secondary coil L2 of the transformer T1, the drive signals of the FETs Q1 and Q2 are controlled so that current flows alternately to the FETs Q1 and Q2. Therefore, each drive signal of the FETs Q1 and Q2 is an inverted signal of one drive signal. Therefore, by driving the FET Q2 using the signal obtained by inverting the drive signal of the drive signal generation unit E1 of the FET Q1 via the inverter INV1 as the drive signal of the FET Q2, the drive circuit of the FET Q2 can be simplified. Cost and size can be reduced.
[0056]
  In addition, even when a forward method using synchronous rectification is adopted as the rectifier circuit of the secondary side circuit G2, the present invention can be similarly applied to two rectifier and commutation switching elements.
[0057]
    (Reference Example 5)
  FIG.Reference Example 5The circuit block diagram of is shown. Basic circuit configuration and operationReference example 3FIG. 10 differs from FIG. 7 in that the current detection units H1 and H2 in FIG. 7 are replaced with current detection units H3 and H4 including resistors R1 and R2 connected in series to the FETs Q1 and Q2, respectively. . For circuit configurations and operations other than those described aboveReference example 3Since this is the same as FIG.
[0058]
  BookReference exampleThen, voltages proportional to the currents flowing through the FETs Q1 and Q2 are generated at both ends of the resistors R1 and R2 respectively connected in series to the FETs Q1 and Q2. The voltages at both ends of the resistors R1 and R2 are input to drive signal generators E1 and E2, respectively. The drive signal generators E1 and E2 are FETs if the voltages at both ends of the resistors R1 and R2 are equal to or higher than a predetermined threshold value. A drive signal for turning on the elements P1 and P2 is output, and a drive signal for turning off the FET elements P1 and P2 is output if the voltage across the resistors R1 and R2 is equal to or lower than a predetermined threshold value.
[0059]
  Book like thisReference exampleCan detect the currents of the FETs Q1 and Q2 by a simple method and generate the drive signals of the FETs Q1 and Q2 using the detection signal.Reference example 2Similarly, the rectification loss can be reduced by turning on the FET elements P1 and P2 for as long as possible during each rectification cycle in which current flows in the FETs Q1 and Q2.
[0060]
    (Reference Example 6)
  Figure 11 is a bookReference Example 6Shows the circuit configuration diagram of the basic circuit configuration and operationReference Example 5In FIG. 11, the resistors R1 and R2 in FIG. 10 are replaced with current detectors H5 and H6 each having resistors R3 and R4 each having a minute resistance value (for example, 10 mΩ), and the drive signal generator E1 is replaced. , E2 is replaced with drive signal generation units E3, E4 each composed of operational amplifiers OP1, OP2. For circuit configurations and operations other than those described aboveReference Example 5Since this is the same as FIG.
[0061]
  BookReference exampleThen, by setting the resistance values of the resistors R3 and R4 connected in series to the FETs Q1 and Q2 to be very small (for example, 10 mΩ),Reference Example 5Compared to the above, the loss at the resistors R3 and R4 is reduced. However, by reducing the resistance values of the resistors R3 and R4, the voltages at both ends of the resistors R3 and R4 are also reduced. Therefore, the voltages at both ends of the resistors R3 and R4 are input to the inverting input terminal and the non-inverting input terminal of the operational amplifiers OP1 and OP2, respectively. Then, the operational amplifiers OP1 and OP2 differentially amplify the voltages at both ends of the resistors R3 and R4 to voltages that can sufficiently drive the FETs Q1 and Q2, and the outputs of the differentially amplified operational amplifiers OP1 and OP2 are applied to the FET elements P1 and P2. Let it be a drive signal.
[0062]
  Book like thisReference exampleThen, the loss in the current detection units H5 and H6 can be reduced.
[0063]
    (Reference Example 7)
  FIG.Reference Example 7The circuit block diagram of is shown. Basic circuit configuration and operationReference example 37 is substantially the same as FIG. 7, and in FIG. 12, the current detection units H1 and H2 of FIG. 7 are replaced with primary coils L4 and L5 and secondary coils L6 and L7, and current transformers CT1 and CT2 secondary coils L6 and L7. Resistors R5 and R6 are respectively connected in parallel, diodes D3 and D4 are respectively connected in series to the secondary coils L6 and L7, and capacitors C6 and C7 are connected in parallel to the resistors R5 and R6 via the diodes D3 and D4. Resistors R7 and R8 and constant voltage diodes ZD1 and ZD2 are replaced with current detection units H7 and H8, respectively, and drive signal generation units E1 and E2 of FIG. 7 are connected in series with diodes D3 and D4, respectively. The difference is that the drive signal generators E5 and E6 are made of AMP2. For circuit configurations and operations other than those described aboveReference example 3Since this is the same as FIG.
[0064]
  Currents flowing through the primary coils L4 and L5 of the current transformers CT1 and CT2 are detected by the secondary coils L6 and L7 of the current transformers CT1 and CT2, respectively, and voltages are generated at both ends of the resistors R5 and R6. Half-wave rectification is performed by diodes D3 and D4. Capacitors C6 and C7 are for noise cut. Resistors R7 and R8 discharge charges accumulated in the capacitors C6 and C7 to make the fall of the input signals of AMP1 and AMP2 steep. The constant voltage diodes ZD1 and ZD2 clamp the half-wave rectified voltage at a constant voltage so that a voltage exceeding the rated voltage of the amplifiers AMP1 and AMP2 is not input to the inputs of the amplifiers AMP1 and AMP2.
[0065]
  Since the FET coils P1 and P2 cannot be driven because the output currents of the secondary coils L6 and L7 of the current transformers CT1 and CT2 are small, they are amplified by the amplifiers AMP1 and AMP2, and the FETs Q1 and Q2 are driven by the amplified drive signals. To do.
[0066]
  Book like thisReference exampleCan detect the currents flowing through the FETs Q1 and Q2, and generate the drive signals for the FETs Q1 and Q2 using the detection signal.Reference example 2Similarly, the rectification loss can be reduced by turning on the FET elements P1 and P2 for as long as possible during each rectification cycle in which current flows in the FETs Q1 and Q2.
[0067]
    (Reference Example 8)
  Using the circuit configuration diagram of FIG.Reference Example 8Will be explained. Basic circuit configuration and operationReference Example 712. In FIG. 13, the amplifiers AMP1 and AMP2 of FIG. 12 are connected to comparators CP1 and CP2 and comparators CP1 and CP2 with reference voltage sources E1 and E2 connected to the inverting input terminals, respectively. The point of replacement is different. For circuit configurations and operations other than those described aboveReference Example 7Since this is the same as FIG.
[0068]
  In this reference example, the outputs of the secondary coils L6 and L7 of the current transformers CT1 and CT2 half-wave rectified by the diodes D3 and D4 are connected to the non-inverting input terminals of the comparators CP1 and CP2, respectively, and the reference voltage source E1 , E2 to the inverting input terminals of the comparators CP1 and CP2, respectively, and by appropriately setting the reference voltages of the reference voltage sources E1 and E2, as long as possible during each rectification cycle in which current flows in the FETs Q1 and Q2. The FET elements P1 and P2 can be turned on to reduce rectification loss.
[0069]
  Figure 14 shows the bookReference exampleShows the current waveform S9 flowing through the FET Q1, the reference voltage M1 of the reference voltage source E1, and the output waveform S10 of the comparator CP1. When the waveform S9 exceeds the reference voltage M1, the waveform S10 becomes H level, When the waveform S9 falls below the reference voltage M1, the waveform S10 becomes L level. Therefore, by appropriately setting the reference voltage M1, the section where the output waveform S10 of the comparator CP1 is at the H level can be widened. The same applies to the FET Q2.
[0070]
  That is, the rectification loss can be reduced by turning on the FET elements P1 and P2 for as long as possible during each rectification cycle in which current flows in the FETs Q1 and Q2.
[0071]
    (Embodiment 1)
  Using the circuit configuration diagram of FIG.Embodiment 1Will be explained. For basic circuit configuration and operationReference Example 8Since it is the same as that, it is omitted.
[0072]
  The current of the FET Q1 having the FET element P1 that has been turned on to perform synchronous rectification smoothly decreases in accordance with the induced electromotive force generated in the secondary coil L2 due to the load matching capacitor C6. . Similarly, the FET Q2 having the FET element P2 that is turned on to perform the next half-cycle synchronous rectification similarly starts to flow through the parasitic diode D2 before the current flowing through the FET Q1 becomes zero because of the capacitor C6. Therefore, the FET elements P1 and P2 may be turned on at the same time, and rectification may not be performed.
[0073]
  So this embodimentIn stateOutputs a drive signal from the comparator CP1 to turn off the FET element P1 that has been turned on until each current flowing through the FETs Q1 and Q2 becomes equal, and turns on the FET element P2 that has been turned off until then. A drive signal is output from the comparator CP2. Similarly, in the reverse half cycle, when the currents flowing through the FETs Q1 and Q2 become equal, a driving signal for turning off the FET element P2 that has been turned on is output from the comparator CP2, and has been turned off until then. A drive signal for turning on the FET element P1 is output from the comparator CP1.
[0074]
  In this way, this embodimentStateAccordingly, the FET elements P1 and P2 are not turned on at the same time, and the secondary side circuit G2 including the heat sink can be reduced in size by reducing the rectification loss.
[0075]
    (Embodiment 2)
  Using the circuit configuration diagram of FIG.Embodiment 2Will be explained. For basic circuit configuration and operationEmbodiment 1Since it is the same as that, it is omitted.
[0076]
  Embodiment 1As described above, when the currents flowing through the FETs Q1 and Q2 become equal, the comparator CP1 outputs a drive signal for turning off the FET element P1 that has been turned on, and the FET element P2 that has been turned off until then. A drive signal for turning on is output from the comparator CP2. Similarly, in the reverse half cycle, when the currents flowing through the FETs Q1 and Q2 become equal, a driving signal for turning off the FET element P2 that has been turned on is output from the comparator CP2, and has been turned off until then. If the driving signal for turning on the FET element P1 is output from the comparator CP1, the FET elements P1 and P2 are not turned on at the same time, and the rectification loss can be reduced.
[0077]
  Therefore, this embodimentIn state13 represents the output voltages obtained by half-wave rectifying the detection signals detected by the current transformers CT1 and CT2 with the diodes D3 and D4 in the circuit configuration of FIG. 13, that is, the output voltages of the constant voltage diodes ZD1 and ZD2, respectively. Reference voltage sources E1 and E2 having reference voltages as output voltages of constant voltage diodes ZD1 and ZD2 when input to the inverting input terminal and the currents flowing through the FETs Q1 and Q2 become equal are the inverting inputs of the comparators CP1 and CP2. By connecting each of the terminals to the input and using the outputs of the comparators CP1 and CP2 as drive signals for the FET elements P1 and P2, the FET elements P1 and P2 are not simultaneously turned on, reducing rectification loss and radiating heat. The secondary circuit G2 including the plate can be reduced in size.
[0078]
  FIG. 15 shows the present embodiment.StateCurrent waveform S11 flowing through FET Q1, reference voltage M2 of reference voltage source E1, output waveform S12 of comparator CP1, current waveform S13 flowing through FET Q2, reference voltage M3 of reference voltage source E2, output waveform S14 of comparator CP2 and Indicates. At time t4 when the magnitude of the current waveform S11 flowing through the FET Q1 is equal to the magnitude of the current waveform S13 flowing through the FET Q2, the output of the comparator CP1 is set to L, the FET element P1 is turned off, and the output of the comparator CP2 is set to H. By turning on the element P2, the FET elements P1 and P2 are not turned on at the same time, and the secondary side circuit G2 including the heat sink can be reduced in size by reducing the rectification loss.
[0079]
    (Embodiment 3)
  Using the circuit configuration diagram of FIG.Embodiment 3Will be explained. For basic circuit configuration and operationReference Example 7Since it is the same as that, it is omitted.
[0080]
  Embodiment 1As described in the above, when the currents flowing through the FETs Q1 and Q2 become equal, the driving signal for turning off the FET Q1 that has been turned on is output from the comparator CP1, and the FET Q2 that has been turned off is turned on. A drive signal is output from the comparator CP2. Similarly, in the reverse half cycle, when the currents flowing through the FETs Q1 and Q2 become equal, a driving signal for turning off the FET Q2 that has been turned on is output from the comparator CP2, and the FET Q1 that has been turned off until then is output. If the driving signal to be turned on is output from the comparator CP1, the FETs Q1 and Q2 are not turned on at the same time, and rectification loss can be reduced.
[0081]
  Therefore, this embodimentIn state12 is an output voltage obtained by half-wave rectifying the detection signals detected by the current transformers CT1 and CT2 with the diodes D3 and D4 when the currents flowing through the FETs Q1 and Q2 become equal in the circuit configuration of FIG. 12, that is, constant voltage diodes ZD1 and ZD2. The output voltages of the FETs P1 and P2 obtained by amplifying the output voltages of the amplifiers AMP1 and AMP2 respectively become voltages that can sufficiently turn on the FET elements P1 and P2, and the primary coil L4 and the secondary of the current transformer CT1. The winding ratio with the coil L6 and the winding ratio between the primary coil L5 and the secondary coil L7 of the current transformer CT2 are set.
[0082]
  FIG. 16 shows the present embodiment.StateDrive signal waveform S15 of FET element P1, current waveform S16 flowing through FET Q1, clamp voltage N1 of constant voltage diode ZD1, drive signal waveform S17 of FET element P2, current waveform S18 flowing through FET Q2, clamp voltage of constant voltage diode ZD2 N2 and a voltage K that can sufficiently turn on the FET elements P1 and P2. At time t5 when the magnitude of the current waveform S16 flowing through the FET Q1 is equal to the magnitude of the current waveform S18 flowing through the FET Q2, the drive signal waveform S15 of the FET element P1 drops below the voltage K that can sufficiently turn on the FET elements P1 and P2, and the FET element. P1 is turned off, and the drive signal waveform S17 of the FET element P2 exceeds the voltage K that can sufficiently turn on the FET elements P1 and P2, and the FET element P2 is turned on so that the FET elements P1 and P2 are not turned on at the same time. The secondary side circuit G2 including the heat sink can be reduced in size by reducing the rectification loss.
[0083]
  The waveforms S15 and S17 are clamped to the clamp voltages N1 and N2 of the constant voltage diodes ZD1 and ZD2.
[0084]
    (Reference Example 9)
  As shown in the circuit configuration diagram of FIG. 1, when half-wave rectification is performed using one synchronous rectification FET Q1, in order to reduce the rectification loss in FET Q1, as long as possible during the rectification cycle in which current flows in FET Q1. It is necessary to turn on the FET element P1 of the FET Q1.
[0085]
  The current detection unit H1 and the drive signal generation unit E1 in FIG. 1 are respectively replaced with the current detection unit H9 and the drive signal generation unit E7 in FIG. 13, and connected to the inverting input terminal of the comparator CP1 of the drive signal generation unit E7. By making the reference voltage of the reference voltage source E1 close to 0V, the comparator CP1 outputs a drive signal for turning on the FET element P1 for as long as possible during the rectification cycle, thereby reducing the rectification loss in the FET Q1. Thus, the secondary circuit G2 including the heat sink can be reduced in size.
[0086]
  For circuit configurations and operations other than the above,Reference Examples 1 and 8The explanation is omitted here.
[0087]
    (Reference Example 10)
  As shown in the circuit configuration diagram of FIG. 1, when half-wave rectification is performed using one synchronous rectification FET Q1, in order to reduce the rectification loss in FET Q1, as long as possible during the rectification cycle in which current flows in FET Q1. It is necessary to turn on the FET element P1 of the FET Q1.
[0088]
  The current detection unit H1 and the drive signal generation unit E1 in FIG. 1 are respectively replaced with the current detection unit H7 and the drive signal generation unit E5 in FIG. 12, and the primary coil L4 and the secondary coil of the current transformer CT1 of the current detection unit H7 are replaced. By increasing the turn ratio of the coil L5, even when the current flowing through the primary coil L4 of the current transformer CT1 is small, the induced voltage of the secondary coil L5 increases, and the drive signal that can turn on the FET element P1 of the FET Q1 is an amplifier AMP1. Is output from. Therefore, the rectifying element P1 is turned on as long as possible during the rectification cycle, and the secondary side circuit G2 including the heat sink can be reduced in size by reducing the rectification loss in the FET Q1.
[0089]
  For circuit configurations and operations other than the above,Reference Examples 1 and 7The explanation is omitted here.
[0090]
【The invention's effect】
  The invention according to claim 1 is a power supply section that supplies a DC power supply, an inverter section that converts the DC power supply to a high-frequency power supply, a primary coil that is supplied with high-frequency power from the inverter section, and power that is received from the primary coil A secondary side circuit configured to be separable from the primary coil of the transformer, the secondary coil, a load matching capacitor connected in parallel to the secondary coil, and the Non-contact power having a secondary side circuit composed of a rectifying unit that rectifies the output voltage of the secondary coilTransmissionIn the deviceThe secondary coil of the transformer includes a center tap, and includes first and second synchronous rectification elements including a switching element and a diode reversely connected in parallel to the switching element, and the secondary coil of the transformer Full-wave rectification by connecting each other end not connected to the secondary coil of the transformer of the first and second synchronous rectification elements connected in series and in opposite directions to both output ends which are not center taps The current flowing through the first synchronous rectification element that has been conducted earlier and has finished rectification, and the rectification section that constitutes a section, a current detection section that detects a current flowing through the first and second synchronous rectification elements The switching element of the first synchronous rectification element is turned off at a time when the value and the current value starting to flow through the diode of the second synchronous rectification element to be conducted for the next rectification become equal to each other That has a first drive signal generator for outputting a driving signal, and a second drive signal generator for outputting a driving signal to turn on the switching elements of the second synchronous rectifierThis is advantageous in that the rectification loss of the secondary circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.In addition, full-wave rectification has an effect of performing efficient rectification with less loss than half-wave rectification. Furthermore, there is an effect that the rectification loss of the secondary circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0091]
  The invention of claim 2 is the invention of claim 1,A drive signal for the switching element of the first synchronous rectification element is generated from a detection signal of the one current detection unit, and the drive signal for the switching element of the second synchronous rectification element is the switching signal of the first synchronous rectification element. It is characterized in that it is an inverted signal of the drive signal of the element, and it is possible to simplify the drive signal generation unit, and there is an effect that the cost can be reduced and the size can be reduced.
[0092]
  The invention of claim 3 is the invention of claim 1 or 2,The current detection unit includes a current detection resistor connected in series to the synchronous rectification element, and the drive signal generation unit switches the switching element of the synchronous rectification element based on a voltage generated at both ends of the current detection resistor. The driving signal is generated, and the current detection unit can be configured with a simple circuit configuration.
[0093]
  The invention of claim 4 is the invention of claim 3,The resistance value of the current detection resistor is such that the voltage across the current detection resistor generated with respect to the current flowing through the current detection resistor can drive the switching element of the synchronous rectification element in the drive signal generation unit The resistance value is a minimum voltage that can be amplified to a voltage, and there is an effect that the loss in the current detection unit can be reduced.
[0094]
  The invention of claim 5 is the invention of claim 1 or 2, whereinThe current detection unit includes a current transformer including a primary coil and a secondary coil connected in series to the synchronous rectification element, a resistor connected in parallel to both ends of the secondary coil of the current transformer, and both ends of the resistor A rectifier diode connected in series with a secondary coil of the current transformer to rectify the voltage between the current transformer and the drive signal generator based on the output of the current detector output from the rectifier diode. A drive signal for the switching element of the synchronous rectification element is generated, and the rectification loss of the secondary side circuit can be reduced.
[0095]
  The invention of claim 6 is the invention according to any one of claims 1 to 5,The drive signal generation unit compares the output of the current detection unit with a reference voltage, and generates a drive signal of the switching element of the synchronous rectification element based on the comparison result. There is an effect that the rectification loss can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0096]
  The invention of claim 7 is the invention according to any one of claims 1 to 6,The first and second drive signal generation units include a current value flowing through the first synchronous rectification element that has been turned on and has finished rectification, and a second synchronous rectification that should be turned on for the next rectification. A reference voltage that is the same voltage as the output voltage of the current detection unit at a time when the current values that start to flow through the element diodes are equal to each other, and a detection signal of the current detection unit are compared, and based on the comparison result, It is characterized in that it generates a drive signal for the switching element of the synchronous rectifying element, reduces the rectification loss of the secondary side circuit, reduces the size of the heat sink of the rectifying unit, and increases the efficiency of the entire circuit There is.
[0097]
  The invention of claim 8 is the invention according to any one of claims 1 to 6,The second drive signal generation unit includes a current value flowing through the first synchronous rectification element that has been turned on and finished rectification, and a diode of the second synchronous rectification element that should be turned on for the next rectification. And output a drive signal amplified to a voltage that can turn on the switching element of the second synchronous rectification element at a time when the current value starting to flow is equal to each other. This reduces the size of the radiating plate of the rectifying unit, and can increase the efficiency of the entire circuit.
[0098]
  The invention of claim 9 is the invention according to any one of claims 1 to 8,The inverter part is composed of a half-bridge inverter having a switching element, and the switching element performs zero volt switching, and the rectification loss of the secondary side circuit can be reduced and the size of the heat sink of the rectification part can be reduced. There is an effect that the efficiency of the entire circuit can be increased.
[Brief description of the drawings]
FIG. 1 of the present inventionReference examples 1, 9, 10FIG.
FIG. 2 of the present inventionReference example 1It is a figure which shows the current waveform which flows into FET of this.
FIG. 3 of the present inventionReference example 2FIG.
FIG. 4 of the present inventionReference example 2FIG.
FIG. 5 shows the present invention.Reference example 2It is a figure which shows the switching operation | movement of FET element.
FIG. 6 of the present inventionReference example 2FIG.
[Fig. 7] of the present invention.Reference example 3FIG.
[Fig. 8] of the present inventionReference example 3FIG.
FIG. 9 shows the present invention.Reference example 4FIG.
FIG. 10 shows the present invention.Reference Example 5FIG.
FIG. 11 shows the present invention.Reference Example 6FIG.
FIG. 12 shows the present invention.Embodiment 3, Reference Example 7FIG.
FIG. 13 shows the present invention.Embodiments 1 and 2, Reference Example 8FIG.
FIG. 14 shows the present invention.Reference Example 8It is a figure which shows the switching operation | movement of.
FIG. 15 shows the present invention.Embodiment 2It is a figure which shows the switching operation | movement of.
FIG. 16 shows the present invention.Embodiment 3It is a figure which shows no switching operation.
[Explanation of symbols]
  A Power supply
  B Inverter part
  C1 capacitor
  D1 Parasitic diode
  E1 Drive signal generator
  F Smoothing part
  G1 Primary side circuit
  G2 secondary circuit
  H1 Current detector
  L1 primary coil
  L2 secondary coil
  P1 FET element
  Q1 FET
  T1 transformer

Claims (9)

A power supply unit that supplies a DC power supply, an inverter unit that converts the DC power supply to a high-frequency power source, a primary coil that is supplied with high-frequency power from the inverter unit, and a secondary coil that outputs the power received from the primary coil; A primary circuit composed of the primary coil of the separable transformer, the secondary coil, a load matching capacitor connected in parallel to the secondary coil, and an output voltage of the secondary coil. In a non-contact power transmission device having a secondary circuit composed of a rectifying unit that rectifies,
The secondary coil of the transformer includes a center tap,
The first and second synchronous rectifying elements, each of which includes a switching element and a diode reversely connected in parallel to the switching element, are connected in series to both output ends that are not center taps of the secondary coil of the transformer, and to each other. The rectification unit configured by connecting the other ends not connected to the secondary coil of the transformer of the first and second synchronous rectification elements connected in the reverse direction to form a full-wave rectification unit;
A current detection unit for detecting a current flowing through the first and second synchronous rectification elements;
The current value that flows through the first synchronous rectification element that has been turned on first and ends rectification, and the current value that starts to flow through the diode of the second synchronous rectification element that should be turned on for the next rectification A drive signal generating section for outputting a drive signal for turning off the switching element of the first synchronous rectification element, and a drive signal for turning on the switching element of the second synchronous rectification element at the same time; A non-contact power transmission device comprising: a second drive signal generation unit for outputting. A drive signal for the switching element of the first synchronous rectification element is generated from a detection signal of the one current detection unit, and the drive signal for the switching element of the second synchronous rectification element is the switching signal of the first synchronous rectification element. The non-contact power transmission device according to claim 1, wherein the non-contact power transmission device is an inverted signal of an element drive signal. The current detection unit includes a current detection resistor connected in series to the synchronous rectification element, and the drive signal generation unit switches the switching element of the synchronous rectification element based on a voltage generated at both ends of the current detection resistor. The non-contact power transmission device according to claim 1, wherein the driving signal is generated. The resistance value of the current detection resistor is such that the voltage across the current detection resistor generated with respect to the current flowing through the current detection resistor can drive the switching element of the synchronous rectification element in the drive signal generation unit The non-contact power transmission device according to claim 3, wherein the resistance value is a minimum voltage that can be amplified to a voltage. The current detection unit includes a current transformer including a primary coil and a secondary coil connected in series to the synchronous rectification element, a resistor connected in parallel to both ends of the secondary coil of the current transformer, and both ends of the resistor A rectifier diode connected in series with a secondary coil of the current transformer to rectify the voltage between the current transformer and the drive signal generator based on the output of the current detector output from the rectifier diode. The non-contact power transmission device according to claim 1, wherein a driving signal for the switching element of the synchronous rectification element is generated. 6. The drive signal generation unit compares the output of the current detection unit and a reference voltage, and generates a drive signal of a switching element of the synchronous rectification element based on the comparison result. The non-contact power transmission device described in any one. The first and second drive signal generation units include a current value flowing through the first synchronous rectification element that has been turned on and has finished rectification, and a second synchronous rectification that should be turned on for the next rectification. A reference voltage that is the same voltage as the output voltage of the current detection unit at a time when current values that start to flow through the element diodes are equal to each other, and a detection signal of the current detection unit are compared, and based on the comparison result, 7. The non-contact power transmission device according to claim 1, wherein a drive signal for the switching element of the synchronous rectification element is generated. The second drive signal generation unit includes a current value flowing through the first synchronous rectification element that has been turned on and finished rectification, and a diode of the second synchronous rectification element that should be turned on for the next rectification. 7. The drive signal amplified to a voltage at which the switching element of the second synchronous rectification element can be turned on is output at a time when the current value starting to flow is equal to each other. Non-contact power transmission device. The non-contact power transmission apparatus according to claim 1, wherein the inverter unit includes a half-bridge inverter having a switching element, and the switching element performs zero-volt switching.

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