JP3904888B2 - Display panel drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display panel driving circuit, and more particularly to a circuit for driving a display panel in which light emitting elements are arranged in a matrix.
[0002]
[Prior art]
A display panel is a device that displays light-emitting elements such as electroluminescence elements (EL elements) in a matrix and displays an image on a panel screen by passing a current through the elements. The light emitting element used for the display panel is represented by an equivalent circuit as shown in FIG. 5, and emits light with an intensity proportional to the current flowing through the diode portion.
[0003]
A display panel driver is a circuit that allows current to flow through light emitting elements arranged in a matrix. A column side (column) driver causes current to flow into the positive electrode (anode terminal) of the light emitting element, and the row side (low). ) Ground the negative electrode (cathode terminal) of the light emitting element and draw a current. When image data is input to the light emission control circuit, information on the columns and rows of the light emitting elements that emit light is transmitted to the drive circuit.
A schematic configuration of a conventional display device is shown in FIG. The display device shown in FIG. 1 includes a display panel 10, drive circuits 20 and 30 for driving the display panel 10, and a light emission control circuit 1. Each circuit block in the display device will be described with reference to FIG.
[0004]
Referring to the figure, the display panel 10 includes a cathode line (a line connected to a cathode terminal of a diode of a light emitting element) B serving as a first display line to an nth display line.₁~ B_nAnd these cathode rays B₁~ B_nM anode lines (lines connected to the anode terminal of the diode of the light emitting element) A₁~ A_mAnd are formed. These cathode rays B₁~ B_nAnd anode wire A₁~ A_mLight-emitting element E at the intersection with₁₁~ E_nmEach of the light emitting elements bears one pixel of the display panel 10.
[0005]
As shown in FIG. 7, the light emission control circuit 1 converts the input image data for one screen (n rows, m columns) into the light emitting element E.₁₁~ E_nmPixel data group D corresponding to each of₁₁~ D_mnThese are sequentially supplied to the anode line drive circuit 20 line by line. Here, for example, pixel data D₁₁~ D_1mIs a light emitting element E belonging to the first display line of the display panel 10.₁₁~ E_1mAre m data bit rows that specify whether or not to emit light, and emits light at a logic level “1” and does not emit light at a logic level “0”. Similarly, pixel data D_{twenty one}~ D_2mIs a light emitting element E belonging to the second display line._{twenty one}~ E_2m, Pixel data D₃₁~ D_3mIs a light emitting element E belonging to the third display line.₃₁~ E_3m, Pixel data D_n1~ D_nmIs a light emitting element E belonging to the nth display line._n1~ E_nmThese are m data bit rows that specify whether or not to emit light.
[0006]
Further, the light emission control circuit 1 supplies a cathode line selection control signal for sequentially scanning the first display line to the nth display line to the cathode line drive circuit 30 in synchronization with the pixel data supply timing for each row.
The anode line drive circuit 20 first extracts data bits designating light emission from m data bits in the pixel data group sent from the light emission control circuit 1. The anode lines belonging to the columns corresponding to the extracted data bits are designated as anode lines A.₁~ A_mA constant current source is connected to the selected anode line, and a predetermined pixel driving current is supplied.
[0007]
Cathode line drive circuit is cathode line B₁~ B_nThe display line selected by the cathode line selection control signal of the light emission control circuit is set to the ground potential, and a current is supplied from a constant current source connected to the anode line of the element to emit light. At this time, the diode of the light emitting element is forward-connected. At that time, the unselected cathode lines are connected to a high potential. At this time, the diode of the light emitting element is reversely connected.
A light emission driving current flows between the column connected to the constant current source by the anode line drive circuit 20 and the display line set to the ground potential by the cathode line drive circuit 30, and crosses the column and the display line. The light emitting element emits light with an intensity proportional to the light emission driving current amount. On the other hand, since no current flows between the display line connected to the high potential by the cathode line drive circuit 30 and the column connected to the constant current source, the light emitting elements crossing the column and the display line do not emit light. Remains.
[0008]
The above operation is the pixel data group D.₁₁~ D_1m,D _{twenty one} ~ D_2m... D_n1~ D_nmWhen implemented for each, a light emission pattern for one field corresponding to the input image data, that is, an image is sent on the screen of the display panel.
By the way, in recent years, in realizing a large screen of a display panel, the cathode ray B_i(I = 1 to n) and anode wire A_jThe number of (j = 1 to m) is increased and the screen is highly detailed. Therefore, cathode ray B_iAnd anode wire A_jAs the number increases, the circuit scale of the cathode line drive circuit 30 and the anode line drive circuit 20 also increases. At this time, when the drive circuits 20 and 30 are integrated into an IC, the yield is expected to be deteriorated as the chip area increases. Therefore, it is general to use a technique in which each of the cathode line drive circuit 30 and the anode line drive circuit 20 is configured by a plurality of chips.
[0009]
However, if the anode line drive circuit 20 is constituted by a plurality of chips, a variation in transistor characteristics in manufacturing results in a difference in the amount of light emission drive current to be supplied to the anode line between the IC chips. There is a problem if areas with different brightness are formed on the display panel.
A technique for solving this is described in Japanese Patent Laid-Open No. 2001-42827. The technique described in the publication will be described with reference to FIGS.
[0010]
In FIG. 8, the display panel 10 includes a cathode line (metal electrode) B that bears each of the first display line to the nth display line.₁~ B_nAnd these cathode rays B₁~ B_n2m anode wires (transparent electrodes) A arranged crossing each other₁~ A_2mIs formed. These cathode rays B₁~ B_nAnd anode wire A₁~ A_2mA light emitting element E having a structure as shown in FIG._1,1~ E_{n, 2m}Is formed. These light emitting elements E_1,1~ E_{n, 2m}Each bears one pixel as the display panel 10.
[0011]
As shown in FIG. 9, the light emission control circuit 1 supplies a scanning line selection control signal for sequentially scanning each of the first display line to the nth display line of the display panel 10 to the cathode line drive circuit 30. The cathode line drive circuit 30 converts the cathode line corresponding to the display line indicated by the scanning line selection control signal to the cathode line B of the display panel 10.₁~ B_nAre selectively grounded to the ground potential, and each of the other cathode lines has a predetermined high potential V._ccAre applied respectively.
[0012]
The light emission control circuit 1 converts the input image data for one screen (n rows, 2 m columns) into each pixel of the display panel 10, that is, the light emitting element E._1,1~ E_{n, 2m}Pixel data D corresponding to each_1,1~ D_{n, 2m}Are divided into those belonging to the first column to the m-th column and those belonging to the m + 1-th column to the second m-th column. At this time, pixel data D obtained by grouping the pixel data belonging to the first column to the m-th column for each display line._1,1~ D_{1, m}, D_2,1~ D_{2, m}, D_3,1~ D_{3, m}, ... and D_{n, 1}~ D_{n, m}As shown in FIG. 9, each of the first drive data GA_1-mAre sequentially supplied to the first anode line drive circuit 21. At the same time, the light emission control circuit 1 ′ has pixel data D obtained by grouping the pixel data belonging to the m + 1-th column to the second m-th column for each display line._{1, m + 1}~ D_1,2m, D_{2, m + 1}~ D_2,2m, D_{3, m + 1}~ D_3,2m, ... and D_{n, m + 1}~ D_{n, 2m}Each of the second drive data GB, as shown in FIG._1-mAre sequentially supplied to the second anode line drive circuit 22.
[0013]
These first drive data GA_1-mAnd second drive data GB_1-m9 are sequentially supplied to the first anode line drive circuit 21 and the second anode line drive circuit 22 in synchronization with the scanning line selection control signal, as shown in FIG. At this time, the first drive data group GA_1-mIs m data bits that specify whether or not light emission is to be performed for each of the m light emitting elements belonging to the first to m-th columns of each display line of the display panel 10. The second drive data group GB_1-mIs m data bits for designating whether or not light emission is to be performed for each of the m light emitting elements belonging to each of the (m + 1) -th column to the second m-th column of each display line of the display panel 10. For example, when such a data bit is a logical level “1”, light emission is performed, whereas when it is “0”, light emission is not performed.
[0014]
In short, in the above publication, an anode line drive circuit is composed of a plurality of chips, the first anode line drive circuit 21 as a master chip and the second anode line drive circuit 22 as a slave chip. Then, a bias current for driving the first anode line drive circuit 21 is passed to the bias circuit of the second anode line drive circuit 22 using a current mirror circuit, and the second anode line drive circuit 22 is driven by this current. With this configuration, both drive circuits 21 and 22 are driven with almost the same bias current, and therefore, between the IC chip of the first anode line drive circuit and the IC chip of the second anode line drive circuit. Thus, the difference in light emission drive current to be supplied to the anode line Aj can be reduced.
[0015]
FIG. 10 shows an internal configuration example of the first anode line drive circuit 21 and the second anode line drive circuit 22. In the figure, the first anode line drive circuit 21 includes an internal reference current bias circuit 211, a current mirror circuit 212, and a current DAC circuit 210.
The internal reference current bias circuit 211 has a reference voltage V_refIs applied to the positive input of the operational amplifier OP1 and its output is applied to the gate of the PMOS transistor MP_rAnd MP₀It is comprised including. PMOS transistor MP_rThe reference resistor R between the source and the ground_refIs connected, and this reference resistance R_refIs applied to the negative input of the operational amplifier OP1.
[0016]
On the other hand, PMOS transistor MP₀A current mirror circuit 212 is connected to the source of the current source between the current source and the ground. The current mirror circuit 212 includes a reference resistor R_refCurrent I corresponding to the current flowing through₀Flows in.
The current mirror circuit 212 is a mirror source NMOS transistor MN.₀And the mirrored NMOS transistor MN₁And the former is the current I₀, The current I₁Flows. Current output terminal I_outCurrent input terminal I of the second anode line drive circuit 22_inAnd the current I₁Is passed to the second anode line drive circuit 22.
[0017]
The current DAC circuit 210 has a bias voltage V_bias1And a digital-to-analog converter that operates in response to a light emission control signal given from the outside and outputs a light emitting element driving current.
The second anode line drive circuit 22 includes current mirror circuits 221 and 222 and a current DAC circuit 220. The current mirror circuit 221 includes a PMOS transistor MP as a mirror source.₁And mirrored PMOS transistor MP₂It consists of and. PMOS transistor MP₁Includes the current I described above.₁Current flows, and the corresponding current I₂PMOS transistor MP₂Flowing into.
[0018]
The current mirror circuit 222 includes a mirror-source NMOS transistor MN.₂And the mirrored NMOS transistor MN_ThreeIt consists of and. NMOS transistor MN₂Includes the current I described above.₂Current flows, and the corresponding current is applied to the NMOS transistor MN._ThreeFlowing into.
The current DAC circuit 220 has a bias voltage V_bias2And a digital-to-analog converter that operates in response to a light emission control signal given from the outside and outputs a light emitting element driving current.
[0019]
The transistor sizes in the first anode line drive circuit 21 and the second anode line drive circuit 22 are MN₀= MN₁= MN₂, MP₀= MP₁= MP₂It is.
The current DAC circuit 210 in the first anode line drive circuit 21 and the current DAC circuit 220 in the second anode line drive circuit 22 have a mirror source NMOS transistor MN, respectively.₀, MN₂Bias voltage V determined by_bias1, V_bias2Are received by the gate of an NMOS transistor (not shown) in the current DAC circuit.
[0020]
With this configuration, it is considered that even when the anode line drive circuit is configured by a plurality of IC chips, the light emission luminance on the display panel can be made uniform.
[0021]
[Problems to be solved by the invention]
In the prior art described above, a bias current is passed using a current mirror circuit. In this current mirror circuit, a systematic current value deviation caused by a deviation in drain voltage between a mirror source transistor and a mirrored transistor, transistor size and V_onRandom current value variation determined by
[0022]
FIG. 11 shows the drain current characteristics with respect to the drain voltage. In the transistor, the drain voltage V_dsAs the rise of the drain current I_dsIs saturated, the drain current I_dsIs the drain voltage V_dsShould no longer depend on That is, the drain current I_ds-Drain voltage V_dsThe characteristic should be like the ideal characteristic S1 originally shown by a solid line in FIG.
However, in reality, it does not become flat, and has a drain voltage dependency of the slope λ as shown by the actual characteristic S2 indicated by a broken line in FIG. Therefore, the drain voltage V of the mirror source transistor_ds1And the drain voltage V of the mirrored transistor_ds2Varies depending on the effect of the slope λ, and as a result, the drain current slightly deviates. This drain current difference ΔI_dsTherefore, a systematic current value deviation occurs in the current mirror circuit.
[0023]
In addition, the difference between the bias current output from the master chip side and the bias current received on the slave chip side increases according to the number of current mirrors. That is, as shown in FIG. 12, a current difference d appears in the light emitting element driving currents of the master chip and the slave chip output through the current DAC circuit with respect to the position in the anode line channel direction. End up. This current difference d is a current difference due to a current mirror propagation shift.
[0024]
In an actual circuit, the threshold voltage V inside the chip_thDue to this tendency and a gate voltage drop due to a long gate wiring, the slopes as shown in FIG. 13 occur in the light emitting element drive currents of the master chip and the slave chip. That is, as shown in the figure, the solid line J in the figure_mMaster chip output and solid line J_sIn addition to the current difference d in FIG. 12, current differences d1 and d2 due to the slope of the output current are generated between the slave chip outputs indicated by. That is, in addition to the systematic current shift due to the current mirror, a systematic current shift due to the slope of the output current further occurs. Therefore, as a result, there is a drawback that the light emission luminance between adjacent IC chips is not uniform.
[0025]
The present invention has been made to solve the above-described drawbacks of the prior art, and its purpose is to accurately reproduce the light emission drive current level of the master chip with the light emission drive current output level of the slave chip, and between adjacent IC chips. It is an object to provide a display panel driving circuit capable of uniforming the light emission luminance.
[0026]
[Means for Solving the Problems]
  A display panel driving circuit according to a first aspect of the present invention includes a first and a second IC chip, and drives a plurality of pixel elements constituting the display panel with a driving output group of the first and second IC chips. The display panel driving circuit is provided to the first and second driving line groups for the first IC chip and the second IC chip, the first driving line group and the second driving line. Drive lines that make up a groupIn the middle ofEach has a dummy drive output,Of the first IC chipDummy drive outputIs input to the second IC chip, and the dummy drive output of the second IC chip is the dummy drive output of the first IC chip.To be the sameSystemIt includes control means for controlling. By doing so, the light emission drive current level of the master chip can be reproduced with high accuracy at the light emission drive current output level of the slave chip, and the light emission luminance between adjacent IC chips can be made uniform.
[0027]
  A display panel drive circuit according to a second aspect of the present invention is the display panel drive circuit according to the first aspect, wherein the control means includes a comparison circuit that compares the dummy drive outputs with each other and outputs a difference between the dummy drive outputs. SaidOf the second IC chipDummy driving outPowerIt is characterized by controlling. In this way, a feedback circuit is formed so that dummy drive outputs are the same, and as a result, the light emission luminance between adjacent IC chips can be made uniform.
[0030]
In short, in the present invention, among the systematic current value deviation and random current value variation, in order to eliminate the systematic current value deviation of the current mirror and the systematic current value deviation due to the slope of the gate voltage inside the chip, The bias current level is controlled according to the comparison result between the dummy drive outputs. Thereby, the light emission drive current level of the master chip can be reproduced with high accuracy at the light emission drive current output level of the slave chip. Therefore, the light emission luminance between adjacent IC chips can be made uniform, and the image quality of the display panel can be improved.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In each drawing referred to in the following description, the same reference numerals are given to the same parts as in the other drawings.
Example 1
FIG. 1 is a block diagram showing a first embodiment of a display panel driving circuit according to the present invention. As shown in the figure, the display panel driving circuit according to the present embodiment includes a first anode which is a first IC chip and a second IC chip that operate by applying a reference current as a reference output from one to the other. A line drive circuit 21 and a second anode line drive circuit 22 are included. The drive output groups of the drive circuits 21 and 22 are given to the first and second drive line groups for driving a plurality of pixel elements constituting the display panel.
[0032]
In this circuit, a reference current I which is a drive output of a dummy channel dch not corresponding to the drive lines constituting the first and second drive line groups._refAre derived from the first and second IC chips, respectively, and the level of the reference current is controlled according to the comparison result between these dummy drive outputs. That is, this embodiment has a circuit configuration that reproduces the light emission drive current output of the dummy channel inside the slave chip with high accuracy for the light emission drive current of the dummy channel inside the master chip.
[0033]
As shown in FIG. 1, when the anode line drive circuit (column driver) is constituted by a plurality of IC chips, dummy output channels are respectively installed in the adjacent master chip and slave chip.
The output channel here means that the anode line is A in FIG.₁~ A_mIf so, there are longitudinal circuit arrays for driving m anode lines, and each circuit array is called a channel. The dummy channel is a drive circuit row for driving an anode line other than a prescribed anode line. However, in actuality, only the current is output for reference, and the anode line is not driven.
[0034]
In this example, the light emission drive current of the dummy output channel of the master chip is passed to the feedback circuit in the slave chip to be used as a reference current. By returning the light emission drive current of the dummy output channel of the slave chip to the feedback circuit in the slave chip, it is adjusted to be the same as the reference current. Therefore, the light emission drive current of the master chip can be accurately reproduced with the light emission drive current output of the slave chip. With the above method, a display driver circuit can be realized in which the light emission luminance between adjacent chips is made uniform (the image quality of the display panel is improved).
[0035]
A specific circuit configuration is shown in FIG. In the figure, a first anode line drive circuit 21 includes an internal reference current bias circuit 211 and an NMOS transistor MN.₀It is comprised including. PMOS transistor MP in internal reference current bias circuit 211₀The current flowing through the NMOS transistor MN₀Bias voltage V_bias1Is input to the current DAC circuit 210.
Current output terminal I_outCurrent input terminal I of the second anode line drive circuit 22_inAnd the reference current I which is the drive output of the dummy channel dch of the current DAC circuit 210._refIs passed to the second anode line drive circuit 22.
[0036]
The second anode line drive circuit 22 is provided with an operational amplifier OP2. This operational amplifier OP2 has a reference current I from the first anode line drive circuit 21._refSame current I as₁Is resistance R₁V generated by flowing through₁Is a positive input, and a reference current I which is a drive output of the dummy channel dch of the current DAC circuit 210_refSame current I as₂Is resistance R₂V generated by flowing through₂Is a negative input. For this reason, in the operational amplifier OP2, the voltage V₁And voltage V₂Are compared, and a voltage corresponding to the difference between the two is output. The differential voltage output from the operational amplifier OP2 is the PMOS transistor MP._ThreeGiven to. This PMOS transistor MP_ThreeCurrent I3 flowing through the NMOS transistor MN_FourBias voltage V_bias2Is input to the current DAC circuit 220. Therefore, the current DAC circuit 220, the operational amplifier OP2, and the transistor MP_ThreeAnd MN_FourThus, a feedback circuit as shown by an arrow Y is configured, and the drive outputs of the dummy channels dch are controlled to be at the same level. The transistor size is MN₀= MN_Four, MP₀= MP_ThreeIt is. The resistance value is R₁= R₂It is.
[0037]
In the feedback circuit, the widths of the comparison resistors R1 and R2 are large, and the relative variation in resistance value is very small. In addition, the input conversion offset variation of the amplification computing unit OP2 is very small. Therefore, in the following, it is assumed that there is no random current variation due to the input conversion offset of the resistance element of the feedback circuit and the arithmetic unit, and considering the systematic current value deviation,₁= V₂Resistance value R₁= R₂So I₁= I₂become. Feedback circuit allows current I₁And current I₂Are controlled to be equal to each other, so that the reference current I from the first anode line drive circuit 21 is controlled._refIs derived from the dummy channel dch of the current DAC circuit 220, and the output of the dummy channel dch is equal between the first anode line drive circuit 21 and the second anode line drive circuit 22.
[0038]
A description will be given of how the output current difference between adjacent chips can be improved by using this circuit system. If there is a systematic propagation shift of the mirror current taken up as a problem of the prior art and a slope of the output current inside the chip, the output current difference between adjacent chips becomes d1 in FIG.
On the other hand, the reference current of the dummy channel at the center of the master chip is input to the feedback circuit of the slave chip, and the output current of the dummy channel at the center of the slave chip is adjusted to match the reference current, so that the solid line J_mThe output current level at the center of the master chip characteristic indicated by_s12 coincides with the output current level at the center of the slave chip characteristic, and the output current difference between adjacent chips is as indicated by d2 in FIG. Therefore, significant improvement is expected.
[0039]
(Reference example)
  BookreferenceThe example employs a circuit configuration that accurately reproduces the light emission drive current of the adjacent dummy channel of the master chip and the light emission drive current output of the adjacent dummy channel of the slave chip. That is, when the anode line drive circuit (column driver) is constituted by a plurality of IC chips, a dummy output channel is provided at each end of the adjacent master chip and slave chip. That is, as shown in FIG. 3, channels for outputting dummy drive outputs are provided adjacent to each other.
[0040]
  In the circuit configuration shown in FIG. 1 described above, an output channel for deriving a dummy drive output is arranged at the center of each IC chip. In contrast, the bookreferenceIn the example, the difference is that a dummy output channel is arranged at the end of the chip where the IC chips face each other.
  BookreferenceAlso in the example, the light emission drive current of the dummy output channel of the master chip is passed to the feedback circuit in the slave chip, and used as a reference current. By returning the light emission drive current of the dummy output channel of the slave chip to the feedback circuit in the slave chip, it is adjusted to be the same as the reference current. Therefore, there is no difference between the light emission drive current at the master chip end and the light emission drive current output at the slave chip end between adjacent chips. By the above method, it is possible to realize a display driver circuit that makes the light emission luminance between adjacent chips more uniform (improves the image quality of the display panel).
[0041]
In FIG. 3, the transistor size is MN as in FIG.₀= MN_Four, MP₀= MP_ThreeAnd the resistance value is R₁= R₂It is. Also, by using a feedback circuit, I₁= I₂The features that become are the same as in the case of FIG.
How the output current difference between adjacent chips is improved by using this circuit configuration will be described with reference to FIG. In the figure, the output current difference between adjacent chips in the prior art is indicated by d1 as in the case of FIG. In this embodiment, the reference current of the dummy channel at the master chip end adjacent to the slave chip is input to the feedback circuit of the slave chip, and the output current of the dummy channel at the slave chip end adjacent to the master chip is input. Operates to match the reference current. In order to operate in this way, the broken line J in FIG._s2As shown, the slave chip characteristics are improved. Therefore, as shown in the figure, the output current level at the adjacent master chip end matches the output current level at the slave chip end, and the output current difference between adjacent chips can be eliminated.
[0042]
  In this case, the output current changes uniformly in the chip, but since there is no abrupt output current difference between adjacent chips, an area with different luminance is created on the display panel due to the difference in emission luminance. The problem does not occur. That is, in this embodiment, even when the light emission drive current has an inclination with respect to the channel direction, the light emission luminance between adjacent IC chips can be made uniform. As explained above,1'sBy using the circuit configuration according to the embodiment, the output current of the dummy channel of the slave chip can be made equal to the output current of the dummy channel of the master chip installed in a plurality of IC chips. For this reason, since the difference in the drive current amount of the light emitting element between adjacent chips is significantly reduced as compared with the conventional method, the light emission luminance on the display panel can be made uniform.
[0043]
Although the case where two IC chips are used has been described above, the present invention is not limited to this, and it is obvious that the present invention can be applied to a case where more IC chips are used. Even in this case, a dummy drive output that does not correspond to each drive line corresponding to the IC chip is provided, and the bias voltage level is controlled according to the comparison result between the dummy drive outputs, thereby driving the light emission of the master chip. The current level can be accurately reproduced with the light emission drive current output level of the slave chip. Therefore, the light emission luminance between adjacent IC chips can be made uniform, and the image quality of the display panel can be improved.
[0044]
Further, the case where the pixel element constituting the display panel is an EL element has been described above. However, it is obvious that the present invention can be applied to a case where the pixel element is other than that.
Furthermore, in the above embodiment, a control circuit for comparing dummy drive outputs is provided on the slave chip side, but may be provided on the master chip side. If it is provided in any of the chips, it is not necessary to provide a special circuit other than those IC chips, and the image quality of the display panel can be improved without increasing the mounting space.
[0045]
【The invention's effect】
As described above, according to the present invention, by controlling the bias voltage level according to the comparison result between dummy drive outputs provided in the IC chip, the light emission drive current level of one IC chip is set to the other IC chip. The light emission drive current output level can be reproduced with high accuracy, the light emission luminance between adjacent IC chips can be made uniform, and the image quality of the display panel can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a display panel driving circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an operation of the display panel drive circuit of FIG. 1;
[Fig. 3]referenceIt is a block diagram which shows the structure of the display panel drive circuit by an example.
4 is a diagram showing an operation of the display panel drive circuit of FIG. 3;
FIG. 5 is a diagram showing an equivalent circuit of a light emitting element used in a display panel.
FIG. 6 is a schematic configuration diagram of a general display device.
7 is a timing chart showing the operation of the display device of FIG.
FIG. 8 is a block diagram showing a configuration of a conventional display panel drive circuit.
9 is a timing chart showing the operation of the display panel drive circuit of FIG.
FIG. 10 is a block diagram showing an internal configuration of an anode line drive circuit in a conventional display panel drive circuit.
FIG. 11 is a diagram showing a drain current having a drain voltage dependency.
FIG. 12 is a diagram showing a current mirror propagation shift in a conventional display panel drive circuit.
FIG. 13 is a diagram showing a slope of output current inside an IC chip in a conventional display panel drive circuit.
[Explanation of symbols]
10 Display panel
20 Anode wire drive circuit
21 First anode line drive circuit
22 Second anode line drive circuit
30 Cathode line drive circuit
210, 220 Current DAC circuit
dch dummy channel
OP1, OP2 operational amplifier

Claims (2)

The drive output groups of the first and second IC chips including the first and second IC chips are given to the first and second drive line groups for driving a plurality of pixel elements constituting the display panel. A display panel drive circuit, wherein the first IC chip and the second IC chip are dummy drives located in the center of the drive lines constituting the first drive line group and the second drive line group. The first IC chip dummy drive output is input to the second IC chip, and the second IC chip dummy drive output is the dummy drive output of the first IC chip. display panel driving circuit, which comprises a control Gosuru control means so as to be identical to the output. Wherein said control means includes a comparator circuit for outputting the difference by comparing the drive outputs of the said dummy, to control the driving output of the dummy of the second IC chip in accordance with the output of the comparator circuit 2. The display panel driving circuit according to claim 1, wherein

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