JP3841254B2 - Three-phase neutral point clamp type PWM inverter device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power converter such as an inverter / servo drive that performs variable speed driving of a motor, and a power converter connected to a grid.
[0002]
[Prior art]
Conventionally, as a PWM pulse generation method of a three-phase neutral point clamp type PWM inverter device, as shown in Japanese Patent Laid-Open No. 5-146160, unipolar modulation / dipolar modulation for outputting a pulse by comparing an amplitude command with a carrier wave, etc. As disclosed in Japanese Patent Laid-Open No. 5-292754, there is a method for generating a PWM pulse by calculating the generation time of each vector using the concept of a space vector. FIG. 10 is a vector diagram illustrating an output voltage vector of a three-phase neutral point clamp type PWM inverter on a plane. The switch state where the phase output terminal of the three-phase neutral point clamp PWM inverter is connected to the positive bus is P, the switch state connected to the negative bus is N, the switch state connected to the neutral line is O, and the output Assuming that the phases are arranged in the order of UVW, the output voltage vector that can be taken by the three-phase neutral point clamp inverter takes 27 kinds of switch states as shown in FIG.
[0003]
Here, for convenience of explanation, 27 types of switch states that can be taken by the three-phase neutral point clamp type PWM inverter shown in FIG. 10 are represented by a zero vector PPP: Op.
OOO: Oo
NNN: On
x vector POO, OPO, OOP: xp
ONN, NON, NNO: xn
y vector PPO, OPP, POP: yp
ON, NOO, ONO: yn
z vector PON, OPN, NPO, NOP, ONP: z
a vector PNN, NPN, NNP: a
b vector PPN, NPP, PNP: b
And divided into groups
The area surrounded by the zero vector, the x vector, and the y vector is 1-1 to 6-1.
The area surrounded by the x vector, a vector, and z vector is 1-2 to 6-2.
The region surrounded by the x vector, y vector, and z vector is 1-3 to 6-3.
The area surrounded by the y vector, b vector, and z vector is 1-4 to 6-4.
Divide as follows.
In order for the three-phase neutral point clamp type PWM inverter to output a voltage vector A within the region shown in FIG. 10, the vector of the switch state closest to the tip of the voltage vector is used and the vectors are sequentially And an output voltage is obtained by performing pulse width modulation (PWM) so that the combined value of the vectors within a certain unit time is the same as the voltage vector A.
[0004]
[Problems to be solved by the invention]
In the three-phase neutral point clamp type PWM inverter, an even number of smoothing capacitors 3 and 4 are connected in series between the main circuit positive bus P and the negative bus N in order to generate a neutral point voltage as shown in FIG. In general, a neutral line is taken out from the terminal 0 of the capacitor, which is a voltage just between P and the negative bus N, and used. In FIG. 9, 1 is a three-phase AC power source, 2 is a rectifier diode bridge, 6 to 11 are clamp diodes, 12 to 23 are freewheeling diodes, 24 to 35 are IGBTs, 36 to 38 are current sensors, and 39 is a load motor. .
The neutral line 0 is connected as shown in FIGS. 7 and 8 according to the state of the PWM inverter output load (load motor 39) and the switch of the PWM inverter. The potential of the neutral line (neutral point potential) varies depending on the current from the load connected to the capacitor charged from the positive bus / negative bus.
In the switch state shown in FIG. 7, the line voltage output to the load is the same, but a set of switch states in which the phases of the load connected to the neutral line are different (the adjacent switch states in FIG. ) And the neutral point potential can be finely controlled by adjusting the time ratio at which this set of switch states is generated.
However, in the switch state shown in FIG. 8, the neutral point potential fluctuates depending on the phase current of the load connected to the neutral line and the time ratio at which this switch state is generated. Because it does not exist, the neutral point potential variation caused by the switch state of FIG. 8 must be corrected using the switch state of FIG.
[0005]
Therefore, conventionally, as shown in Japanese Patent Application Laid-Open No. 2-261063, a zero-phase voltage is added to the modulation rate, the generation time of the switch state of the set shown in FIG. Neutral point potential fluctuation is controlled without changing. In addition, the voltage vector to be output is also output by using the space vector method so that the set of switch states shown in FIG. 7 is used, and the neutral point potential is controlled by adjusting the generation time of the switch state of the set. It was.
In the three-phase neutral point clamp type PWM inverter, the neutral point potential fluctuation in the switch state of FIG. 8 is determined by the phase current of the load connected to the neutral line from FIG. When the phase current of the load connected to the neutral line (when the load power factor = 1) is shown in FIG. 11, the output voltage vector changes 120 degrees in the direction of the phase current 110 of the load connected to the neutral line. Since this is always reversed, the neutral point potential fluctuates at a frequency three times the output frequency due to this influence.
Further, when the modulation rate is considerably large, the generation time ratio of the switch state shown in FIG. 8 is larger than that in the switch state shown in FIG. 7, and in the overmodulation state where the modulation rate exceeds about 1.15, FIG. The occurrence time ratio of the switch state shown is completely zero, and there is a problem that the fluctuation of the neutral point potential caused by the switch state shown in FIG. 8 cannot be suppressed.
Therefore, the problem to be solved by the present invention is to suppress the neutral point potential fluctuation of the three-phase neutral point clamp type PWM inverter device and to adjust the neutral point potential at the time of overmodulation, which was impossible in the past. And to improve safety and output voltage quality.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, the present invention
(1) a positive bus, a negative bus, and a neutral wire, the first and second switch elements between the positive bus and the phase voltage output terminal, and between the negative bus and the phase output terminal, and The third and fourth switch elements are connected in series, and the connection points of the first and second switch elements and the connection points of the third and fourth switch elements are respectively connected via the clamp elements. In a three-phase neutral point clamp type PWM inverter provided with three phases of neutral point clamp type PWM inverters connected to a neutral line, the positive bus, the negative bus, and the neutral line are each in three phases The time of the three-phase output voltage that is in the six switch states connected to the phase output terminal is suppressed to the first set value or less, and the shortage of the output voltage due to being suppressed to the first set value or less Each of the three-phase phase output terminals is the front Of the eight switch states connected to the positive bus or the negative bus, the three phase output terminals of the three phases are supplemented by six switch states excluding the two switch states connected to the positive bus or the negative bus at the same time. This is a three-phase neutral point clamp PWM inverter device.
[0007]
(2) In the three-phase neutral point clamp PWM inverter device of (1), the six switch states that compensate for the shortage of the output voltage from the six switch states that are suppressed below the first set value. The three-phase neutral point clamp type PWM inverter device is characterized in that the switch state of only one phase of the neutral point clamp type PWM inverter is changed when shifting to the above.
(3) The three-phase neutral point clamp type PWM inverter device according to (1) or (2), wherein the first set value is changed according to a modulation factor value. A PWM inverter device is assumed.
(4) In the three-phase neutral point clamp PWM inverter device of (1) or (2), the first set value is changed depending on the direction of the current flowing through the neutral line or the phase of the output current. The three-phase neutral point clamp type PWM inverter device.
(5) The three-phase neutral point clamp PWM inverter device according to (1) or (2), wherein the first set value is changed in accordance with a voltage value of the neutral line. A neutral point clamp PWM inverter device is used.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
1 to 4 show an example of a PWM output pulse train of the present invention.
1 to 4, the PWM output cycle is 2 × T, the horizontal axis is time series, and pulses are output in order from left to right.
In the example shown in FIGS. 1 to 3, when the z vector is included in the three vectors close to the output voltage vector, the z vector can be moved by the change of the switch state of only one phase, and is close The a or b vector not included in the three vectors is also output.
1-3 to 6-3 region (FIG. 1)
Example 1: yp → b → z → yn → xn → a → z → xp → yp
1-2 to 6-2 region (FIG. 2)
Example 2: xp → z → b → z → a → xn, xn → a → z → b → z → xp
Example 3: b → z → xp → a → xn, xn → a → xp → z → b
1-4 to 6-4 region (FIG. 3)
Example 4: yp → b → z → a → z → yn, yn → z → a → b → yp
Example 5: yp → b → yn → z → a, a → z → yn → b → yp
Although not shown in the above example, the average value of the output voltage is the same as in the above example even in the reverse order of the above example (outputting PWM pulses in order from right to left).
[0009]
When the pulse train as described above is output, the generation time of each switch state is k (the inscribed circle radius of the hexagon in FIG. 10 is 1), and the angle a closest in angle. When the angle formed from the vector is θ, the period of the PWM output pulse is T, and the output time of the z vector is T2, the zero vector generation time (T0) is T0 = 0 in the 1-3 to 6-3 region.
The generation time (T1) of the x vector is T1 = T {1-2ksinθ}
The generation time (T2) of the z vector is T2 = T {2ksin (θ + π / 3) -1} or less and the generation time (T3) of an arbitrary value y vector of zero or more is T3 = T {1-2ksin (π / 3− θ)}
The a vector generation time (T4) is T4 = [T {2ksin (θ + π / 3) -1} -T2] / 2
The generation time (T5) of the b vector is T5 = [T {2ksin (θ '+ π / 3) -1} -T2] / 2
In the 1-2-2 range, the zero vector generation time (T0) is T0 = 0.
x vector generation time (T1) is T1 = T {1-ksin (θ + π / 3)}
The generation time (T2) of the z vector is T2 = 2Tksinθ or less and the generation time (T3) of an arbitrary value y vector of zero or more is T3 = 0
The a vector generation time (T4) is T4 = T (3 ^1/2 kcos θ-1) -T2 / 2
The generation time of the b vector (T5) is T5 = (2Tksinθ-T2) / 2
In the 1-4 to 6-4 region, the zero vector generation time (T0) is T0 = 0.
x vector generation time (T1) is T1 = 0
z vector generation time (T2) is T2 = 2Tksin (π / 3−θ) or less and zero or more arbitrary value y vector generation time (T3) is T3 = 2T {1-ksin (θ + π / 3)}
a vector generation time (T4) is T4 = {2ksin (π / 3−θ) −T2} / 2
b vector generation time (T5) is ^{T5 = T (3 1/2 kcos (} π / 3-θ) -1) -T2 / 2
It can be shown as follows.
[0010]
Furthermore, in the 1-3-3-6 region,
Example 6: yp → xp → z → a → xn → yn, yn → a → z → xp → yp
Example 7: xp → yp → b → z → yn → xn, xn → yn → z → b → yp → xp
And the pattern shown in FIG. 4 can be taken, and the occurrence time of each switch state in that case is
In the case of yp → xp → z → a → xn → yn, the zero vector generation time (T0) is T0 = 0
The generation time (T1) of the x vector is T1 = T {2−3ksinθ−3 ^1/2 kcosθ} + T2
The generation time (T2) of the z vector is T2 = {2ksin (θ + π / 3) −1} or less and the generation time (T3) of an arbitrary value y vector of zero or more is T3 = T {2ksinθ} −T2
a vector generation time (T4) is ^{T4 = T {3 1/2 kcosθ +} ksinθ-1} -T2
In the case of xp → yp → b → z → bn → xn, the generation time (T0) of the zero vector is T0 = 0
The generation time (T1) of the x vector is T1 = T {3 ^1/2 kcosθ−ksinθ} −T2
z vector generation time (T2) is T2 = {2ksin (θ + π / 3) −1} or less and zero or more arbitrary value y vector generation time (T3) is T3 = T {2−2 · 3 ^1/2 kcosθ } + T2
The generation time (T5) of the b vector is T5 = T {ksinθ + 3 ^1/2 kcosθ−1} −T2
It can be shown as follows.
[0011]
With the PWM output pulse train as described above, the z vector generation time (T2) shown in FIG. 8 can be determined to an arbitrary value equal to or greater than zero, and the neutral point potential by the z vector can be reduced by shortening T2. Fluctuation can be suppressed, and when the modulation rate is large (when the generation time of the x and y vectors is short), the generation time of the z vector for changing the neutral point potential can be shortened, so that the output frequency can be three times higher. Fluctuating neutral point potential fluctuations can be suppressed.
Also, with the PWM pulse train of the present invention as described above, only the switching state of only one phase changes at the time of the transition of the PWM pulse, so that the fluctuation range of the output line voltage is almost the same as the neutral point potential and the load Surge can be suppressed. The above PWM pulse train is an example, and there are pulse trains satisfying the characteristics of the present invention other than the above example.
FIG. 5 is a block diagram showing an example of the present invention. In the figure, 101 is a z vector generation time calculator 1, 102 is a z vector generation time upper limit setter, 103 is a PWM generation time calculator, 104 is each vector generation time setter, and 105 is a PWM pattern generator.
Since the generation time of the z vector varies greatly depending on the modulation rate, when the modulation rate is small and the generation time of the z vector is small, if the generation time of the z vector is further shortened, the z vector and the z vector are output. If the generation time of both a and b vectors is very small and the response of the switch element is slow, a correct pulse may not be output and the output voltage may be insufficient. Therefore, as shown in FIG. 5, a z vector generation time calculator 1 (101) for changing the set value of T2 according to the modulation rate is added, and the set value of T2 is optimized according to the modulation rate, z, The output voltage is not shorted by adjusting the generation of the a and b vectors so as not to be too short.
[0012]
FIG. 6 is a block diagram showing an example of the present invention. In the figure, reference numeral 106 denotes a z vector generation time calculator 2.
The direction of fluctuation of the neutral point potential when the z vector is generated is determined by the direction of the load current of the phase connected to the neutral line, and when the current flows into the neutral line, the neutral point potential increases, As the flow begins, the neutral point potential decreases.
The voltage vector modulation factor and phase and the direction of the phase current of the load connected to the neutral line are measured by current sensors 36, 37, and 38 shown in FIG. The time setting of T2 is calculated by the z vector generation time calculator 2 (106) according to the direction and neutral point potential control command.
[0013]
If the neutral point potential control command is (1) a command to increase the neutral point potential,
The z vector generation time ratio is increased when the current flows into the neutral line from the switch state and the phase current state, and the z vector generation time ratio is decreased otherwise.
(2) In the case of a command to lower the neutral point potential,
The z vector generation time ratio is increased when the current flows out of the neutral line from the switch state and the phase current state, and the z vector generation time ratio is decreased otherwise.
(3) In the case of a command for holding a neutral point potential, the z vector generation time ratio is set to a constant value.
As described above, the neutral point potential can be adjusted to a desired potential. In an overmodulation state in which the modulation rate exceeds 1, the generation time of the x and y vectors that can adjust the neutral point potential that has been used in the past is almost eliminated, and the neutral point potential cannot be adjusted. However, the neutral point potential can be adjusted even during overmodulation by adjusting the generation time of the z vector with the circuit configuration shown in FIG.
[0014]
【The invention's effect】
As described above, according to the present invention, the neutral point potential fluctuation of the three-phase neutral point clamp type PWM inverter device can be suppressed, and further, the neutral point potential at the time of overmodulation, which has been impossible in the past, can be adjusted. Thus, safety and output voltage quality can be improved.
[Brief description of the drawings]
FIG. 1 is a time chart showing an example of a PWM pulse pattern of the present invention.
FIG. 2 is a time chart showing an example of a PWM pulse pattern of the present invention.
FIG. 3 is a time chart showing an example of a PWM pulse pattern of the present invention.
FIG. 4 is a time chart showing an example of a PWM pulse pattern of the present invention.
FIG. 5 is a block diagram showing an example of a PWM pulse generation circuit of the present invention.
FIG. 6 is a block diagram showing an example of a PWM pulse generation circuit of the present invention.
FIG. 7 is an explanatory diagram showing a connection state with a load in a switch state 1 of a three-phase neutral point clamp type inverter.
FIG. 8 is an explanatory diagram showing a connection state with a load in a switch state 2 of a three-phase neutral point clamp type inverter;
FIG. 9 is a circuit configuration diagram of a three-phase neutral point clamp type inverter.
FIG. 10 is an output voltage space vector diagram of a three-phase neutral point clamp type inverter.
FIG. 11 is a diagram of current flowing through a neutral wire (load power factor = 1).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Three-phase alternating current power supply 2 Rectifier diode bridge 3, 4 Smoothing capacitor 6-11 Clamp diode 12-23 Freewheeling diode 24-35 IGBT
36 to 38 Current sensor 39 Load motor 101 z vector generation time calculator 1
102 z vector generation time upper limit setter 103 PWM generation time calculator 104 vector generation time setter 105 PWM pattern generator 106 z vector generation time calculator 2
107 U-phase current 108 V-phase current 109 W-phase current 110 Current flowing in the neutral line at the time of z vector output

Claims (5)

A positive bus line, a negative bus line, and a neutral line; first and second switch elements; and third and fourth terminals between the positive bus line and the phase voltage output terminal, and between the negative bus line and the phase output terminal, respectively. Are connected in series, and a connection point between the first and second switch elements and a connection point between the third and fourth switch elements are connected to the neutral line via a clamp element, respectively. In the three-phase neutral point clamp type PWM inverter provided with three neutral point clamp type PWM inverters,
The positive bus, the negative bus, and the neutral wire are suppressed to the first set value or less, and the time of the three-phase output voltage in which the six switch states are respectively connected to the three-phase phase output terminals, The shortage of the output voltage due to the suppression to the first set value or less is obtained by changing the three-phase output terminals from the eight switch states in which each of the phase output terminals is connected to the positive bus or the negative bus. A three-phase neutral point clamped PWM inverter device comprising six switch states excluding two switch states in which three phase output terminals are simultaneously connected to the positive bus or negative bus. 3. The three-phase neutral point clamp type PWM inverter device according to claim 1, wherein the six switch states that are suppressed to be equal to or lower than the first set value shift to the six switch states that compensate for the shortage of the output voltage. The three-phase neutral point clamp type PWM inverter device is characterized in that the switch state of only one phase of the neutral point clamp type PWM inverter changes. 3. The three-phase neutral point clamped PWM inverter device according to claim 1, wherein the first set value is changed according to a modulation factor value. 4. The three-phase neutral point clamp type PWM inverter device according to claim 1 or 2, wherein the first set value is changed according to a direction of a current flowing through a neutral line or a phase of an output current. Neutral point clamp type PWM inverter device. The three-phase neutral point clamp type PWM inverter device according to claim 1 or 2, wherein the first set value is changed according to a voltage value of the neutral line. PWM inverter device.

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