JP3827661B2 - Signal processing circuit of differential capacitive transducer - Google Patents

Description

  The present invention relates to a signal processing circuit of a differential capacitive transducer that is attached to a motor, an actuator, or the like and detects the amount of change in the rotation angle or linear direction with high accuracy.

The present applicant has proposed a rotary differential capacitive angle converter (Patent Document 1) using a differential capacitive transducer.
According to this proposal, the rotation angle can be detected with high accuracy without using a large-amplitude AC signal source or feedback control for temperature compensation. In the present invention, however, the detection accuracy is further improved. In addition, it is devised to eliminate the influence of noise and DC voltage offset generated in the signal processing circuit.

FIG. 7 shows a signal processing circuit of another conventional differential capacitance type transducer, and shows a block diagram of a circuit configuration provided with a feedback circuit.
The signal vs of the sine wave oscillator 27 is applied to the common electrode 2 of the differential capacitive transducer having two capacitances Ca and Cb, the other terminal of Ca is connected to the connection point of the diodes D1 and D2, and the other of Cb. Is connected to a connection point between the diodes D3 and D4. Thereby, the alternating currents ia and ib proportional to the capacitances Ca and Cb are directly half-wave rectified by the diodes D1, D2, D3, and D4. DC voltage signals Va and Vb are output by a secondary active low-pass filter 22 composed of an operational amplifier OP1, a resistor and a capacitor, and a secondary active low-pass filter 23 composed of an operational amplifier OP2, a resistor and a capacitor. The DC voltage signals Va and Vb are connected to the subtracting circuit 24 and the adding circuit 25, respectively.

From the subtraction circuit 24, a voltage Vo proportional to the amount of change in each capacitance is output. The output of the adder circuit 25 is input to the inverting input terminal of the operational amplifier OP3 through a resistor and compared with the non-inverting input terminal voltage, so that the adder circuit output always has a constant value Vr. The amplitude or frequency is controlled.
The output Va of the operational amplifier OP1 and the output Vb of the operational amplifier OP2 in FIG. 7 can be expressed as follows.
Va = {2fCaRaAa (Vs−Vd)} / (1 + 2fCaRa) (1)

Vb = {2fCbRbAb (Vs−Vd)} / (1 + 2fCbRb) (2)

Here, the frequency and peak amplitude value of the sine wave from the f and Vs sine wave oscillators, Ra and Rb are the resistance values viewed from the nodes A and B in FIG. 7, respectively, and Aa and Ab are formed by OP1 and OP2, respectively. Is the gain of the pass band of the second order low pass filter being
In the configuration of FIG. 7, Aa = Ab≈1 (3)
It becomes.
Therefore, Va and Vb are 2fCaRa ≦ 1, 2fCbRb ≦ 1 (4)
Va is proportional to Ca and Vb is proportional to Cb.
At this time, the subtraction circuit output Vo is Vo = 2f (CaRa−CbRb) (Vs−Vd) (5)
And
Ra = Rb (6)
Under these conditions, Vo is proportional to Ca-Cb. Under the above conditions, the summing circuit output Vsum is Vsum = (Ca + Cb) (Vs−Vd) (7)
It becomes.
Since the integrator formed by OP3 controls the oscillation amplitude Vs or oscillation frequency f of the oscillator so that Vsum coincides with the DC voltage Vr, Vsum = (Ca + Cb) (Vs−Vd) = Vr (8)
It becomes. Therefore, the output Vo of the subtraction circuit 24 is obtained by substituting the equation (8) into the equation (5). Vo = {(Ca−Cb) Vr} / (Ca + Cb) (9)
It becomes. Therefore, this configuration can cancel the temperature change of Ca and Cb.
Japanese Patent No. 29967413 JP 07-55500 A

  However, the conventional direct detection method using a diode also detects electromagnetic waves other than external noise and signal components that are unrelated to the amount of change in capacitance. In addition, as shown in conditional expressions (3) and (6), high-precision matching of the detector circuit is required. Furthermore, from the conditional expression (4), the amplitude of the sine wave oscillator vs must be set to about several hundred volts in order to make the detection output a useful value.

In order to generate such a high voltage, a transformer is required, and there is a problem that the circuit scale becomes large.
Moreover, in order to prevent unnecessary radio waves from the transformer, an electromagnetic shield and a guard ring are required. Furthermore, in order to prevent discharge due to high voltage, the space between the capacitance electrodes must be widened, and it becomes easier to be affected by the parasitic capacitance and the electric field at the electrode end, and the overall system becomes complicated and large for higher accuracy. There was a problem that.

The object of the present invention is not to detect direct half-wave rectification using a diode, but to perform full-wave rectification using low-voltage driven synchronous detection, so that only the amount of change in capacitance can be detected, thereby simplifying the circuit scale. It is an object of the present invention to provide a signal processing circuit of a differential capacitance type transducer that can constitute a circuit that is possible and that is not affected by the DC offset voltage of the signal processing circuit itself or temperature drift.
Another object of the present invention is to provide external noise, offset, and temperature before synchronous detection when the capacitance change of each capacitance with respect to the movement of the second electrode has a first order error with respect to the ideal value of each capacitance. It is an object of the present invention to provide a signal processing circuit for a differential capacitive transducer that can compensate for the error without being affected by drift.

In order to achieve the above object, the present invention according to claim 1 is characterized in that a plurality of first electrodes arranged on the same plane, and a second electrode opposed to the first electrode via a gap are provided. Two capacitors Ca and Cb that share the first plurality of electrodes and the second electrode, and when one capacitor increases in accordance with the rotation or movement of the second electrode, the other is In a differential capacitive transducer arranged and connected so as to decrease, a sine wave oscillation circuit for supplying a high-frequency sine wave to the second electrode, and terminals of the plurality of first electrodes as input terminals A plurality of capacitance / voltage conversion circuits for converting a high-frequency current flowing through two capacitances into a voltage; a subtraction circuit for subtracting an AC voltage output of the plurality of capacitance / voltage conversion circuits; Add the AC voltage output of the voltage conversion circuit A synchronous detection circuit for synchronously detecting the AC voltage output of the circuit, the subtracting circuit and the adding circuit to obtain a DC output voltage proportional to (Ca−Cb) and (Ca + Cb), and a part of the output of the synchronous detection circuit A feedback circuit that controls the sine wave oscillation circuit so that the output of the addition circuit is always a constant DC potential by referring to a predetermined reference voltage, and the synchronous detection circuit includes: A waveform shaping circuit that obtains a synchronous carrier signal from an AC voltage output, a first synchronous detection unit that synchronously detects an AC voltage output of the subtraction circuit by the waveform shaping circuit output, and an AC voltage of the addition circuit by the waveform shaping circuit output It is characterized by comprising a second synchronous detector for synchronously detecting the output .
According to a second aspect of the present invention, in the first aspect of the present invention, the change in the two capacitances with respect to the rotation or movement of the second electrode is a capacitance change having a first order error with respect to an ideal value. In such a differential capacitance type transducer, the capacitance / voltage conversion circuit has a function capable of correcting the primary error by adjusting a part of circuit constants so as to change the sensitivity of the capacitance. It is characterized by having.

According to the above configuration, an output proportional to (Ca−Cb) / (Ca + Cb) can be obtained, and the output voltage is low power, low drive voltage, and is not affected by parasitic capacitance or external noise, and the circuit itself has a DC offset. The sine wave oscillation circuit can be made compact without being affected by voltage and temperature drift.
In addition, a circuit for obtaining a carrier signal for synchronous detection from the drive signal is not required, and the circuit can be made compact.
Furthermore, the first order error can be easily corrected.
By using the signal processing circuit of the differential capacitive transducer according to the present invention, a compact and highly accurate system for measuring the rotation angle and displacement can be constructed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating an example of a configuration of electrodes of a differential capacitive transducer.
The electrodes 1a and 1b are metal patterns on the substrate, and the electrode 2 of the metal pattern on the substrate is also provided facing the electrodes 1a and 1b. The electrode 2 is movable in the x direction.
Capacitances Ca and Cb formed between the electrode 2 and the electrodes 1a and 1b increase or decrease as the electrode 2 moves in the x direction.
The example shown in FIG. 1A is a case where the electrode 2 moves in the x direction while maintaining a parallel state with the electrodes 1a and 1b. In this case, the amount of change in capacitance with respect to the movement amount is shown in FIG. It changes linearly as shown. However, it is difficult to keep it completely parallel, and as shown in FIG. 2A, the electrode 2 may be inclined to some extent with respect to the electrodes 1a and 1b. In this case, the change amount of the capacitance with respect to the movement amount is a change amount of the curve as shown in FIG.

FIG. 3 is a block diagram showing an embodiment of the signal processing circuit of the differential capacitive transducer according to the present invention.
The signal processing circuit according to the present invention is formed between a sine wave oscillator 21 having an AGC circuit and outputting a high frequency sine wave vs, a capacitor Ca11 formed between the electrode 2 and the electrode 1a, and an electrode 2 and the electrode 1b. AC voltage of the CV conversion circuits 13 and 14 and the circuits 13 and 14 that are connected to the other terminals of the capacitor Cb12 and the capacitors 11 and 12, respectively, and output AC voltages va and vb according to the capacitances Ca and Cb. Va and vb are respectively input, and the subtraction circuit 15 and the addition circuit 16 that perform addition and subtraction, the AC output (vb-va) of the subtraction circuit 15 and the AC output (vb + va) of the addition circuit 16 are synchronously detected to detect a DC voltage detection signal. The synchronous detection circuit 17 that outputs Vo, the LPF 18 that removes noise superimposed on the DC voltage detection signal Vo of the synchronous detection circuit 17, and the synchronous detection circuit 1 The LFP 19 for removing the noise component of the output Vsum on the addition side and the output Vsum of the LFP 19 are compared with the reference voltage Vref so that the output on the addition circuit side is held at a constant value Vs, and the amplitude of the sine wave oscillator (or The feedback circuit 20 controls the frequency.

  The CV conversion circuit 13 includes an operational amplifier OP1 having a non-inverting input terminal grounded and an inverting input terminal connected to the terminal of the capacitor 11, and a resistor R connected between the inverting input terminal and the output. The CV conversion circuit 14 is formed of an operational amplifier OP2 having a non-inverting input terminal grounded and an inverting input terminal connected to the terminal of the capacitor 12, and a resistor R connected between the inverting input terminal and the output. In the subtraction circuit 15, the output (AC voltage va) of the operational amplifier OP1 is connected to the inverting input terminal side via the resistor R3, and the output (AC voltage vb) of the operational amplifier OP2 is connected to the resistor R5 on the non-inverting input terminal side. And an operational amplifier OP3 connected through the resistor R4 connected between the inverting input terminal and the output, and a resistor R6 connected between the non-inverting input terminal and the ground.

In the adder circuit 16, the output of the operational amplifier OP1 (AC voltage va) and the output of the operational amplifier OP2 (AC voltage vb) are connected to the inverting input terminal side through resistors R7 and R9, respectively, and the non-inverting input terminal side is grounded. The operational amplifier OP4 and the resistor R8 connected between the inverting input terminal and the output are formed.
The synchronous detection circuit 17 is a waveform shaping circuit 17c that generates a synchronous carrier signal from the output (va + vb) of the operational amplifier OP4, a synchronous detector 17a that synchronously detects the output (AC voltage vb-va) of the operational amplifier OP3 using this synchronous carrier signal, and Similarly, it is formed by a synchronous detector 17b for synchronously detecting the output (AC voltage va + vb) of the operational amplifier OP4 by the synchronous carrier signal.
The feedback circuit 20 includes an operational amplifier OP5 in which the output Vsum of the LPF 19 is connected to the inverting input terminal via the resistor R10, and the reference voltage Vref is input to the non-inverting input terminal, and the capacitor C1 connected between the inverting input terminal and the output. It is comprised from the integrating circuit which consists of.

Next, the operation of the signal processing circuit will be described with reference to the timing chart of FIG.
The AC voltage output of operational amplifiers OP1 and OP2 is
va = -jωCaRvs (10)
vb = −jωCbRvs (11)
It is represented by va and vb are in a state where the phase is advanced by 90 ° with respect to vs.
The outputs of the operational amplifiers OP3 and OP4 in the next stage for these AC voltages are
vb−va = jω (Ca−Cb) Rvs (12)
va + vb = jω (Ca + Cb) Rvs (13)
It becomes. When the AC voltage signal of equation (12) is full-wave rectified by synchronous detection and smoothed by the LPF 18, a DC voltage detection signal Vo proportional to the target capacitance change amount is obtained.

In addition, since the signal component asynchronous with the synchronous carrier signal vc is converted into an AC signal by synchronous detection and removed by the LPF 18, it is affected by external radio waves, noise, the DC offset voltage of the circuit itself and its temperature drift component. Only the amount of change in capacitance can be detected without any problem.
Furthermore, since the alternating voltage of the expression (12) is in phase with the alternating voltage of the expression (13), if a synchronous carrier signal is generated from the alternating voltage of the expression (13), a circuit for generating the carrier signal vc from the drive input signal is obtained. It becomes unnecessary and simplification of the circuit can be realized.

5A and 5B are examples of the synchronous detection output wave when the signal vc and the detection input signal have a predetermined phase relationship, and FIGS. 5B and 5C are the cases where the detection input signal for the signal vc is higher and lower than the synchronous carrier frequency. Each example is shown.
FIG. 5A shows a case where the signal vc and the detection input signal have the same phase, and is a circuit employed by the present invention. The output after synchronous detection and passing through the LPF 18 is Vo = (2ω / π) (Ca−Cb) RVs (14)
It becomes.
FIG. 5B shows a case where the signal Vc and the detection input signal are 90 ° out of phase, and the output after synchronous detection and passing through the LPF 18 becomes Vo = 0.
FIG. 5C shows a case where the detection input signal has a lower frequency than the signal Vc, and the output after synchronous detection and passing through the LPF 18 becomes Vo = 0 as described above.
FIG. 5D shows a case where the detection input signal has a higher frequency than the signal Vc, and the output after synchronous detection and passing through the LPF 18 becomes Vo = 0 as described above.
From the results of FIGS. 5C and 5D, it can be seen that noise having a frequency component different from the synchronous carrier frequency has no effect due to synchronous detection.

Further, the AC voltage itself of the expression (13) is also full-wave rectified by synchronous detection by the synchronous carrier signal vc, smoothed by the LPF 19, and a sine wave oscillator 21 having an AGC circuit or a DC voltage signal that is integrated with the reference voltage Vref. Connected to.
The relationship between the reference voltage Vref and the equation (13) at this time is as follows:
| Va + vb | = (2ω / π) (Ca + Cb) RVs = Vref (15)
Therefore, as a result, the DC voltage detection signal Vo proportional to the target capacitance change amount can be obtained by substituting Equation (15) into Equation (14).
Vo = {(Ca−Cb) Vref} / (Ca + Cb) (16)
It becomes. Therefore, it is possible to detect a DC voltage proportional to an ideal amount of change in capacitance without causing an error with respect to conventional diode detection.

  Further, in the circuit configuration of the present invention, each terminal of the capacitor of the differential capacitance type transducer is connected to the low impedance output terminal of the sine wave oscillator or the virtual ground of the CV conversion circuit, so that it is affected by the parasitic capacitance. There is no such thing.

The above operation is based on an ideal state in which the electrode 2 moves in a parallel state with respect to the electrodes 1a and 1b as shown in FIG. However, as described above, as shown in FIG. 2A, it is conceivable that the electrode 2 moves with a certain inclination. The amount of change in capacitance at this time is a curve as shown in FIG. That is, the amount of movement of the common electrode x
The capacitance change of each of the capacitances Ca and Cb with respect to the equation has a first-order error ε with respect to the ideal value of the capacitance Ca, and each capacitance at this time is expressed by equations (16) and (17). expressed.
Ca = Co (1 + x) / (1 + εx) (16)
Cb = Co (1-x) / (1-εx) (17)
Substituting the equations (16) and (17) into (Ca−Cb) / (Ca + Cb),
x (1-ε) / (1-εx ² ) (18)
It becomes. Here, Co is a capacitance at the origin position. Based on the above, when εx ² << 1 and 1 / (1−εx ² ) ≈1 + εx ² , formula (18) is rearranged:
x (1-ε) (1 + εx ² ) (19)
Thus, it can be seen that the final signal processing output is a second order error with respect to the movement amount x.

In order to compensate for this error, one of the terminals of the capacitance Ca is connected to the signal vs of the sine wave oscillator, and the other is fed back to the operational amplifier OP1 connected to the inverting input terminal of the operational amplifier OP1 serving as a virtual ground. By varying the resistance R, that is, adjusting the sensitivity of one capacitance, the output va of the operational amplifier OP1 and the output vb of the operational amplifier OP2 are: va = jωCo (1 + x) (R + r) vs / (1 + εx) (20)
vb = jωCo (1-x) Rvs / (1-εx) (21)
r: It is expressed as a compensation resistor for making the output va a first order error with respect to the movement amount x. Substituting the equations (20) and (21) into (va−vb) / (va + vb)
{2x (1-ε) R + (1 + x) (1-εx) r} / {2 (1-εx ² ) R + (1 + x) (1-εx) r} (22)
It becomes. Compensation resistance r such that this equation becomes equal to the ideal amount of displacement x is expressed by equation (22) = x.
r = 2εxR / (1-εx) (23)
Thus, the first order error component can be compensated by adjusting the compensation resistor r as shown in equation (23).

Further, since the output va is calculated in the alternating current region before the synchronous detection, the secondary error can be compensated without affecting external noise, offset, and temperature drift.
FIG. 6A shows the relationship of the output Vo to the movement amount x when there is a first order error with respect to the ideal value. FIG. 6B shows the relationship of the output Vo ′ with respect to the movement amount x when a resistor for compensating the first order error is connected.
It can be understood that the Vo ′ curve when the compensation resistor is inserted is closer to the ideal value straight line than the Vo curve having the first order error ε.
The same applies when the capacitance Cb has a first-order error ε with respect to the ideal value, and compensation can be made by changing the resistance value (capacitance sensitivity) of the feedback resistor R of the operational amplifier OP2. It is.

  The present invention can be applied to a scanner that scans laser light with a mirror attached to a rotating shaft of a motor.

It is a figure which shows an example of a structure of the division | segmentation electrode in an electrostatic capacitance type transducer. It is a figure for demonstrating the error which generate | occur | produces in the division | segmentation electrode in an electrostatic capacitance type transducer. It is a block diagram which shows embodiment of the signal processing circuit of the capacitive type transducer by this invention. 6 is a timing chart for explaining the operation of the signal processing circuit of the capacitive transducer according to the present invention. It is a wave form diagram which shows the example of the synchronous detection output wave in case the signal vc and a detection input signal are the same phases. It is a wave form diagram which shows the example of the synchronous detection output wave in case the phase of signal vc and a detection input signal differs 90 degrees. It is a wave form diagram which shows the example of a synchronous detection output wave when the frequency of a detection input signal is lower than the synchronous carrier signal vc. It is a wave form diagram which shows the example of a synchronous detection output wave when the frequency of a detection input signal is higher than the synchronous carrier signal vc. (A) is a diagram showing the relationship of the output Vo with respect to the movement amount x when there is a first order error with respect to the ideal value, and (b) is the output with respect to the movement amount x when a resistor for compensating the first order error is connected. It is a figure which shows the relationship of Vo '. It is a block diagram which shows an example of the signal processing circuit of the conventional capacitive transducer.

Explanation of symbols

1a, 1b, 2 electrodes 11, 12 capacitors 13, 14 CV conversion circuit (capacitance / voltage conversion circuit)
15 Subtraction circuit 16 Addition circuit 17 Synchronous detection circuit 18, 19 Low-pass filter (LPF)
20 Feedback circuit (integrator)
21 Sine wave oscillator

Claims (2)

A plurality of first electrodes arranged on the same plane and a second electrode facing the first electrode with a gap therebetween, wherein the first plurality of electrodes and the second electrode are In the differential capacitance type transducer having two capacitors Ca and Cb to be shared and arranged and connected so that when one capacitor increases in accordance with the rotation or movement of the second electrode, the other decreases,
A sine wave oscillation circuit for supplying a high-frequency sine wave to the second electrode;
A plurality of capacitance / voltage conversion circuits for connecting a terminal of the plurality of first electrodes to an input terminal and converting a high-frequency current flowing through two capacitors into a voltage;
A subtraction circuit for subtracting the AC voltage output of the plurality of capacitance / voltage conversion circuits;
An adding circuit for adding the AC voltage outputs of the plurality of capacitance / voltage conversion circuits;
A synchronous detection circuit that synchronously detects the AC voltage output of the subtraction circuit and the addition circuit, and obtains a DC output voltage proportional to (Ca−Cb) and (Ca + Cb);
A feedback circuit for controlling the sine wave oscillation circuit to input a part of the output of the synchronous detection circuit and refer to a predetermined reference voltage so that the output of the addition circuit is always a constant DC potential;
The synchronous detection circuit is
A waveform shaping circuit for obtaining a synchronous carrier signal from the AC voltage output of the adding circuit;
A first synchronous detector for synchronously detecting the AC voltage output of the subtracting circuit by the waveform shaping circuit output;
A second synchronous detector for synchronously detecting the AC voltage output of the adder circuit from the waveform shaping circuit output;
A signal processing circuit of a differential capacitance type transducer characterized by comprising: For a differential capacitive transducer in which the change in the two capacitances with respect to the rotation or movement of the second electrode results in a capacitance change having a first order error with respect to the ideal value,
2. The difference according to claim 1, wherein the capacitance / voltage conversion circuit has a function of correcting the first order error by adjusting a part of circuit constants so as to change sensitivity of the capacitance. Signal processing circuit for dynamic capacitive transducer.

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