JP3736348B2 - Single-chip microcomputer that can control output signal with timer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer, and more particularly to a microcomputer suitable for an electronic control device that performs processing periodically with an external device.
[0002]
[Prior art]
Conventionally, some electronic control devices (hereinafter referred to as “ECUs”) perform processing periodically with an external device.
For example, in a so-called keyless entry system that locks or unlocks a vehicle door wirelessly, even when the engine is stopped, the ECU detects the lock / unlock signal from the outside and detects a predetermined lock. Unlocking control must be executed. Such ECU operation while the engine is stopped is executed by the power supplied from the on-vehicle battery, but the battery is not charged while the engine is stopped, which is possible to prevent excessive consumption of the battery. It is necessary to suppress power consumption as much as possible.
[0003]
Therefore, conventionally, a microcomputer having the following configuration has been adopted as a microcomputer (hereinafter simply referred to as “microcomputer”) applied to such an ECU.
[Conventional example 1]
The conventional microcomputer 101 shown in FIG. 3 performs an intermittent operation that repeats a function stop state and an operation state, and outputs a start signal to an external device 50 having a communication function in the ECU at a predetermined timing during the intermittent operation. Then, the external device 50 is activated to perform communication processing with an external communication device (not shown).
[0004]
That is, as shown in FIG. 3A, the microcomputer 101 includes a CPU 102 that operates according to a predetermined program, a main clock generator 103 that generates a main clock (several MHz to several tens of MHz) that is an operation clock of the CPU 102, an external In addition to a basic configuration such as an I / O port 104 that inputs and outputs signals to and from the device 50, an intermittent operation control unit 105 that controls the CPU 102 to repeat an operation state and a stop state, and an intermittent operation control unit 105 A sub-clock generator 106 that generates a sub-clock that is an operation clock (having a frequency lower than the main clock and several tens of KHz) is provided.
[0005]
That is, in this microcomputer 101, when the CPU 102 determines that there is no process to be executed and it is not necessary to operate, the CPU 102 stops the operation and issues an operation instruction to the intermittent operation control unit 105.
Then, the intermittent operation control unit 105 outputs a stop command to the main clock generation unit 103 to stop the operation and starts timing. An operation command is output to the main clock generation unit 103 when a predetermined intermittent time (a time during which the CPU 102 is in a stopped state when intermittently operating) has elapsed. The main clock generator 103 starts operating again in response to this operation command, and starts supplying the main clock to the CPU 102. Then, after confirming that its own oscillation state is stabilized, a RUN signal for operating the CPU 102 is output. Upon receiving the RUN signal from the main clock generator 103, the CPU 102 wakes up from the stopped state to the operating state, and resumes the operation. The intermittent operation is performed by repeating the above operation.
[0006]
The specific operation of the microcomputer 101 is shown in FIG.
That is, the microcomputer 101 periodically outputs a start signal to the external device 50 during the intermittent operation. Then, it waits for a response from the external device 50 for a predetermined time (that is, waits for the external device 50 to complete the preparation for processing), and then performs a predetermined communication process with the external communication device via the external device 50 ( The desired action).
[0007]
In this case, when the CPU 102 is in a stopped state, not only the CPU 102 but also the main clock generation unit 103 stops its operation, so that power consumption is reduced accordingly. At that time, the intermittent operation control unit 105 operates. However, since the operation is performed using a sub-clock having a low frequency, the power consumption is relatively small.
[Conventional example 2]
A conventional microcomputer 201 shown in FIG. 4 has an operation speed switching function, and periodically outputs an activation signal in the low speed state.
[0008]
That is, the microcomputer 201 is an I / O port for inputting / outputting signals to / from the external device 50 and the main clock generator 203 that generates the main clock (several MHz to several tens of MHz) that is the operation clock of the CPU 202. In addition to the basic configuration such as 204, an operation speed switching control unit 205 provided between the CPU 202 and the main clock generation unit 203 is provided.
[0009]
The operation speed switching control unit 205 is configured by a known frequency dividing circuit or the like (PLL circuit or the like), and supplies the main clock generated by the main clock generating unit 203 to the CPU 202 as it is in response to a switching command from the CPU 202, or A frequency dividing circuit or the like (PLL circuit or the like) is operated to switch to a clock (several tens of KHz) slower than the main clock and supplied to the CPU 202.
[0010]
In other words, the CPU 202 operates at high speed by setting the frequency of the operation clock output from the operation speed switching control unit 205 to the frequency of the main clock during normal operation of executing the program, but there is no processing to be executed. When it is determined that the state has been reached, the operation clock frequency output from the operation speed switching control unit 205 is operated with a low-speed clock (that is, a low power consumption state).
[0011]
The specific operation of the microcomputer 201 is shown in FIG.
That is, in the microcomputer 1, the CPU 202 periodically outputs an activation signal to the external device 50 having a communication function at a preset time within the low speed operation period. Then, after waiting for a response from the external device 50 for a predetermined time and determining that the processing preparation of the external device 50 has been completed based on a preset time set in the program, a switching instruction is output to the operation speed switching control unit 205. It operates at high speed and performs predetermined communication with the external communication device via the external device 50.
[0012]
In this case, the CPU 202 operates with a low-speed clock until the external device 50 is activated and preparation for processing with the external communication device is completed. As for (time), the power consumption can be suppressed as compared with the case of the conventional example 1 described above.
[0013]
That is, the microcomputer 301 is an I / O port for inputting / outputting signals to / from the external device 50 and the main clock generator 303 that generates the main clock (several MHz to several tens of MHz) that is the operation clock of the CPU 302. In addition to the basic configuration such as 304, a timer control circuit 305 as a peripheral circuit is provided.
[0014]
The timer control circuit 305 is built in the microcomputer 301 as a peripheral circuit, and executes a normal timer interrupt process or the like according to an instruction from the CPU 302. In this configuration, the timer control circuit 305 further outputs a start signal to the external device 50 at a timing instructed by the CPU 302, and wakes up the CPU 302 from a stopped state to an operating state at a different timing. . The main clock generator 303 supplies the same main clock as the operation clock of the CPU 302 as the operation clock to the timer control circuit 305.
[0015]
In other words, in this microcomputer 301, when the CPU 303 determines that there is no process to be executed and it is not necessary to operate, the CPU 303 stops the operation and issues an operation instruction to the timer control circuit 305.
Then, the timer control circuit 305 starts timing and outputs a signal for waking up (wake-up signal) to the CPU 302 when a predetermined timer time has elapsed.
[0016]
Then, the CPU 302 wakes up from the stop state to the operation state by the wakeup signal from the timer control circuit 305, and resumes its operation.
The specific operation of the microcomputer 301 is shown in FIG.
That is, in the microcomputer 301, immediately before the CPU 302 stops its operation, the output timing (first set time) of the start signal to the external device 50 and the wake-up timing (second set time) of the CPU 302 are set to a timer. Set in the control circuit 305. The time difference between the first set time and the second set time coincides with the time from when the timer control circuit 305 outputs the start signal to when the external device 50 is started and ready for processing with the external communication device. It is set to be.
[0017]
In accordance with the setting of the CPU 302, the timer control circuit 305 outputs a start signal to the external device 50 when the first set time elapses after the operation stops, and further wakes up to wake up the CPU 302 when the second set time elapses. An up signal is output. For this reason, the CPU 302 can wake up when processing preparation of the external device 50 is completed, and can immediately execute predetermined communication processing.
[0018]
As described above, the CPU 302 can be stopped until the external device 50 is activated and can communicate with the external communication device, thereby reducing power consumption.
[0019]
[Problems to be solved by the invention]
However, in the conventional example 1, the microcomputer 101 needs to continue outputting the activation signal until the processing preparation of the external device 50 is completed. For this reason, the CPU 102 continues to operate during a period other than the original communication process. During this time, the CPU 102 receives the main clock and operates at a high speed, so that a relatively large amount of power is consumed.
[0020]
Further, in the conventional example 2, since the CPU 202 has no stop period and always operates at a low speed, the overall power consumption is rather larger than that in the conventional example 1.
Further, in the above conventional example 3, although the CPU 302 which is the central part of the microcomputer 301 stops its operation, an oscillation circuit (which generates a high-frequency clock for operating the CPU 302 in order to operate the timer control circuit 305 at all times). That is, a circuit that generates a main clock in the main clock generator 303 always operates. For this reason, current consumption cannot be significantly reduced. Moreover, it takes a long time until the CPU 302 wakes up after stopping the operation, and any external signal is input during that time, or even if there is a change in the internal device, there is a disadvantage that it cannot cope with this.
[0021]
The present invention has been made in view of these problems, and a microcomputer that periodically outputs a start signal to start a communication device that is an external device, and waits for a predetermined time for completion of processing preparation to start communication processing. The purpose is to reduce the power consumption.
[0022]
[Means for Solving the Problems and Effects of the Invention]
In view of this problem, the microcomputer according to claim 1 periodically outputs a start signal to an external device which is a communication means for communicating with the external communication device, and then the external device is started. The communication processing with the external communication device is started after waiting for a predetermined time, and the CPU for executing the communication processing with the external communication device via the external device and the control for operating the CPU intermittently are performed. Intermittent operation control means to perform.
[0023]
For this reason, the intermittent operation control means enables the CPU to perform the intermittent operation as shown in the conventional example 1, thereby reducing the power consumption of the microcomputer to some extent. In addition, by adopting the intermittent operation method in this way, at a time other than when the CPU executes the original intended operation of communication with the external communication device, the device is received by an input signal from the inside of the device to which the microcomputer is applied. It is also possible to appropriately grasp the state of the above. For this reason, when the said apparatus is abnormal, it can respond quickly.
[0024]
In the microcomputer, when the CPU stops its own operation, the CPU outputs an operation command to the timer interlock control means. When the timer interlock control means receives the operation command from the CPU, the CPU is stopped. When the external device wakes up to the operation state, the external device starts measuring the set time set to complete the processing preparation , and when the set time elapses, the start signal is output to the external device. For this reason, the CPU resumes the communication process when it wakes up after a lapse of a predetermined time after the timer interlock control means outputs the start signal, but there is no waiting time and at the same time as the wake-up in the intermittent operation Communication processing can be started. In other words, while ensuring intermittent operation, it is possible to make the CPU stop time relatively long, thereby expecting a significant reduction in power consumption, and improving processing efficiency .
[0026]
In this case, as a method of setting the CPU to the stop state, the CPU may stop the operation itself or simply stop the CPU via the intermittent operation control unit, but the main clock for operating the CPU may be used. When the generation source is in the microcomputer, it is preferable to stop the operation. This is because the main clock is a high-speed operation clock, and thus it is considered that the power consumption at the generation source is not negligible. For this reason, the power consumption can be significantly reduced by stopping the source of the main clock.
[0027]
Further, the intermittent operation control means itself, since they are to perform a simple operation of causing intermittent operation of the CPU, the operating clock is considered to be able to function well even in low-speed operation clock, the operation of the CPU The power consumption in the intermittent operation control means can be reduced by configuring to operate by receiving a sub clock having a frequency lower than that of the main clock to be operated.
In this case, as a method of generating the sub clock, the operation clock branched from the same generation source as the main clock may be generated by dividing the operation clock via a frequency dividing circuit or the like. Alternatively, a sub-clock generation source may be provided.
[0029]
However, when the generation source is shared as in the former case, the high-speed main clock generation source cannot be stopped as described above, so that it is difficult to achieve a power saving effect by stopping the generation source. It is done. From such a point of view, it is considered preferable to provide a generation source dedicated to the sub clock so that the main clock generation source can be stopped independently.
[0030]
From the same point of view as in claim 1 , as described in claim 2 , the timer interlocking control means may also be configured to operate by receiving a subclock having a frequency lower than that of the main clock for operating the CPU. preferable.
By the way, in the above configuration, since the set time by the timer interlocking control means is an important factor for reducing power consumption, it is desired to set the set time optimally.
In this case, the set time set in the timer interlocking control means may be set as a fixed value. In this case, the set time, the start time of communication processing, the communication time, etc. are uniquely defined. The target device and the control method to which the microcomputer can be applied are also limited to a very limited range.
[0032]
Therefore, as described in claim 3, it is more preferable that the CPU is configured to set the set time for the timer interlock control means during the operation (that is, it is programmable).
This is because by configuring in this manner, the versatility of the microcomputer is widened and can be applied to various control objects (devices).
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of a single chip microcomputer 1 of this embodiment.
[0035]
As shown in FIG. 1, the microcomputer 1 of this embodiment includes a CPU 2 that operates according to a predetermined program, a ROM 3 that stores programs and fixed data in advance, a RAM 4 that temporarily stores calculation results by the CPU 2, and a communication function. In addition to a basic configuration such as an I / O port 5 for inputting / outputting signals to / from an external device 50, a main clock (operation clock of the CPU 2) in cooperation with the oscillation element 11 provided outside the microcomputer 1 In the present embodiment, in cooperation with the oscillation control unit 6b, the main clock generation unit 6 including a main oscillation circuit 6a that generates several MHz to several tens of MHz) and an oscillation control unit 6b that controls the main oscillation circuit 6a, The intermittent operation control unit 7 that performs control for causing the CPU 2 to operate intermittently (intermittent operation), and the external device 50 according to an instruction from the CPU 2 A sub-clock (several tens of KHz in this embodiment) having a frequency lower than that of the main clock in cooperation with the timer interlocking control unit 8 for outputting a start signal, which will be described later, and the oscillation element 12 provided outside the microcomputer 1. And a sub oscillation circuit 9 for generating.
[0036]
In the microcomputer 1 of the present embodiment, each of the oscillation control unit 6b, the intermittent operation control unit 7, and the timer interlocking control unit 8 operates by receiving a subclock that is constantly generated by the sub oscillation circuit 9. .
Here, the CPU 2 can stop its own operation similarly to the CPU 102 of the conventional example 1 described above, and outputs an operation command to the intermittent operation control unit 7 when stopping its own operation. It is like that.
[0037]
On the other hand, the intermittent operation control unit 7 includes a register 7a in which the time to be measured for intermittent operation of the CPU 2 is set (written) by the CPU 2. The intermittent operation control unit 7 normally gives an operation instruction to the oscillation control unit 6b of the main clock generation unit 6 to operate the main oscillation circuit 6a in the oscillation control unit 6b. When the operation command is received (that is, when the CPU 2 stops the operation), a stop instruction is output to the oscillation control unit 6b, and the oscillation control unit 6b stops the operation of the main oscillation circuit 6a and is set in the register 7a. Start measuring the set time. When the set time elapses, an operation instruction is output again to the oscillation control unit 6b, and the oscillation control unit 6b restarts the operation of the main oscillation circuit 6a. The set time is counted based on the number of subclocks (that is, the number of periods).
[0038]
The oscillation control unit 6b of the main clock generation unit 6 switches between the operation and stop of the main oscillation circuit 6a in accordance with the operation instruction and stop instruction from the intermittent operation control unit 7. In particular, intermittent operation control is performed. When the operation of the main oscillation circuit 6a is started in response to the operation instruction from the unit 7, a predetermined oscillation stabilization wait time (set (written) by the CPU 2 is assumed that the frequency of the main clock is stabilized from that point. ) (With register 11a) elapses, a RUN signal is output to CPU 2 to wake CPU 2 from the stopped state to the operating state (see FIG. 2).
[0039]
The oscillation stabilization wait time is provided to wake up the CPU 2 after the main clock frequency is reliably stabilized, and is counted based on the number of sub-clocks.
In the microcomputer 1 of the present embodiment as described above, when the CPU 2 determines that the operation may be stopped and stops its own operation and outputs an operation command to the intermittent operation control unit 7, the intermittent operation control unit 7 outputs a stop instruction to the oscillation control unit 6b to stop the operation of the main oscillation circuit 6a, and starts measuring the set time set in the register 7a. When the set time elapses, the oscillation control unit The operation instruction is output again to 6b, and the operation of the main oscillation circuit 6a is resumed. Then, when the above-described oscillation stabilization waiting time elapses, a RUN signal is output from the oscillation control unit 6b to the CPU 2, and the CPU 2 wakes up from the stopped state to the operating state. By being repeated, the intermittent operation of the CPU 2 is performed.
[0040]
Further, when the CPU 2 outputs the operation command to the intermittent operation control unit 7 as described above, the CPU 2 outputs the operation command to the timer interlocking control unit 8 at the same time.
On the other hand, the timer interlocking control unit 8 includes a register 8a in which a time to be measured (corresponding to a preset set time) is set (written) by the CPU 2.
[0041]
When the timer interlock control unit 8 receives an operation command from the CPU 2, the timer interlocking control unit 8 starts measuring the time set in the register 8a (hereinafter referred to as a set time), and when the set time elapses, the I / O port 5, an activation signal is output to the external device 50. This set time is set at a timing when the CPU 2 performs a predetermined number of intermittent operations after transitioning to the intermittent operation mode. In addition, the time from the output of the start signal to the completion of processing preparation of the external device 50 is obtained in advance by experiments or the like, and the set time is the time when the CPU 2 wakes up from the stopped state to the operating state. The time is set such that the external device 50 completes the preparation for processing. The set time is counted based on the number of subclocks (that is, the number of periods).
[0042]
Next, specific operation timing of the microcomputer 1 will be described with reference to FIG. FIG. 2 shows an example in which the next communication process is started in synchronization with the third wake-up after the CPU 2 shifts to the intermittent operation mode after completing the previous communication process.
First, at the end of the previous communication process, the CPU 2 operates the intermittent operation control unit 7 as described above to shift to the intermittent operation mode, while the timer interlock control unit 8 stores the timer interlock control in the register 8a. The unit 8 sets a time t at which the start signal should be output, and outputs an operation command to the timer interlocking control unit 8.
[0043]
When the timer interlock control unit 8 receives an operation command from the CPU 2, the timer interlocking control unit 8 starts measuring the set time t set in the register 8 a. The activation signal is output to the device 50.
Therefore, after the CPU 2 shifts to the intermittent operation, the preparation for the processing is completed at the time of the third wake-up, and the CPU 2 can immediately execute the target communication process after the wake-up.
[0044]
Thus, in the present embodiment, the CPU 2 can execute the intended communication process without requiring a waiting time after getting up at a certain point in the intermittent operation. In other words, it is possible to avoid a situation in which the CPU 2 wakes up and operates although the processing preparation is not completed. For this reason, the CPU 2 can be stopped for a relatively long time, and the power consumption can be reduced accordingly. In particular, when the CPU 2 performs the intermittent operation as described above, it is considered that the effect of reducing the power consumption is cumulatively increased, and a significant reduction in power consumption can be expected as a whole.
[0045]
In addition, the timer interlock control unit 8 is configured as a dedicated timer for the microcomputer 1 and automatically outputs a start signal after a set time by the CPU 2, so the output timing of the start signal is set by software. It is not necessary and power consumption can be reduced with a simple configuration.
[0046]
In this embodiment, the intermittent operation control unit 7 corresponds to intermittent operation control means, and the timer interlock control unit 8 corresponds to timer interlock control means.
As mentioned above, although the Example of this invention was described, it cannot be overemphasized that embodiment of this invention can take various forms, as long as it belongs to the technical scope of this invention, without being limited to the said Example at all. Nor.
[0047]
For example, in each of the above embodiments, the time taken by the intermittent operation control unit 7 is not set (programmable) by the CPU 2 but may be a fixed value. However, it is more versatile and advantageous to adopt the configuration of the above-described embodiment in which the time can be arbitrarily set.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a microcomputer according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram for explaining a method of using the microcomputer according to the embodiment and its operation.
FIG. 3 is an explanatory diagram for explaining a conventional example 1;
FIG. 4 is an explanatory diagram for explaining a second conventional example.
FIG. 5 is an explanatory diagram for explaining a conventional example 3;
[Explanation of symbols]
1 ... Microcomputer, 2 ... CPU, 5 ... I / O port,
6 ... main clock generation unit, 7 ... intermittent operation control unit,
8 ... Timer interlocking control unit, 9 ... Sub oscillation circuit

Claims (3)

A microcomputer that periodically outputs a start signal to an external device that can be controlled by starting and outputting a start signal, and then starts processing after a predetermined time for the external device to start,
A CPU for executing processing with the external device;
Intermittent operation control means for controlling the CPU to operate intermittently;
Timer interlocking control means for outputting the start signal to the external device according to a set time set so that the external device completes processing preparation when the CPU wakes up from the stopped state to the operating state. Prepared,
When the CPU stops its own operation, it outputs an operation command to the timer interlock control means,
The intermittent operation control means operates by receiving a sub clock having a frequency lower than a main clock for operating the CPU,
The timer interlock control means starts counting the set time when receiving the operation command from the CPU, and outputs the start signal to the external device when the set time elapses. Microcomputer. A microcomputer that periodically outputs a start signal to an external device that can be controlled by starting and outputting a start signal, and then starts processing after a predetermined time for the external device to start,
A CPU for executing processing with the external device;
Intermittent operation control means for controlling the CPU to operate intermittently;
Timer interlocking control means for outputting the start signal to the external device according to a set time set so that the external device completes processing preparation when the CPU wakes up from the stopped state to the operating state. Prepared,
When the CPU stops its own operation, it outputs an operation command to the timer interlock control means,
The timer interlocking control unit operates by receiving a sub clock having a frequency lower than a main clock for operating the CPU, and when receiving the operation command from the CPU, starts measuring the set time. When the time has elapsed, the activation signal is output to the external device.
A microcomputer characterized by that. 3. The microcomputer according to claim 1, wherein the CPU sets the set time for the timer interlock control means during the operation.

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