JP3517314B2 - Clock supply device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of digital signal processing technology and its circuit technology. In particular, it relates to a clock supply device for a computer or an IC card.

[0002]

2. Description of the Related Art A digital circuit includes an asynchronous circuit and a synchronous circuit. In the synchronous circuit, the operation of the circuit proceeds in synchronization with a clock signal. A device that supplies this clock signal to the digital circuit is a clock supply device. The operation of the synchronous circuit is the frequency of the clock signal (clock frequency)
High-speed processing is possible when the clock frequency is high. However, in reality, an appropriate clock frequency is selected in consideration of the operational limits of the synchronous circuit, the operational limits of the peripheral devices, and the reliability. Also, regardless of the operation limit, an appropriate clock frequency may be set depending on the application. For example, the sampling time or the like in the measuring device depends on the clock frequency, or the clock frequency is changed according to the specifications of the connected external device in the communication device. As described above, in a device having a synchronous circuit, there is an appropriate value for the clock frequency, and if the clock frequency changes depending on the situation, there are some that prepare and select and use a plurality of clock frequencies.

An example is an IC card, and the standard clock frequency of the IC card in Japan is 4.9 MHz.
Is standard, the standard clock frequency in the ISO standard is 3.5 MHz. Therefore, in order to realize an IC card conforming to the ISO standard, when the IC card is accessed by the reader / writer device, the 3.5 MHz clock in the ISO standard is supplied in the initial stage, and then the standard of Japan is used. 4.9M
It is necessary to perform processing to switch to the Hz clock.

[0004]

However, when the clock frequency is changed according to the situation as described above, it may not be possible to unconditionally change it. For example, the CPU (Central Processing Uni
t; If the frequency of the clock signal supplied to the central processing unit) is changed indiscriminately, malfunction or runaway may occur. Therefore, in order to enable the switching of the clock frequency while maintaining the normal operation, a method of switching the clock frequency while keeping the duty factor within a certain range has been proposed. For example, a method of switching at the moment when the phases of signals to be switched match (phase matching method),
There has been proposed a system (PLL system) in which a frequency is changed stepwise before and after switching using a PLL circuit.

However, in the phase matching method, the timing control circuit is required for the number of switching frequencies, and the control circuit for switching timing becomes complicated.
The time from the input of the signal instructing the switching to the actual switching of the clock depends on the clock frequency and timing and is not constant. Also, in the PLL system,
The configuration itself of the PLL circuit such as the VCO and the low-pass filter is complicated, and the time required for switching is long depending on the characteristics of the low-pass filter. Therefore, an object of the present invention is to provide a clock supply device in which the CPU does not malfunction even if the clock frequency is switched while the CPU is operating normally, and the device configuration is simple and the clock can be switched quickly. Especially.

[0006]

The above object can be achieved by the present invention described below. That is, the present invention has "a pulse oscillating means, a frequency dividing means, and a selecting means, and there are a plurality of the pulse oscillating means, each of which outputs a pulse oscillating signal of a frequency corresponding to a desired clock frequency. The frequency divider inputs the selected pulse oscillation signal, divides it by 2n in n, which is an integer value of 2 ≦ n, and generates a clock signal, and the selecting means raises and falls the clock signal. In the step 1, the counting of the number of pulses of the pulse oscillation signal is started, and the pulse oscillation signal corresponding to the selection input is selected in synchronization with the point when the count value reaches the count setting value m of 1 ≦ m ≦ (n−1). It is a switching clock supply device. "

In the clock supply device of the present invention, the pulse oscillating means exists in the number of the desired clock frequency, and outputs the pulse oscillating signal at the frequency of 2n times the desired clock frequency. This pulse oscillation signal is 2n by the frequency dividing means.
The frequency is divided and a clock signal is generated. Further, the selection means selects one of a plurality of pulse oscillation signals of the pulse oscillation means corresponding to the selection input and outputs it to the frequency division means. Here, when the selection input is switched, the selection means does not immediately switch the pulse oscillation signal to be selected, but the selection means switches the pulse oscillation signal in synchronization with a predetermined timing. The timing is the time when the counting of the pulse number of the pulse oscillation signal is started at the rising and falling edges of the clock signal and the count value reaches the count setting value m of 1 ≦ m ≦ (n−1).

According to the present invention described above, even if the clock frequency is switched while the CPU is operating normally, the CP
The U does not malfunction, and the device configuration is simple and the clock can be switched quickly. Further, in the above-mentioned present invention, the effect is more remarkable when the n and the m satisfy the following formula 2. The reason why the count setting value m has a value below the decimal point in Expression 2 is that m means not a “count value” but a value as “timing” of switching. The value below the decimal point is 0.5, which means a half cycle.

## EQU2 ## n = 2 ^x-1 m = 2 ^x-2 +0.5 where 3 ≤ x

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 is a diagram showing a configuration of a clock supply device of the present invention. In FIG. 1, 1, 2 and 3 are pulse oscillating means, and there are a plurality of them, 1 is a first pulse oscillating means, 2 is a second pulse oscillating means, and 3 is a k-th pulse oscillating means. Further, 4 is a selecting means, and 5 is a frequency dividing means. The selecting means 4 inputs the pulse oscillation signals output from the pulse oscillating means 1 to 3, selects one of them and outputs it to the frequency dividing means. The frequency dividing means 5 receives the pulse oscillation signal output from the selecting means 4, divides it by 2n, and outputs a clock signal. Here, n is an integer value of 2 or more (the same as or larger than 2).

The selecting means 4 inputs a signal capable of detecting the rising and falling edges of the clock signal, that is, a rising and falling edge signal. The rising and falling signals are
Instead of the direct clock signal, for example, it may be a signal one stage before the clock signal of the frequency dividing means, and in order to show that, the clock signal is connected to the rising and falling signals by broken lines in FIG. Further, the selecting means 4 starts measuring the number of pulses of the selected pulse oscillation signal at the rising and falling edges of the clock signal. Then, the selection means 4 switches the selection to the pulse oscillation signal corresponding to the selection input in synchronization with the time when the count value reaches the count setting value m of 1 ≦ m ≦ (n−1).

FIG. 2 is a diagram showing the configuration of the clock supply device of the present invention in a more practical form. FIG. 3 is a timing chart showing the operation of the clock supply device shown in FIG. In FIG. 2, reference numeral 21 is a switch for selecting one of a plurality of pulse oscillation signals, 22 is a frequency divider for dividing the selected clock signal by 2n, and 23 is a selection signal (equivalent to "selection input"). Is a latch for input-holding at the timing of the trigger signal and outputting it to the switch 21. As shown in FIG. 3, the pulse oscillation signal 1 and the pulse oscillation signal 2 have different frequencies, and the frequency of the pulse oscillation signal 2 is high in this example. The selection signal 1 and the selection signal 2 are signals that are normally input asynchronously from the outside, and a plurality of selection signals perform an exclusive operation, and only one of them has a selected signal level. The latch output is a signal output from the latch 23 to the switch 21, and the latch output changes in synchronization with the trigger signal (see FIG. 2), and the pulse oscillation signal output from the switch 21 to the frequency divider 22 is switched off. Replace

The selector 21 switches the selected oscillation signal,
It is the selected pulse oscillation signal, that is, the pulse oscillation signal output to the frequency divider 22. In the example of FIG. 3, the pulse output signal 1 is output before the latch output changes, and the pulse output signal 2 is output after the change from the switch 21. The clock signal is an output obtained by dividing the selected oscillation signal by 2n,
Naturally, it changes before and after the latch output changes. The trigger signal that causes the change of the latch output starts counting the number of cycles of the selected oscillation signal (that is, the number of pulses of the pulse oscillation signal) at the rising and falling edges of the clock signal, and the count value is the count setting value m (1 ≦ It is output when m ≦ (n−1) is reached. Even if the trigger signal is output, nothing happens if the selection signal does not change, but the selection oscillation signal is switched by the first trigger signal after the selection signal changes.

As is apparent from the above description, the selecting means 4 in FIG. 1 is composed of all of the switching device 21, the part of the frequency divider 22 and the latch 23 of FIG. The frequency dividing means 5 in FIG. 1 is composed of a part of the frequency divider 22 in FIG. The details of the configuration will be made clearer by the embodiments described below.

[0014]

FIG. 4 shows an example of the circuit configuration of the clock supply device of the present invention. In FIG. 4, X1 and X2 are input terminals for the pulse oscillation signal output by the pulse oscillation means, and the pulse oscillation means itself is omitted. In this embodiment, as is clear from the following description, n = 4 and M =
2.5, which satisfies the relationship between n and m in claim 1 and the relationship between n and m in claim 2 of the present invention. BUF1 and BUF2 are three-state buffers and correspond to the switch 21 of FIG. The three-state buffer has three terminals: a signal input terminal, a signal output terminal, and a control input terminal. If the control input terminal is "H", the signal input terminal and the signal output terminal have the same logical value. When the control input terminal is "L", the signal output terminal becomes "high impedance" regardless of the logical value of the signal input terminal. It is called a three-state buffer because the signal output terminal has three states of "high impedance" as well as "H" and "L" of normal logic elements. By setting the control input terminal of either BUF1 or BUF2 to "H" exclusively,
Only the signal (the pulse oscillation signal of either X1 or X2) at the signal input terminal of the three-state buffer which is set to "H" is output to the signal output terminal as the selective oscillation signal.

CNT is a counter, and the frequency divider 2 in FIG.
Equivalent to 2. In CNT, CK is a clock input terminal, Q1 is a divide-by-2 output terminal, Q2 is a divide-by-4 output terminal, Q
Reference numeral 3 is an output terminal divided by eight. This Q3 is not only a divide-by-8 output terminal but also a clock signal output terminal. That is, the CNT is both a counter and a frequency dividing means. Further, CK and Q1 are directly connected to the input terminal of the AND gate, and Q2 is connected to the input terminal of the AND gate through the inverter. This AND gate has an output terminal that is "H" only when all the input terminals are "H", and is "L" otherwise. Therefore, AND
The gate is 1 every 8 cycles of the selective oscillation signal input to CK.
It becomes “H” at a rate of times (see FIG. 5 for details of timing).

FF1 and FF2 are D-type flip-flops and correspond to the latch shown in FIG. S1 and S2 are X
It is an input terminal of a selection signal for selecting the pulse oscillation signals of 1 and X2, and is connected to the D input terminals of FF1 and FF2. In FF1 and FF2, Q is an output terminal. CK is a clock input terminal, and the logical value (“H” or “L”) input to the D input terminal is output to the Q output terminal and held at the rising edge of the pulse input to CK. An exclusive signal of which only one signal is "H" is input to S1 and S2. Therefore, BUF
One of the control input terminals of 1 and BUF2 becomes "H", and the pulse oscillation signal on the side that becomes "H" is selected.

FIG. 5 is a diagram showing a timing chart of the clock supply device of FIG. In the timing chart of FIG. 5, the pulse oscillation signal X1 is 28 MHz and the pulse oscillation signal X2 is 40 MHz. Further, the clock X1 is selected in the initial state, and then the clock X2 is selected, and the output clock signal is set to 3.5 MHz (8 MHz of 28 MHz).
(Division) to 5 MHz (40 MHz divided by 8). At time t1, the selection signals S1 and S2 switch. The FF1 and FF2 hold the logical value of the Q output terminal up to that time until the time t2 at which the CK terminal receives the signal from the AND gate which changes from "L" to "H", and switch after the time t2. Since the frequency of the selective oscillation signal input to the CK of the counter CNT changes after time t2, the rise of the pulse oscillation signal X2 is counted, and the Q2 output and the Q3 output are divided into 4 and 8 of the pulse oscillation signal X2, respectively. Become. Then, after the time t3 when the output state of the Q3 output changes, the Q3 output signal is the pulse oscillation signal X2 (40 MH).
It becomes 5 MHz which is a frequency division of 8 of z).

In order for the CPU to operate normally, it is necessary that the duty factor of the clock signal be within a certain range. The duty factor in this embodiment will be examined. The half cycle time before the time t1 when the selection signals S1 and S2 are changed is Ta, t1.
The half cycle including Tb is Tb, and the time of the half cycle after Tb is Tc. Ta and Tc are constant because they are determined only by X1 and X2, but there is some variation in Tb depending on the phases of X1 and X2 at the switching instant. That is, at time t2 when the selective oscillation signal input to CK of CNT switches, the phases of X1 and X2 do not always match, and there is a possibility that a maximum time difference of one cycle of X2 will occur.

The signal of X2 when the phase shifts to the maximum is X2 'and the signal input to the CK of the CNT is CK', and the case where the phases match is compared. In FIG. 5, X
Reference numeral 1 is a pulse oscillation signal selected before switching, and its frequency is 28 MHz. X2 and X2 'are pulse oscillation signals selected after switching and have a frequency of 40 MHz,
The case where the phases match at X1 and t2 is X2, and the case where the phases are slightly delayed is X2 ′. Also CNTC
K and CNTCK ′ are signals input to the CK of CNT, and when the selected oscillation signal after switching is a signal from X2, CNTCK, and when it is a signal from X2 ′, C
NTCK '. The CNT divides the pulse input to CK by 8 and outputs it to Q3. When the pulse input to CK is CNTCK, the output signal is CNTQ3 and CN
The output signal in the case of TCK 'is CNTQ3'.

In FIG. 5, CNTCK and CNTCK '
When compared with, the time from counting the second count at time t2 to counting the third count is CNTCK.
And CNTCK ', CNTCK' is shortened by about half a cycle of X2. Therefore, the output pulse width T of CNTQ3
b and the output pulse width Tb 'of CNTQ3' are as follows. Tb = 126.79 ns Tb ′ = 114.29 ns where Ta = 142.85 ns Tc = 100.00 ns.

The duty factors DFA and DFA 'before switching the pulse oscillation signal and the duty factors DFB and DFB' after switching are calculated as follows. Both fall within the range of 40 to 60%, and the clock can be switched while satisfying the standard specifications of the input of the microprocessor. DFA = Ta / (Ta + Tb) = 0.530 DFA '= Ta / (Ta + Tb') = 0.556 DFB = Ta / (Tc + Tb) = 0.441 DFB '= Ta / (Tc + Tb') = 0.467

[0022]

As described above, according to the present invention, the CPU does not malfunction even if the clock frequency is switched while the CPU is normally operating, and the device configuration is simple and the clock can be switched. A quick clock supply is provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a clock supply device of the present invention.

FIG. 2 is a diagram showing a configuration of a clock supply device of the present invention in a more practical form.

FIG. 3 is a timing chart showing an operation of the clock supply device shown in FIG.

FIG. 4 is an example of a circuit configuration of a clock supply device of the present invention.

5 is a diagram showing a timing chart of the clock supply device of FIG.

[Explanation of symbols]

1 First pulse oscillating means 2 Second pulse oscillating means 3 Kth pulse oscillating means 4 selection means 5 frequency dividing means 21 Switch 22 frequency divider 23 Latch

Claims (2)

(57) [Claims] 1. A pulse oscillating means, a frequency dividing means, and a selecting means, wherein there are a plurality of the pulse oscillating means, each of which outputs a pulse oscillating signal having a frequency corresponding to a desired clock frequency, The frequency divider inputs the selected pulsed oscillation signal,
The frequency is divided by 2n in n, which is an integer value of 2≤n, to generate a clock signal, and the selection means starts counting the number of pulses of the pulse oscillation signal at the rising and falling edges of the clock signal, and the count value is A clock supply device, wherein the selection is switched to the pulse oscillation signal corresponding to the selection input in synchronization with the time when the count setting value m of 1 ≦ m ≦ (n−1) is reached. 2. The clock supply device according to claim 1, wherein the n and the m satisfy the following formula 1. N = 2 ^x-1 m = 2 ^x-2 + 0.5 where 3 ≤ x