JP3487903B2 - Arithmetic device and arithmetic method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fixed-point arithmetic unit incorporated in a digital signal processor (DSP) or the like, and more particularly, to accurately perform overflow correction in double-precision arithmetic or parallel arithmetic. It is composed.

[0002]

2. Description of the Related Art In recent years, DSP has been widely used in digital mobile phones and the like. In such a DSP for incorporating equipment,
In order to keep costs down, a device for performing fixed-point arithmetic is built in as an arithmetic device.

In a fixed-point arithmetic unit, a decimal point is often placed at the right end of the displayed numerical value to treat the numerical value as an integer. When the number of digits of the calculation result overflows, overflow correction is performed to set the calculation result to the maximum positive value or the minimum negative value in accordance with the direction of the overflow.

Description will be made of overflow correction when a double precision operation is performed in a conventional operation device of this type.

As shown in FIG. 7, this arithmetic unit stores memories 1 and 2 for storing N-bit data, an ALU 5 which is a logical and arithmetic unit, and an ALLU for the data of the memory 1.
A bus 3 input to the right side of U5 and data in memory 2
Connected to the bus 4 inputting to the left side of LU5 and ALU5, overflow detection signal 11 and overflow code signal 12
Overflow detection means 6, which outputs a carry flag register 7 which holds a carry generated in the most significant bit of the lower digit in a double-precision operation, and overflow detection signal 11 which is active and overflow code signal 12 Outputs the maximum positive value when positive, overflow detection signal 11 is active, and overflow sign signal
When 12 is negative, the negative minimum value is output, and when the overflow detection signal is not active, the maximum value minimum value setting means 8 that outputs the output of the ALU 5 as it is and the output of the maximum value minimum value setting means 8 are retained as they are. Registers 9 and 10
It has and.

The overflow detecting means 6 has the structure shown in FIG. 8 and outputs the carry value of the most significant digit of the complemented number as the overflow code signal 12 (0
Is positive and 1 represents negative), and overflow detection signal 11 of 0 when the carry value of the most significant digit and the carry value from the previous digit match, and 1 when they do not match.
Is output.

As shown in FIG. 9, the maximum / minimum value setting means 8 outputs "10000 ..." (Negative minimum value) when the overflow code signal 12 is 1, and the overflow code signal 12 is 0. In this case, a maximum value / minimum value output element that outputs "01111 ..." (Positive maximum value) and a multiplexer to which the output from this element and the output of the ALU 5 are input. The multiplexer selects the output of the ALU 5 when the overflow detection signal 11 is 0, and selects the output of the maximum value / minimum value output element when the overflow detection signal 11 is 1.

Now, it is assumed that the number of bits N of data in the memories 1 and 2, the buses 3 and 4, the ALU 5, and the registers 9 and 10 is 16 bits. In the double-precision operation, the ALU 5 adds / subtracts the data supplied from the bus 3 and the bus 4 twice. As a result, it is possible to add / subtract 2N = 32-bit data.

The maximum positive value in 16 bits is 7fff in 2's complement notation, and the minimum negative value is 8000. The maximum value / minimum value setting means 8 outputs the maximum positive value 7fff when the overflow detection signal 11 is active (1) and the overflow code signal 12 is positive (0), and the overflow detection signal 11 is active and the overflow code signal 12 is output. Is negative (1), the negative minimum value 8000 is output.

In the arithmetic unit configured as described above, the operation for performing addition / subtraction of double-precision (2N = 32 bits) data X and Y will be described.

(1) Step of Addition / Subtraction of Lower Side Data of X and Y First, the lower 16 bits of data XL of the data X is read from the memory 1 and output to the bus 3. Further, the lower 16 bits of data YL of data Y are read from the memory 2 and output to the bus 4. The ALU 5 performs addition and subtraction of XL and YL, and outputs the result to the register 10 via the maximum / minimum value setting means 8.
To store.

The carry generated in the most significant bit is stored in the carry flag register 7. At this time,
The maximum value / minimum value setting means 8 outputs the output of the ALU 5 to the register 10 as it is.

(2) Step of Addition / Subtraction of Higher-Order Data of X and Y: First, the upper 16-bit data XU of the data X is read from the memory 1 and output to the bus 3. Further, the upper 16 bits of data YU of data Y are read from memory 2 and output to bus 4. The ALU 5 performs addition / subtraction of the values of the XU, YU and carry flag register 7, and stores the result in the register 9 via the maximum / minimum value setting means 8.

At this time, the overflow detecting means 6 is
When the calculation result of the ALU 5 overflows, the overflow detection signal 11 and the overflow code signal 12 indicating the direction of the overflow are output. The maximum value / minimum value setting means 8 is a positive maximum value (7f) when the overflow detection signal 11 is active and the overflow sign signal 12 is positive.
ff), and when the overflow detection signal 11 is active and the overflow sign signal 12 is negative, the minimum negative value (8000) is output. When the overflow detection signal 12 is not active, the output of ALU5 is output as it is.

By the operations of the steps (1) and (2), the double-precision data is added and subtracted, and the operation result of the lower 16 bits is stored in the register 10 and the operation result of the upper 16 bits is stored in the register 9. To be done.

[0016]

However, in the conventional arithmetic unit, when the arithmetic result overflows in the double precision arithmetic, the value of the lower 16 bits stored in the register 10 of the arithmetic result 32 bits is corrected. Is not done,
There is a problem that the overflow cannot be correctly corrected to the maximum positive value or the minimum negative value with 32-bit precision.

Further, in recent years, a convolutional code is often used for error correction in digital communication, and the Viterbi decoding process of the error correction convolutional code is often performed by a DSP. Viterbi decoding is executed by repeating a process called a so-called ACS (addition comparison selection) operation. This ACS operation is a process of performing addition twice, comparing the magnitudes of the addition results, and selecting one of the two addition results based on the comparison result. Since such processing is repeated, by the time the Viterbi decoding result is obtained,
A large number of calculations are required and it takes time. Therefore, it is required to efficiently process such a large number of calculations to speed up the calculations, and to accurately correct the overflow when an overflow occurs in each of the calculations.

The present invention addresses these problems, and an object of the present invention is to provide an arithmetic unit and an arithmetic method capable of accurately performing overflow correction when arithmetically operating double-precision data.

It is another object of the present invention to provide an arithmetic unit and an arithmetic method capable of efficiently processing a large number of arithmetic operations and accurately performing overflow correction in the arithmetic operations.

[0020]

Therefore, in the present invention, the first register for storing the operation result of the upper digit of the double precision data and the second register for storing the operation result of the lower digit of the double precision data.
And a maximum value / minimum value setting means for outputting the maximum value or the minimum value to the first register based on the detection result of the overflow detection means. The apparatus is provided with a correction unit that sets the output value of the second register to data in which all bits are 0 or 1 based on the detection result of the overflow detection unit.

In addition, in the method of calculating the double-precision data in which the calculation of the upper digit and the calculation of the lower digit of the double-precision data are performed a plurality of times, in calculating the upper digit of the double-precision data,
An overflow of the operation result is detected, and the operation result of the upper digit is set to the maximum value or the minimum value based on the overflow detection result, and the operation result of the lower digit is set to the data whose all bits are 0 or 1. ing.

Bits of data handled by one arithmetic unit
Include multiple data in width and read from memory simultaneously
A plurality of operations on a plurality of data in parallel,
Depending on the presence or absence of overflow in each of the multiple operations
The maximum value or
Is configured to output the minimum value .

Further, a plurality of operation results stored in the register
To perform a plurality of operations in parallel to obtain the plurality of operations
Depending on the presence or absence of overflow in each of the
Maximum or minimum value as a result of each number operation
And the operation result stored in the register.
To obtain the above-mentioned one calculation result
Depending on the presence or absence of overflow in the operation,
The maximum or maximum value as the result of the operation to obtain the calculation result.
It is possible to perform any operation with the storage of small values,
Is calculated based on the results of the above multiple operations on the lower side.
Based on the presence of overflow,
When occurs, the maximum value is returned as the calculation result of the lower side.
Or the minimum value is stored in the lower side of the register, and
When performing the operation to obtain the operation result of
The presence or absence of overflow is determined based on the result of the
If one overflow occurs
The lower side of the maximum value or the minimum value as the calculation result
It is configured to be stored in the lower side of the register .

Further, in the calculation method of the present invention, one calculation
Including the multiple data in the bit width of the data
Memory for multiple data read simultaneously from memory.
The operations are performed in parallel, and each operation of the plurality of operations is performed.
Each of the plurality of operations depending on the presence or absence of bar flow
To output the maximum or minimum value as a result of
There is.

Further, in the calculation method of the present invention, the register
Store multiple operations in parallel to obtain multiple operation results.
Done in columns and overflow in each of the above operations
Depending on the presence or absence of
Storage of the maximum or minimum value and the value stored in the register.
Perform the calculation to obtain one calculation result
There is an overflow in the operation to obtain one operation result.
Depending on nothing, the result of the operation for obtaining the above-mentioned one operation result
Play either with maximum or minimum value storage
Is possible, and when performing the above multiple operations,
Whether there is an overflow based on the results of the multiple operations
When an overflow occurs, the lower side
The maximum value or the minimum value as the operation result of
An operation for storing in the lower side and obtaining the above-mentioned one operation result
When performing
When there is a flow and an overflow occurs
Is the maximum value as the operation result for the one data or
Stores the lower side of the minimum value in the lower side of the register.
I am sorry.

[0026]

Therefore, in the arithmetic unit and the arithmetic method for arithmetically operating double-precision data, when overflow occurs and the upper digit is set to the maximum value, the lower digit is also "1111".
. "And the upper digit is set to the minimum value, the lower digit is also set to" 0000 ... ". Therefore, in double-precision arithmetic, accurate overflow correction is performed.

Further, in the arithmetic unit and the arithmetic method for performing parallel arithmetic, a plurality of arithmetics are simultaneously performed in parallel,
It is possible to process a large number of calculations at high speed, and if an overflow occurs at that time, correct overflow correction is performed for each calculation.

[0028]

【Example】

(First Embodiment) As shown in FIG. 1, the arithmetic unit in the first embodiment of the present invention outputs a value (ffff) as the output of the register 10 when the overflow detection signal 11 is active and the overflow sign signal 12 is positive. When the overflow detection signal 11 is active and the sign signal 12 is negative, a value (0000) is output as the output of the register 10, and when the overflow detection signal is not active, the register 10 is output.
The correction value setting means 13 is provided for outputting the value of as is. Other configurations are the same as those of the conventional device.

As shown in FIG. 2, the correction value setting means 13 outputs "0000 ..." When the overflow code signal 12 is active, and "1111" when the overflow code signal 12 is inactive (0). Outputting correction value output element, output from this element and register
It has a multiplexer to which 10 outputs are input.
The multiplexer selects the output of the correction value output element when the overflow detection signal 11 is active (1), and selects the output of the register 10 when the overflow detection signal 11 is not active (0).

Now, assuming that the number of bits N of data in the memories 1 and 2, buses 3 and 4, ALU 5, registers 9 and 10 is 16 bits, double precision (2N = 3
An operation for adding / subtracting 2-bit data X and Y will be described.

(1) Step of Addition / Subtraction of X and Y Lower Side Data First, lower 16 bits of data XL of the data X is read from the memory 1 and output to the bus 3. Further, the lower 16 bits of data YL of data Y are read from the memory 2 and output to the bus 4. The ALU 5 performs addition and subtraction of XL and YL, and outputs the result to the register 10 via the maximum / minimum value setting means 8.
To store. The carry generated in the most significant bit is stored in the carry flag register 7. At this time, the maximum value / minimum value setting means 8 outputs the output of the ALU 5 to the register 10 as it is.

(2) Step of Addition / Subtraction of Higher-Order Data of X and Y: First, the upper 16-bit data XU of the data X is read from the memory 1 and output to the bus 3. Further, the upper 16 bits of data YU of data Y are read from memory 2 and output to bus 4. The ALU 5 performs addition / subtraction of the values of the XU, YU and carry flag register 7, and stores the result in the register 9 via the maximum / minimum value setting means 8.

At this time, the overflow detecting means 6 is
When the calculation result of the ALU 5 overflows, the overflow detection signal 11 and the overflow code signal 12 indicating the direction of the overflow are output. The maximum value / minimum value setting means 8 is a maximum positive value (7ff) when the overflow detection signal 11 is active and the overflow sign signal 12 is positive.
f) is output, and when the overflow detection signal 11 is active and the overflow sign signal 12 is negative, the minimum negative value (8
000) is output, and if the overflow detection signal 11 is not active, the output of the ALU 5 is output as it is.

The correction value setting means 13 to which the overflow detection signal 11 and the overflow code signal 12 are input from the overflow detection means 6
When 11 is active and overflow sign signal 12 is positive, the value (ffff) is set as the output of register 10. When overflow detection signal 11 is active and sign signal 12 is negative, the value (0000) is output from register 10. Set as. When the overflow detection signal 11 is not active, the value of the register 10 is output as it is.

By the operations of the above steps (1) and (2), addition / subtraction of double precision data is performed.

Therefore, when the maximum value / minimum value setting means 8 corrects the upper data of the calculation result at the time of overflow, the correction value setting means 13 corrects the lower data of the calculation result, whereby the addition / subtraction result is When overflowing in the positive direction, the maximum positive value of 32 bits (7fffff
ff) is output and the addition / subtraction result overflows in the negative direction, the 32-bit negative minimum value (80
000000) is output.

The value set by the correction value setting means 13 may be stored in the register 10.

As described above, the arithmetic unit of the first embodiment can accurately perform overflow correction when adding / subtracting double-precision data. Further, this correction is executed at a high speed of 2 steps.

(Second Embodiment) In the second embodiment, the correction value setting means 13 in the first embodiment is constructed integrally with the register 10.

This device, as shown in FIG.
10 is composed of a D latch with a set / reset function.

The data from the maximum / minimum value setting means 8 is input to the data input terminal D of the register 10, and this data is obtained when the write enable terminal E is active.
It is written in the register 10 and output from the data output terminal Q to the bus 3.

When the overflow detection signal 11 becomes active and at the same time the overflow code signal 12 becomes active, the reset terminal R becomes active, the register 10 is reset to "0000", and the data output terminal Q
Outputs "0000".

When the overflow detection signal 11 is active and the overflow code signal 12 is inactive, the set terminal S becomes active, the register 10 is set to "ffff", and the data output terminal Q outputs "ffff". Is output.

As a result, when the maximum value / minimum value setting means 8 corrects the upper data of the calculation result stored in the register 9 to the maximum value or the minimum value at the time of overflow,
The lower-order data of the operation result stored in the register 10 is “f
It is corrected to "fff" or "0000".

(Third Embodiment) The arithmetic unit of the third embodiment is
It is possible to select and process double-precision operations and parallel operations in which two operations with a bit width that is half the bit width of the operation device are executed in parallel at the same time. Can be done.

As shown in FIG. 4, this arithmetic unit is an ALU having a structure in which two 8-bit wide ALUs are arranged in parallel.
5 and the carry value of the most significant digit of the operation result of the ALU5 are output as the overflow code signal 12, and when the carry value of this most significant digit and the carry value from the preceding digit are 0, , The first overflow detection means 6 which outputs the overflow detection signal 11 of 1 when they do not match, and the carry value of the 8th bit from the lower side of the operation result of the ALU 5 are output as the overflow code signal 16.
Second overflow detection means 14 which outputs an overflow detection signal 15 of 0 when the value of the carry of the 8th bit from the lower side and the value of the carry from the digit of the 7th bit match, and 1 when they do not match. And the maximum or minimum value that outputs the maximum value or the minimum value according to the double precision arithmetic operation or the parallel arithmetic operation when the overflow occurs and outputs the arithmetic result of the ALU5 when the overflow does not occur. The setting means 8 is provided. The other structure is the same as that of the arithmetic unit of the first embodiment.

The structure of the first overflow detecting means 6 is the same as that shown in FIG. Further, as shown in FIG. 5, the second overflow detecting means 14 outputs the carry value of the 8th bit from the lower side of the operation result of the ALU 5 as an overflow code signal 16 indicating the direction of overflow (direction of overflow). Is 0 when it is positive, 1 when it is negative), and 0 when the value of the carry of the 8th bit from the lower order and the value of the carry from the 7th bit are equal, and when they do not match. The overflow detection signal 15 of 1 is output.

Further, the maximum value / minimum value setting means 8 sets "10000000" (8-bit negative minimum value) when the overflow code signal 16 is 1, and the overflow code signal 16 as shown in FIG. When is 0, "0111
1111 "(8-bit positive maximum value) for outputting the maximum-minimum value output element 81, and when the overflow code signal 12 is 1," 1000000000000000 "(16-bit negative minimum value), and overflow code signal
"01111111111111111" when 12 is 0
The maximum value minimum value output element 82 that outputs (16-bit positive maximum value), the upper 8 bits of the output of the maximum value minimum value output element 82, and the upper 8 bits of the ALU 5 are input, and the overflow detection signal 11 The multiplexer 8 for selecting them by, the lower 8 bits of the output of the maximum / minimum value output element 82, the output of the maximum / minimum value output element 81 and the lower 8 bits of the ALU 5 are input, and the overflow detection signal 11 or 15 is used. And a multiplexer 83 for selecting them.

The multiplexer 83 selects the upper output of the ALU 5 when the overflow detection signal 11 is 0,
When the overflow detection signal 11 is 1, the upper 8 bits of the output of the maximum / minimum value output element 82 are selected and output. Therefore, the multiplexer 83 determines that the overflow code signal 12 is 1 when the overflow detection signal 11 is 1.
If so, "10000000" (8-bit negative minimum value) is output, and if the overflow code signal 12 is 0, "01111111" (8-bit positive maximum value) is output.

When the control section (not shown) instructs parallel operation, the multiplexer 84 outputs the lower side output of the ALU 5 or the output of the maximum / minimum value output element 81 according to the overflow detection signal 15. If any one of them is selected and the overflow detection signal 15 is 0, the operation result of the lower side of the ALU 5 is output, and when the overflow detection signal 15 is 1, if the overflow code signal 16 is 1, then "10000000" ( 8-bit negative minimum value)
If the overflow code signal 16 is 0, “0111
1111 ”(8-bit positive maximum value) is output.

On the other hand, when the control unit (not shown) does not instruct parallel operation, the multiplexer 84 receives the overflow detection signal 11 and outputs the lower side of the ALU 5 or the lower side 8 of the maximum / minimum value output element 82. When any one of the bit outputs is selected and the overflow detection signal 11 is 0, the lower side output of the ALU 5 is output, and when the overflow detection signal 11 is 1, if the overflow code signal 12 is 1, then "00000000". , And if the overflow code signal 12 is 0, “11111111” is output.

When performing a double precision operation with this arithmetic unit, the lower 16 bits of data XL of the 32-bit data X is read from the memory 1 and the lower 16 bits of data Y of the 32-bit data Y is read from the memory 2. Read YL,
1 using one (lower side) of two 8-bit wide ALUs
The operation from the 8th bit to the 8th bit is performed, and the operation from the 9th bit to the 16th bit is performed using the other (upper side) ALU. At this time, the carry value of the 8th bit of the lower ALU is added to the operation of the 9th bit of the upper ALU. The carry generated in the 16th bit on the upper side is stored in the carry flag register 7.

The calculation result of the lower ALU is input to the multiplexer 84 of the maximum / minimum value setting means 8, and the upper A
The calculation result of LU is input to the multiplexer 83. At this time, the multiplexers 83 and 84 select the outputs of the upper side ALU and the lower side ALU as they are, and the maximum value / minimum value setting means 8 outputs 16-bit data combining them and stored in the register 10. .

Next, the upper 16-bit data XU of the data X is read from the memory 1, the upper 16-bit data YU of the data Y is read from the memory 2, and two ALUs each having an 8-bit width are used. The values of XU, YU and carry flag register 7 are added and subtracted, and the operation result of the upper ALU is set by multiplexer 83 of maximum value / minimum value setting means 8.
In addition, the operation result of the lower ALU is output to the multiplexer 84.
To enter.

At this time, the overflow detecting means 6 is
If the operation result of the upper ALU overflows,
An overflow detection signal 11 and an overflow code signal 12 indicating the direction of overflow are output. When the overflow detection signal 11 is output, the multiplexer 83 of the maximum value / minimum value setting means 8 outputs the 16-bit positive maximum value or negative value output from the maximum / minimum value output element 82 in accordance with the overflow sign signal 12. The upper 8 bits of the minimum value are selected and output, and the multiplexer 84 to which the double precision operation is designated selects and outputs the lower 8 bits of the 16 bits. As a result, when an overflow occurs, the maximum value / minimum value setting means 8 outputs the combined 16-bit maximum value or minimum value and stores it in the register 9.

When no overflow occurs, the multiplexers 83 and 84 output the operation results of the upper side and the lower side of the ALU, respectively, and combine them into 1
6-bit data is stored in the register 9.

When an overflow occurs, as in the case of the first embodiment, the overflow detection signal 11 and the overflow code signal 12 output from the overflow detection means 6 are input to the correction value setting means 13 to set the correction value. The means 13 corrects the value stored in the register 10 to (ffff) or (0000).

As described above, in the arithmetic unit of the third embodiment,
In the double-precision calculation, accurate overflow correction can be performed as in the device of the first embodiment.

Next, the operation in the case where the operation with the half bit width of the operation device is performed twice in parallel will be described.

Four data XU ', X having an 8-bit width
For L ', YU', YL ', XU' + YU 'and X
Two additions of L '+ YL' are performed as follows. Data XU ′ is stored in the upper 8 bits of the memory 1 and data XL ′ is stored in the lower 8 bits of the memory 1 in advance.
It is assumed that data YU ′ is stored in the upper 8 bits and data YL ′ is stored in the lower 8 bits. First, the data of XU ′ and XL ′ are read out simultaneously from the memory 1 via the 16-bit bus 3 and input to the right side of the ALU 5. Further, the data of YU 'and YL' are simultaneously read from the memory 2 via the 16-bit bus 4 and input to the left side of the ALU 5.
The ALU 5 performs an operation of XU '+ YU' on its upper side, and in parallel performs an operation of XL '+ YL' on its lower side. At this time, the carry value input to the lower 8th bit to the 9th bit of the ALU is set to 0.

The first overflow detecting means 6 is AL
When the operation result of the upper side of U5 overflows,
An overflow detection signal 11 and an overflow code signal 12 indicating the direction of overflow are output. When the overflow detection signal 11 is output (becomes active),
When the overflow sign signal 12 is positive, the multiplexer 83 of the maximum value / minimum value setting means 8 outputs the upper 8 bits of the 16-bit positive maximum value output from the maximum / minimum value output element 82.
Select and output bit (01111111),
When the overflow code signal 12 is negative, the upper 8 bits (10000000) of the 16-bit negative minimum value are selected and output.

When the overflow detection signal 11 is not active, the multiplexer 83 outputs the upper side output of the ALU 5 as it is.

On the other hand, the second overflow detecting means 14
Outputs an overflow detection signal 15 and an overflow code signal 16 indicating the direction of overflow when the lower-order operation result of the ALU 5 overflows. When the overflow detection signal 15 is output, the multiplexer of the maximum value / minimum value setting means 8 instructed to perform parallel operation.
84 selects and outputs the 8-bit positive maximum value (01111111) output from the maximum value minimum value output element 81 when the overflow code signal 16 is positive, and outputs it when the overflow code signal 16 is negative. , 8-bit negative minimum value (1
(0000000) is selected and output. When the overflow detection signal 15 is not active, the lower side output of the ALU 5 is output as it is.

The outputs of the multiplexer 83 and the multiplexer 84 are put together into 16-bit data,
It is stored in the register 9.

Thus, in the arithmetic unit of the third embodiment, 1
In the step, two 8-bit width additions can be performed simultaneously, and when overflow occurs in each operation, accurate overflow correction can be performed.

In the third embodiment, the maximum value / minimum value output element 81 and the multiplexer 84 for performing the 8-bit overflow correction of the lower operation result of the ALU 5 are provided inside the maximum value / minimum value setting means 8. It is also possible to change these so as to be provided inside the correction value setting means 13. In that case, the upper 8 bits of the register 10 store the upper 8 bits of data of the ALU 5 that has been subjected to overflow correction using the maximum / minimum value output element 82 and the multiplexer 83, and the lower 8 bits are stored in the lower 8 bits. The output of the lower 8 bits of the ALU 8 is stored as it is. Then, the overflow detection signal 15 and the overflow code signal 16 output from the overflow detection means 14 are added to the correction value setting means 13
When the data is input to the register 10, the data is read from the register 10 and output to the bus 3, the correction value setting means 13 outputs the upper 8 bits of the register 10 as they are, and the lower 8 bits of the register 10 data. In this case, overflow correction is performed according to the procedure described above.

Further, in the third embodiment, an example in which an 8-bit operation is simultaneously performed twice by the ALU 8 which performs a 16-bit operation has been described, but it can be applied to an operation having a higher degree of parallelism. . For example, even when four 4-bit operations are performed in parallel, if four overflow detection means and four maximum value / minimum value setting means are provided in parallel, the parallel operation and the overflow correction can be similarly performed at high speed. Moreover, it can be done accurately.

[0068]

As is apparent from the above description of the embodiments, the arithmetic unit and the arithmetic method of the present invention can accurately and promptly perform overflow correction when computing double-precision data.

By simultaneously performing parallel operations with a bit width smaller than that of the arithmetic unit, it is possible to speed up the processing such as Viterbi decoding which requires a large number of operations, and Accurate overflow correction can be performed with respect to the occurrence of overflow in calculation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic unit according to a first embodiment of the present invention,

FIG. 2 is a block diagram showing a correction value setting means of the arithmetic unit,

FIG. 3 is a block diagram showing a correction value setting means of an arithmetic unit according to a second embodiment of the present invention,

FIG. 4 is a block diagram showing a configuration of an arithmetic unit according to a third embodiment of the present invention,

FIG. 5 is a block diagram showing a second overflow detecting means of the arithmetic unit according to the third embodiment;

FIG. 6 is a block diagram showing maximum value / minimum value setting means of the arithmetic unit of the third embodiment;

FIG. 7 is a block diagram showing a configuration of a conventional arithmetic unit,

FIG. 8 is a block diagram showing the configuration of overflow detection means of a conventional arithmetic unit;

FIG. 9 is a block diagram showing a configuration of maximum value / minimum value setting means of a conventional arithmetic device.

[Explanation of symbols]

1, 2 memory 3, 4 bus 5 ALU 6,14 Overflow detection means 7 Carry flag register 8 Maximum value Minimum value setting means 9, 10 registers 11, 15 Overflow detection signal 12, 16 Overflow sign signal 13 Correction value setting means 81, 82 Maximum value Minimum output element 83, 84 multiplexer

Claims (20)

(57) [Claims] 1. A first register for storing the operation result of the upper digit of double-precision data, a second register for storing the operation result of the lower digit of double-precision data, and overflow detection for detecting overflow of the operation result. And a maximum value / minimum value setting means for outputting a maximum value or a minimum value to the first register based on the detection result of the overflow detection means, wherein the detection result of the overflow detection means is used. The arithmetic unit is provided with a correction means for setting the output value of the second register to data in which all bits are 0 or 1. 2. An arithmetic result overflow is detected when a high-order digit of a double-precision data is calculated in a double-precision data arithmetic method in which an operation of a high-order digit and an operation of a low-order digit of double-precision data are performed a plurality of times. Then, based on the detection result of the overflow, the arithmetic result of the upper digit is set to the maximum value or the minimum value, and the arithmetic result of the lower digit is set to data in which all bits are 0 or 1. Calculation method. 3. The bit width of data handled by one arithmetic unit
Multiple data, including multiple data, read simultaneously from memory.
Perform multiple operations on a number of data in parallel and check for overflow in each of the multiple operations.
Depending on the maximum value as a result of each of the plurality of operations
Or a computing device that outputs the minimum value . 4. The arithmetic unit further comprises a bit of data to be arithmetically operated by one arithmetic unit.
Performs operations on the width equal to the data, over at operations on data equal to the bit width
Depending on the presence / absence of flow, data with the same bit width as
Output the maximum or minimum value as the result of the operation
Data that can be processed and is equal to the multiple data or the bit width.
The arithmetic unit according to claim 3, which is capable of selecting an arithmetic operation for it. 5. The result of the plurality of operations is one register
The arithmetic unit according to claim 3, which is stored in a computer. 6. A result of an operation on the plurality of data,
Same as the result of operation on data with the same bit width
Flip stored in the register, before the lower side when performing operations on the plurality of data
Judgment of overflow based on the result of arithmetic operation
However, when an overflow occurs, the operation on the lower side is performed.
As a result, the maximum or minimum value is set to the lower side of the register.
Stored in, when performing operations on data equal to the bit width
Based on the result of the operation on the data with the same bit width
Check whether there is an overflow,
When it occurs, the performance for the data equal to the bit width is generated.
The lower side of the maximum value or the minimum value as the calculation result is the register
The data is stored in the lower side of the data.
Arithmetic unit . 7. A plurality of operation results to be stored in a register are obtained.
Multiple operations in parallel to determine whether there is an overflow in each of the multiple operations.
Depending on the maximum as a result of each of the plurality of operations
The storage of the value or the minimum value and the operation for obtaining one operation result stored in the register.
Overflow in the calculation to obtain one of the above calculation results.
Depending on the presence or absence of
Whether to store the maximum or minimum value as the result of arithmetic
Is possible, and in the case of performing the plurality of operations, one of the plurality of operations on the lower side is
The presence or absence of overflow is judged based on the result, and the overflow
-When a flow occurs, as the calculation result of the lower side
When storing the maximum value or the minimum value in the lower side of the register and performing the operation for obtaining the one operation result,
The presence or absence of overflow can be determined based on the result of one operation.
If there is a disconnection and an overflow occurs,
The lower side of the maximum or minimum value as the calculation result for
Is stored in the lower side of the register.
Arithmetic unit . 8. A bit of data handled by the one arithmetic unit
The width stores the result of the operation on the plurality of data.
Characterized in that equal to the bit width of one of the registers that
The arithmetic unit according to claim 6 . 9. The maximum value is a positive maximum value.
The small value is the negative minimum value.
On-board computing device . 10. The maximum or minimum value of the calculation
The bit width is set according to any one of claims 3 to 8.
Computing device . 11. The method according to any one of claims 3 to 10.
DSP for built-in equipment with built-in arithmetic unit . 12. A bit width of data handled by one arithmetic unit
Read multiple data from memory at the same time
Perform multiple operations on multiple data in parallel, and check for overflow in each of the multiple operations.
Depending on the maximum value as a result of each of the plurality of operations
Or the calculation method that outputs the minimum value . 13. The operation method further comprises a bit of data to be operated by one operation unit.
Performs operations on the width equal to the data, over at operations on data equal to the bit width
Depending on the presence / absence of flow, data with the same bit width as
Output the maximum or minimum value as the result of the operation
Data that can be processed and is equal to the multiple data or the bit width.
The calculation method according to claim 12, wherein a calculation for the same can be selected. 14. The result of the plurality of operations is one register.
The calculation method according to claim 12, wherein the calculation method is stored in a star.
Law. 15. The result of the operation on the plurality of data
And the result of the operation on the data equal to the bit width
Stored in the same register, prior to the lower side when performing operations on the plurality of data
Judgment of overflow based on the result of arithmetic operation
However, when an overflow occurs, the operation on the lower side is performed.
As a result, the maximum or minimum value is set to the lower side of the register.
Stored in, when performing operations on data equal to the bit width
Based on the result of the operation on the data with the same bit width
There is judged whether the overflow, overflow is
When it occurs, the performance for the data equal to the bit width is generated.
The lower side of the maximum value or the minimum value as the calculation result is the register
14. The data is stored on the lower side of the data.
Calculation method. 16. A plurality of operation results stored in a register
Perform multiple operations in parallel to obtain the presence or absence of overflow in each of the multiple operations.
Depending on the maximum as a result of each of the plurality of operations
The storage of the value or the minimum value and the operation for obtaining one operation result stored in the register.
Overflow in the calculation to obtain one of the above calculation results.
Depending on the presence or absence of
Whether to store the maximum or minimum value as the result of arithmetic
Is possible, and in the case of performing the plurality of operations, one of the plurality of operations on the lower side is
The presence or absence of overflow is judged based on the result, and the overflow
-When a flow occurs, as the calculation result of the lower side
When storing the maximum value or the minimum value in the lower side of the register and performing the operation for obtaining the one operation result,
The presence or absence of overflow can be determined based on the result of one operation.
If there is a disconnection and an overflow occurs,
The lower side of the maximum or minimum value as the calculation result for
Is stored in the lower side of the register.
Arithmetic method. 17. A data bit handled by the one arithmetic unit
Stores the results of operations on the above multiple data
Equal to the bit width of one register
The calculation method according to claim 15. 18. The maximum value is a positive maximum value, and
18. The minimum value is a negative minimum value.
The calculation method described in Crab. 19. The maximum or minimum value of the calculation
The bit width is set according to any one of claims 12 to 17.
Calculation method described. 20. The method according to any one of claims 3 to 10.
Viterbi decoding processing means for performing ACS operation using arithmetic device
Digital mobile phone with.