JP3460511B2 - IC circuit with pulse generation function and LSI test apparatus using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC circuit with a pulse generating function and an LSI test apparatus using the IC circuit.

[0002]

2. Description of the Related Art An LSI tester for testing a semiconductor device uses a pulse generating circuit, more specifically an IC circuit with a pulse generating function, to generate its test waveform.

FIG. 11 shows a conventional pulse generating circuit.

The pulse generating circuit shown in FIG. 11 comprises a clock counting circuit 21, a delay circuit 22 and a data operation circuit 23.

The data calculation circuit 23 has delay amount data CT and D for the clock counting circuit 21 and the delay circuit 22, respectively.
Is output.

The clock counting circuit 21 uses the delay amount data CT
Based on, the delay of an integral multiple of the master clock is realized.

The delay circuit 22 realizes a delay equal to or less than the master clock based on the delay amount data D.

The counting clock 21-1 output from the clock counting circuit 21 is also used as an internal operation clock of the data arithmetic circuit.

Next, the operation of the pulse generating circuit of FIG. 11 will be described with reference to FIGS. 12 and 13.

FIG. 12 shows an example in which the delay amount data is 0.

When the master clock 6 as shown in FIG. 12 is input, the delay amount data which the data operation circuit 23 gives to the clock counting circuit 21 and the delay circuit 22 is (CT
(0), D (0)), the output pulse is delayed by the propagation delay time (Tpd1 + Tpd2) required until the master clock is input and generated as the output pulse.

This propagation delay time is a clock passage time that occurs even if the time data to be delayed in the pulse generator is 0, and is hereinafter referred to as an offset delay time.

Next, in FIG. 13, the delay amount data is (CT
(1), D (0.5)) is an example.

When the master clock 6 as shown in FIG. 13 is input, the clock counting circuit 21 first counts the master clock 6 by 1 based on the delay amount data CT (1) given from the data operation circuit 23. Delay by minutes.

Next, in the delay circuit, the data operation circuit 23
Based on the delay amount data D (0.5) given by the above, the pulse delayed by one count in the clock counting circuit is further delayed by a half cycle of the master clock 6. Therefore, the delay time from the reference time is Tpd1 + CT
(1) + Tpd2 + D (0.5).

Now, such a pulse generating circuit is
In the case of a semiconductor element in which a switching current flows every time the internal logic such as OSLSI transitions,
The power supply voltage fluctuates significantly, the signal propagation delay time of the internal circuit of the pulse generation circuit fluctuates, and the pulse generation accuracy deteriorates.

For example, the overall circuit scale of the pulse generation circuit of FIG. 11 is set to 1, and the ratio of the circuit scale of the data operation circuit 23 and the delay circuit 22 which are the internal blocks is 0.
9. If the ratio of the clock counting circuit 21 is set to 0.1 and only the clock counting circuit 21 is designed to always operate,
When it is considered that the scale of the operating circuit is proportional to the current consumption, the current consumption of the entire pulse generation circuit is changed from 0.1 to 1 by generating the desired coefficient clock (by changing the internal logic). Change, and the pulse generation accuracy deteriorates. That is, the power supply pin (V
The transient current (Δi / Δt) flows in the L component (inductance) between the (CC) and the ground pin (GND), causing an inductive voltage ΔV (= -L · Δi / Δt) to occur, and the pulse generation accuracy. Deteriorates. This voltage ΔV
Occurs due to a delay in the current supply response from the DC power supply, etc., and a considerable difference occurs when the LSI is mounted.

FIG. 14A shows, as an example thereof, a power supply voltage fluctuation between VCC and GND immediately after generation of the count clock of the pulse generation circuit. This is an example in which the data operation circuits 23 are simultaneously operated to generate the counting clock, and it can be seen that a transient current flows between VCC and GND, and the power supply voltage VCC fluctuates.

As a method of reducing the fluctuation of the power supply voltage, as shown in FIG. 15, a capacitor 1 is connected between the power supply and GND.
There is a method of inserting 6 (hereinafter abbreviated as “decap”) to suppress the transient current change of the power supply voltage.

[0020]

However, the decap 16
Is effective in reducing the integral component of power supply voltage fluctuation, but it is difficult to reduce power supply voltage fluctuation that is greater than or equal to the frequency response of the capacitor. That is, in the decap 16, the electric charge is charged by the decap after the current change occurs, so that the power supply voltage cannot be brought into a steady state faster than the charging speed.

FIG. 14B shows an example of power supply voltage waveforms when the bypass capacitor is mounted and when it is not mounted.

As can be seen from the figure, since the bypass capacitor 16 cannot reduce the fluctuation of the power supply voltage in the time zone longer than the frequency response, the pulse generation accuracy of the pulse generation circuit in that time zone is not improved. That is, the power supply voltage fluctuates only during the time when the decap 16 charges the electric charge.

Further, in recent semiconductor devices, the operating speed tends to increase more and more, and it is not possible to supply a highly accurate pulse to such a semiconductor device by using the current decaps alone, and it Reliable test results cannot be obtained.

It is an object of the present invention to provide a new pulse generating function for reducing the fluctuation of the power supply voltage caused by the current change.

It is another object of the present invention to provide a highly reliable LSI test apparatus having the above-mentioned pulse generation function.

[0026]

SUMMARY OF THE INVENTION The present invention comprises a pulse generating circuit for generating a desired pulse and a current consuming circuit for consuming a predetermined current as necessary. The above object is achieved by controlling the sum of the consumption current of the current consumption circuit and the current consumption circuit to fall within a predetermined range.

As described above, in the entire circuit including the pulse generation circuit and the current consumption circuit, if the consumed current is kept within the allowable range, the change in current per unit time is reduced and the fluctuation of the power supply voltage is suppressed. can do. That is, it becomes possible to realize a desired pulse generation accuracy.

For example, when the desired semiconductor element varies in propagation delay time per unit voltage at the change rate b, the error time (Terr) of the pulse generation of the output pulse from the pulse generation circuit is Terr = It can be expressed as propagation delay time when output pulse passes through LSI × b × variable voltage. Here, the above-mentioned Terr should originally indicate the time that the power supply voltage fluctuates in an extremely short time zone, but it may change depending on various conditions such as the circuit configuration of the pulse generation circuit and the cycle of the input master clock. Therefore, b is used here for convenience.

Therefore, the fluctuating propagation delay time changes depending on the fluctuation voltage of the power supply voltage (the fluctuation of the current flowing between the power supply pin and GND), so that the pulse generation accuracy of the pulse generation circuit is set to ± a seconds or less. Then, the fluctuation voltage of the power supply voltage is <a / (propagation delay time through which the output pulse passes × b). The pulse generation accuracy of the pulse generation circuit is
There is a case where it is guaranteed at the + 1st pulse generation interval, and a case where it is decided that the nth pulse is generated within a required accuracy at a desired time from a predetermined reference time (reference clock). The arithmetic expression is an example in which the accuracy of the pulse generation circuit is kept within ± a seconds in the latter case.

Further, according to the present invention, the sum of the current consumption of the pulse generation circuit and the current consumption of the current consumption circuit is within a predetermined range with respect to the period including the period before and after the pulse is generated. It is preferable to control. This is because if the current consumption circuit is operated for a required period in this way, low power consumption of the entire circuit can be achieved.

Further, according to the present invention, the data calculation means for generating a pulse generated in a desired cycle or a pulse delayed from the reference signal by a desired time, and the master clock of the master clock by the first data from the data calculation means. Count an integer multiple
Te clock counting means for generating a pulse in the pulse generating circuit which operates in synchronization with the master clock composed of pulse delay means for creating a second I Ri delay amount data from said data operation means, said a first detecting means for the rate of change of (an operating rate that proportion to changes circuit operates below) circuitry of the pulse generating means is operated to advance detects that changes closely from the crude, the pulse based on the detection signal of the second detecting means and, said first detecting means or said second detecting means changes in dynamic <br/> operation rate of the generator is detected in advance that changes from dense to coarse A current consumption means for consuming a predetermined current, the current consumption means is operated based on a detection signal from the second detection means, and the current consumption is based on a detection signal from the first detection means. Even by stopping the means It is possible to achieve the purpose.

Alternatively, the data calculating means for generating a pulse generated at a desired cycle or a pulse delayed for a desired time from a reference signal and the first data from the data calculating means counts an integral multiple of the master clock. clock counting means for generating a pulse and, in the pulse generating circuit which operates in synchronization with the master clock composed of pulse delay means for creating a second I Ri delay amount data from said data operation means, A detection unit that detects a period other than the period of the master clock at which the count completion signal of the clock counting unit is output, and an output that is the logical product of the output of the detection unit and the master clock or a clock having a desired generation period. To achieve the above object by providing a clock generating means for generating and a current consuming means for operating by the clock generating means. It can be.

The first detection means stores the first set time from the pulse generation time stored in advance that the change of the operation rate of the internal logic realizing means of the pulse generation means changes from coarse to dense. The second detection means sets a second setting from a pulse generation time stored in advance that the change of the operating rate of the internal logic realizing means of the pulse generation means changes from dense to coarse. It may be detected based on time.

Further, the first detecting means is configured to store the change in the operating rate of the internal logic realizing means of the pulse generating means from coarse to dense, based on the pulse generation times stored in advance. The second detection means detects that the change of the operating rate of the internal logic realizing means of the pulse generation means changes from dense to coarse from the pulse generation time stored in advance. The current consumption means may be operated / stopped in multiple stages by performing detection based on the second and fourth set times.

In this way, the pulse generation circuit operates in multiple stages /
If stopped, the current consuming means can be operated for a required period, leading to lower power consumption.

Further, a plurality of the current consuming means are provided,
The operation / stop cycles of the plurality of current consuming means may be different. If there are a plurality of current consuming means,
This is because it is possible to reduce the current consumption rate per unit time when the current consumption means is operated.

On the other hand, if such a pulse generating circuit is applied to an LSI test apparatus, a highly accurate test pattern can be generated and a highly reliable LSI test can be realized. In addition, a pulse or reference signal generated at a desired cycle
To generate the desired time-delayed pulse from
By the calculation means and the first data from the data calculation means
A clock that generates a pulse by counting an integer multiple of the master clock.
The lock counting means and the second data from the data calculating means
Pulse generation with delay means to generate delay amount by
Circuit and whether or not the pulse generation circuit is operating.
The output detection circuit and the signal detected by the detection circuit
Based on the LSI test that has a current consumption circuit that consumes current
Highly reliable LSI test can be realized by the test equipment.
Wear. Also, in the above LSI test apparatus, the pulse
When the generation circuit is stopped, the current consumption circuit operates and the power consumption circuit
The current consumption circuit is stopped when the loose generation circuit operates.
Highly reliable LSI test can be realized by LSI.
Wear.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a master clock 6 is counted and predetermined by a data operation circuit 23 for calculating the generation time of an output pulse and output data CT from the data operation circuit 23. , A pulse generation circuit 2 including a clock counting circuit 21 for passing a master clock when counting, a delay circuit for outputting a pulse by delaying an output clock of the clock counting circuit 21 by a predetermined value of the data D, and the data operation circuit. An operation rate detection circuit 4 for detecting the operation rate of the pulse generation circuit 2 (the ratio of the circuit to the switching circuit in the entire circuit is taken as the operation rate) based on the data from 23, and its detection signal. The transient current reduction circuit 3 is composed of a current consumption circuit 5 that consumes a current.

In such a configuration, the operation detection circuit 4
Detects the operating rate of the pulse generation circuit 2 and operates the current consumption circuit 5 that consumes current according to the detection result, thereby limiting the transient current generated in the entire LSI 1 including the pulse generation circuit within a predetermined range. To reduce potential fluctuations.

FIG. 2 shows the operating state of the LSI 1. The horizontal axis shows the time, and the vertical axis shows the current consumption value of the pulse generation circuit 2 and the transient current reduction circuit 3 and the power supply voltage value.

In the circuit shown in FIG. 1, control is performed so that the current consumption value in the transient current reduction circuit 3 and the current consumption value in the pulse generation circuit 2 have completely opposite characteristics as shown in FIG. 2 (a). Therefore, the current change value of the entire LSI 1 including the pulse generation circuit 2 and the transient current reduction circuit 3 (VCC / GN of the LSI)
The value of the current flowing between D) is a substantially constant value, as shown in FIG.

As described above, it can be seen that if the current value changing in the entire circuit is constant, that is, if there is no abrupt current change, the power supply voltage fluctuation due to it is reduced as shown in FIG. 2 (c).

The allowable power supply voltage fluctuation range in the figure is set so that the pulse generation accuracy is always ± a seconds or less.

Next, an example of the transient current reducing circuit 3 will be described with reference to FIGS.

FIG. 3 shows a pulse generation circuit 2 and an operation rate detection for outputting an operation signal to the current consumption circuit 5 by calculating the fluctuation of the internal operation rate which occurs when the pulse is generated from the data A23-2 which is the output time of the pulse. The circuit 4. This is a circuit that controls the operation / stop of the current consumption circuit in accordance with the operation / stop of the pulse generation circuit 2 to make the current consumption of the entire circuit substantially constant.

The pulse generation circuit 2 includes a data calculation circuit 23 that outputs time data (delay amount data) for performing a calculation process to generate a pulse, a clock counting circuit 21 that delays based on the time data, and its clock. Counting circuit 2
The delay circuit 22 delays the output pulse from 1 by the amount of the data D of the data operation circuit 23 (the delay amount equal to or less than the master clock period).

The structure of the clock counting circuit 21 is as follows.

The counter 211 that outputs the data counted by the master clock 6, the FF 212 that latches the data (CT, D) 23-1 from the data operation circuit, and the output data of the FF 212 are compared with the output data of the counter 211. And a coincidence detector 213 that outputs a coincidence signal H only when they coincide with each other, an FF 214 that latches the signal from the coincidence detector 213, and an AND 215 that passes the master clock 6 next to the latched timing.

Next, the operation rate detection circuit 4 is connected to the current consumption circuit 5
Signal generation circuit A41 that outputs a stop signal to stop
And a signal generation circuit B42 which outputs a start signal for starting the current consumption circuit 5, and a consumption clock generation circuit 43 which selectively outputs the above-mentioned stop signal and start signal to the current consumption circuit 5.

The signal generating circuit A41 has a register 411 in which a predetermined value is written, an adder 412 for adding the data A23-2 from the data arithmetic circuit and the output data of the register 411, and an FF 413 for latching the output. The output of the counter 211 is compared with the output of the counter 211, and a coincidence detector 414 that outputs a coincidence signal H only when they coincide with each other; an FF 415 that latches the output on the opposite phase side of the master clock;
Pass the master clock when the output of the FF is H. A
It consists of ND416.

Similarly, the signal generation circuit B42 loads the value of the register 421 into which a predetermined value has been written and the value of the 421 register when the coincidence detector 213 outputs H, down counts the value and indicates TC (0). Terminal count 42
2-1), a down counter 422, and an AND 423 for passing the master clock 6 by its TC.

Finally, the consumption clock generation circuit 43 is reset by the output of the AND 416 which is the stop signal and is set by the output of the AND 423 which is the start signal.
And an AND 432 through which the master clock is passed by the output of the FF 431.

With such a circuit configuration, the operation detection circuit 4 detects the internal operation rate of the pulse generation circuit 2 and controls the operation / stop of the current consumption circuit 5 based on the detection result.

The control operation will be described with reference to FIG.

FIG. 4 shows the operation timing of each part of the circuit shown in FIG.

First, the master clock 6 continuously generates pulses at the timing shown in the figure. Counter 21
1 counts the pulses of the master clock 6. For example, counting is performed as 0, 1, 2, 3, ... At this time, the data operation circuit 23 outputs the timing data 23-1 and 23-2 in synchronization with the divided clock. In this embodiment, 7, B, F ---- are sequentially output as delay amount data (timing data).

The FF 212 latches its outputs 2, 7 and B ---- in order.

The coincidence detector 213 outputs only the cycle in which the output of the counter 211 and the output of the FF 212 latching the output of the data operation circuit coincide with each other (not shown).

The cycle output in this way is FF2
After being latched by 14, it is output as the counting clock 21-1 via the AND 215.

That is, the pulse generation circuit 2 of the present embodiment
Outputs the next pulse of the master clock that coincides with the timing data as the counting clock 21-1 according to the timing data output from the data arithmetic circuit 23.

Next, the operation of the operation rate detection circuit 4 is as follows.

The timing data from the data operation circuit is sent to the adder 412 in the signal generation circuit A included in the operation detection circuit 4 as in the pulse generation circuit.

The stored value -1 is stored in the register 411 and sent to the adder 412.

The adder 412 has its timing data A
23-2 and the added value of the value stored in the register 411-1, E,
--- is calculated in order.

The calculation results 1, 6 and A ---- are FF4.
It is latched at 13 and input to the coincidence detector 414.

The value of the counter 211 provided in the pulse generation circuit is also input to the coincidence detector 414, and only the cycle in which the respective data coincide is output (not shown).

The cycle output in this way is FF4
After being latched by 15, it is output as a stop signal 416 via the AND 416.

That is, in the present embodiment, the register 41
Since -1 is stored in 1, the pulse generation timing of the stop signal, which is the output of the signal generator A, is 1 more than the pulse generation timing of the pulse generation circuit (clock counting circuit).
The stop signal is output earlier by the clock.

Similarly, the signal generating circuit B includes a register 42.
The stored value 2 stored in 1 is input to the counter 422.

The output data B213 of the coincidence detector 213 of the pulse generation circuit is also input to the counter 422, and when the value is H, the stored value 2 of the register 421 is loaded and subtracted according to the master clock 6 to become 0. TC4 at the time
22-1 is output.

The AND circuit 423 outputs the logical product of the signal from the TC and the signal from the master clock as a start signal.

That is, the signal generating circuit B outputs the start signal delayed by 2 clocks stored in the register 421 from the timing of generating the pulse of the pulse generating circuit.

In the consumption clock generation circuit 43, while the output of the FF 431 by the stop / start signal is H, the master clock is output as the operation clock to operate the current consumption circuit 5.

According to the above operation procedure, the current consumption circuit 5 causes a current to flow through the portion of the pulse generation circuit 2 having a low operation rate, and the current consumption circuit 5 operates a predetermined time before the pulse generation circuit 2 operates (clock is generated). Is stopped (corresponding to the transient current reduction circuit operation stop line in FIG. 2A), and when the operation of the pulse generation circuit 2 ends (current consumption decreases), the current consumption circuit is operated again (FIG. 2 (a) (corresponding to the transient current reduction circuit operation start line), and by reducing the current consumption value per unit time of the entire LSI, it is possible to reduce fluctuations in the power supply voltage of the LSI.

That is, according to the present invention, the fluctuation of the power supply voltage is suppressed by reducing the current change value per unit time generated during the pulse generation (operation) of the conventional pulse generation circuit. If the current consumption circuit is operated when the pulse generation circuit is stopped and the current consumption circuit is stopped when the pulse generation circuit is operated, the current consumption of the entire circuit shown in FIG. 3 can be kept substantially constant. The consumption rate can be reduced.

The values stored in the registers 411 and 421 may be set in advance so as to minimize the fluctuation of the power supply voltage from the characteristics of the current consumption of the pulse generating circuit.

Further, in the present embodiment, the clock counting circuit and the signal generating circuit A have almost the same configuration or have the same configuration, so that the clock counting circuit and the signal generating circuit A are common.
The propagation delays of the two can be made substantially the same, and the control of the entire circuit becomes highly accurate.

Next, another embodiment of the present invention will be described with reference to FIGS.
Will be explained.

FIG. 5 is a circuit diagram in which the operating rate detecting circuit 4 shown in FIG. 3 is replaced with an operating rate detecting circuit 8. The operation rate detection circuit 8 receives the master clock 6 and the inverted output of the FF 214 as an input AN
It is composed of a D circuit 82. That is, the operation rate detection circuit 8 uses the data B21-3 sent from the FF 214 as a change point of the operation rate.

In the present embodiment, the operation clock for operating the current consumption circuit 5 is generated in the cycle of the master clock 6 in which the counting clock is not generated.
Preferably has a current consumption characteristic almost equal to that of the pulse generation circuit 2. As a result, the fluctuation of the power supply is stabilized by causing the current to flow through the entire circuit in synchronization with the master clock 6.

That is, in the present embodiment, a current consumption circuit that has a current consumption equivalent to that of the pulse generation circuit is provided in the master clock cycle in which the pulse generation circuit does not generate a pulse, thereby stabilizing the entire current value. , To reduce fluctuations in the power supply voltage of the LSI.

The operation of the circuit shown in FIG. 5 will be briefly described with reference to FIG.

In FIG. 6, the master clock 6, the counter 211, the timing data 23-1, the coincidence detector 213,
The operations of the FF 214 and the counting clock 21-1 are the same as those in FIG.

A signal obtained by inverting the pulse of the FF 214, which represents the operation timing of the pulse generation circuit, is input to the operation detection circuit 8 as the inverter 81.

The AND 82 performs an AND process on the master clock 6 and the inverter signal and outputs it as the operation clock 82.

The consumption circuit 5 operates / stops based on this output.

That is, when the pulse generating circuit outputs a pulse, the current consuming circuit is controlled to stop, and when the pulse generating circuit does not output a pulse, the current consuming circuit is controlled to operate. For example, the current consumption rate for each cycle of the master clock can be reduced, and the power supply voltage fluctuation can be reduced.

Further, as compared with FIG. 3, a circuit such as a register is unnecessary, so that it is suitable for miniaturization.

Next, another embodiment of the present invention will be described with reference to FIGS.
Will be explained.

FIG. 7 is a circuit diagram in which the operating rate detecting circuit 4 of the embodiment shown in FIG. 3 is used as an operating rate detecting circuit 9, and two signal generating circuits A41 and B42 shown in FIG. 3 are provided. Is.

Signal generating circuit A95, value stored in register-
3. Since 1 is set in the signal generating circuit B97, the start signal is generated 3 cycles before and 1 cycle after the counting clock 21-1 of the pulse generating circuit 2 is output.

Similarly, since the signal generating circuit A94, the value stored in the register-1 and the signal generating circuit B96 are set to 3, the count clock 21-1 of the pulse generating circuit 2 is output 1
A start signal is generated before the cycle and after three cycles.

Since these generated stop / start signals are input to the current consumption circuit via the consumption clock generation circuit, first, the current is generated three cycles before the counting clock 21-1 of the pulse generation circuit 2 is output. The consumption circuit is operated and stopped one cycle before.

Next, the counting clock 21 of the pulse generating circuit 2
The current consumption circuit 5 is operated one cycle after -1 is output, and the current consumption circuit 5 is stopped after three cycles.

That is, the count clock 2 of the pulse generation circuit 2
The current consumption circuit is operated for a certain period immediately before and after the output of 1-1.

Since the purpose of the present invention is to improve the accuracy of pulse generation, it is sufficient that the current value changing per unit time during pulse generation is small.

Therefore, as in the present embodiment, it is sufficient to make constant the current value that changes during a predetermined time immediately before and immediately after the pulse generation period, and conversely, in the other periods, the current consumption circuit Not operating will lead to lower power consumption of the entire circuit.

Since the configurations of the pulse generating circuit 2 and the current consuming circuit are the same as those in FIG. 2, their explanations are omitted.

Next, the operation of the operation detection circuit 9 shown in FIG. 7 will be described with reference to FIG. Since the basic operations of the pulse generating circuit 2 and the signal generating circuits A and B are the same as those in FIG. 4, their explanations are omitted.

As shown in FIG. 8, there are two signal generation circuits A and B for generating a stop signal and a start signal, respectively, and each outputs a signal in accordance with the stored value stored therein.
The current consumption circuit is operated immediately before and after the pulse generation circuit operates, and the current consumption circuit is stopped except immediately before and immediately thereafter.

The principle of the operation rate detection circuit for operating the current consumption circuit immediately before and immediately after the operation of the pulse generation circuit will be described with reference to FIG.

FIG. 9A shows the current consumption of the pulse generation circuit 2 and the current consumption of the transient current reduction circuit 3.
As shown in (a), the stabilizing circuit is operated immediately before and after the pulse generating circuit operates. In this case, the current consumption of the current consumption circuit is about half that of the pulse generation circuit.

The current consumption value in the entire LSI obtained by adding the current amounts of these two circuits is (b), and the one in which only the pulse generation circuit is operated changes by Δi / Δt, whereas the current consumption circuit is changed. It can be seen that the one operating at the same time changes with Δi / Δt2, so that the rate of change of current is also reduced to about one half.

In the present embodiment, as shown in FIG. 9 (C), by allowing the power supply voltage to fluctuate so that the pulse generation accuracy does not exceed ± a seconds, the current consumption circuit is not always operated but the pulse generation circuit is operated. 2 operates immediately before and immediately after outputting the counting clock to reduce abrupt current change.

That is, by using this embodiment, it is possible to reduce the power consumption especially when the pulse generating circuit operates in a long cycle.

Next, another embodiment of the present invention will be described with reference to FIG.

FIG. 10 shows an embodiment of the consumption clock generation circuit and the current consumption circuit. The structure is as follows.

The consumption clock generation circuit receives the start signal / stop signal from the operation rate detection circuit (not shown) as an input.
F101, a shift register that shifts its output signal for each cycle of the master clock, and AND groups 103, 104, 105 provided corresponding to the outputs of the shift register.
And the corresponding current consumption circuit groups 111, 112, 1
It is composed of 13.

This circuit uses the shift register 102 to
The start signal / stop signal output from the FF 101 is output as a signal shifted for each cycle of the master clock.

Since the current consuming circuit group 11 starts / stops the operation in response to the output of the shift register, the current change of the current consuming circuit can be gradually increased / decreased in each cycle of the master clock.

Therefore, in the present embodiment, when the pulse generation circuit becomes large in scale and the current consumption circuit also becomes large in scale, the transient current of the pulse generation circuit is reduced and the voltage caused by the transient current of the current consumption circuit itself is reduced. It can also prevent fluctuations.

That is, since the current consuming circuit group is gradually operated, the current value changing when the current consuming circuit itself operates can be reduced.

It goes without saying that this embodiment can be combined with the embodiments described so far.

Further, in combination with the above-described embodiments, a bypass capacitor may be placed between VSS and GND outside the LSI to reduce the fluctuation of the power supply voltage.

FIG. 16 shows power supply voltage fluctuations when a decap is used in combination with the circuits shown in FIGS.

In the operation mode of this figure, the pulse generation circuit
The output pulse of the pulse generation circuit when operating in a 96 ns cycle and the power supply voltage fluctuation at that time are shown.

FIG. 16A shows a power supply voltage fluctuation only in the bypass capacitor, and the power supply voltage fluctuation when the pulse is output is about 20 mV in pp (Peak to Peak). ) Is a power supply voltage waveform when the stabilizing circuit is operated, and can be reduced to about 10 mV or less in pp.

Further, since such a combination can reduce the transient current, it also has an effect of reducing the number of large-capacity bypass capacitors mounted with good high-frequency characteristics.

The embodiments of the present invention described so far can be easily implemented in a circuit such as a timing generator of an LSI test apparatus which uses a plurality of highly accurate pulse generation circuits.

This means that any one of the embodiments of the present invention may be used to provide the transient current consumption circuit for each timing generation circuit for each pin of the LSI test apparatus.

Next, a sixth embodiment will be described with reference to FIGS. 17 and 18.

This embodiment is different from the embodiment described with reference to FIG. 10 in that the shift register 102 and the AND1
Instead of 03-105, AND10 as shown in FIG.
6. The delay circuit group 107 is used.

AND 106 uses the master clock as FF10.
The output of No. 1 is passed as a gate signal, and the output thereof is further delayed by the delay circuit 107 to be applied to the current consumption circuit 11.

At this time, the delay circuit group 107 delays a desired delay time to operate the current consumption circuit from an arbitrary set timing.

The delay circuit group 107 is also connected in order as shown in the figure to individually control the operation start time of the current consumption circuits 111 to 113.

The delay time setting for the delay circuit group 107 can be easily changed by using a delay amount setting means (not shown) such as a register.

Next, FIG. 18 shows another configuration example of the current consumption circuit group.

Unlike the current consumption circuits 111 to 113 described above, the current consumption circuit 114 does not simply consume the current by operating the fixed circuit number with the signal from the consumption clock generation circuit, but sets the operation circuit. The means 114a is provided to adjust the amount of current consumed in one current consumption circuit.

For example, a setting register is used for the operating circuit setting means 114a, and a logical value H is set for the ANDs 114b and 114c.
Alternatively, a desired current consumption is set by giving L and varying the number of operating circuits.

The present embodiment describes that the consumption clock generation circuit or the current consumption circuit controls the rate of change in the amount of current flowing through the circuit when the transient current prevention circuit starts or stops operating. Therefore, if the LSI 1 as a whole can prevent the transient current, FIG.
It is not limited to the circuit configuration of FIG.

Next, regarding another embodiment of the present invention,
This will be described with reference to FIG.

FIG. 19 is a diagram in which the DC power supply 12 is connected to the LSI 1 and the LSI 1 operates at that time to generate the current Ilsi.

This current Ilsi causes a current fluctuation of ΔIlsi due to a change in the circuit operation rate of the LSI, and
A noise voltage of ΔV = −2L · ΔIlsi / Δt is generated between the current pins of I1, and radiation noise (EMI) is generated. Here, L is the inductance component between the LSI 1 and the DC power supply 12, and the inductance components L on the VCC side and the GND side in this example are the same. It should be noted that ΔIlsi / Δt represents a transient change in the current.

However, L using the embodiment described above is used.
If SI is mounted on a printed circuit board, etc., L · ΔIlsi / Δ
Even if the radiation noise (EMI) caused by t is generated, the voltage fluctuation (noise voltage) ΔV between VCC and GND can be reduced, so that the radiation noise (EMI) can be reduced.

[0136]

According to the present invention, it is possible to reduce a sudden change in the current amount by starting or stopping the current consuming circuit before and after the operation cycle of the pulse generating circuit changes. It is possible to reduce the fluctuation of the power supply voltage that is caused.

In particular, according to the present invention, in a circuit such as a high-accuracy pulse generating circuit which requires high accuracy in the generation time of the output signal, the fluctuation of the internal propagation delay time due to the fluctuation of the power supply voltage is significantly reduced. it can.

Further, according to the present invention, the ratio of the operating circuits varies, so that the noise voltage caused by the current variation generated between the power supply grounds of the circuits is reduced, so that an EMC (Electoromagnetic compatibility) countermeasure can be taken. It will be possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing a detailed example of the first embodiment of the present invention.

FIG. 4 is a diagram showing an operation of a detailed example of the first embodiment of the present invention.

FIG. 5 is a diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram showing an operation according to the second embodiment of the present invention.

FIG. 7 is a diagram showing Embodiment 3 of the present invention.

FIG. 8 is a diagram showing an operation according to the third embodiment of the present invention.

FIG. 9 is a diagram showing the principle of the third embodiment of the present invention.

FIG. 10 is a diagram showing Embodiment 4 of the present invention.

FIG. 11 is a diagram showing a conventional technique.

FIG. 12 is a diagram showing a conventional technique.

FIG. 13 is a diagram showing a conventional technique.

FIG. 14 is a diagram showing a conventional technique.

FIG. 15 is a diagram showing a conventional technique.

FIG. 16 is a photograph of an oscilloscope waveform showing the effect of the present invention.

FIG. 17 is a diagram showing Embodiment 5 of the present invention.

FIG. 18 is a diagram showing Embodiment 5 of the present invention.

FIG. 19 is a diagram for explaining the effect of the present invention.

[Explanation of symbols]

1 ... LSI 2 ... Pulse generation circuit 3 ... Transient current reduction circuit 4. Operating rate detection circuit 5 ... Current consumption circuit 6 ... Master clock 7 ... Pulse output pin 21 ... Clock counting circuit 22 ... Delay circuit 23 ... Data operation circuit 41 ... Signal generating circuit A 42 ... Signal generation circuit B 211 ... Counter 212 ... FF 213 ... Primary detector 215 ... Adder

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-6-51027 (JP, A) JP-A-6-317620 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193

Claims (18)

(57) [Claims] 1. A data calculation means for generating a pulse generated at a desired cycle or a pulse delayed for a desired time from a reference signal, and an integer multiple of a master clock is counted by the first data from the data calculation means. An IC circuit with a pulse generation function that operates in synchronization with a master clock, which is composed of a clock counting means for generating a pulse and a pulse delay means for generating a delay amount by the second data from the data operation means, First detecting means for detecting in advance that the change in the operating rate of the pulse generating means changes from coarse to dense, and second detecting in advance for detecting the change in the operating rate of the pulse generating means changing from dense to coarse. And a current consuming unit that consumes a predetermined current based on the detection signal of the first detecting unit or the second detecting unit. The IC circuit with a pulse generating function, characterized in that the current consuming means is operated based on the detection signal of (1) and the current consuming means is stopped based on the detection signal from the first detecting means. 2. A data calculation means for generating a pulse generated at a desired cycle or a pulse delayed for a desired time from a reference signal, and an integer multiple of the master clock is counted by the first data from the data calculation means. In a pulse generation circuit that operates in synchronization with a master clock composed of a clock counting means for generating a pulse and a pulse delay means for generating a delay amount by the second data from the data calculating means. Detecting means for detecting other than the period of the master clock from which the counting end signal of
An output is obtained by ANDing the output of the detecting means and the master clock or a clock having a desired generation period.
A clock generating means, pulse generating function IC circuit, characterized by comprising a current consumption means that the operation by the clock generating means. 3. A first set time from a pulse generation time in which it is stored in advance that the change of the operation rate of the internal logic realizing means of the pulse generation means changes from coarse to fine. The second detection means sets a second setting from a pulse generation time stored in advance that the change of the operating rate of the internal logic realizing means of the pulse generation means changes from dense to coarse. The IC circuit with a pulse generating function according to claim 1, wherein the IC circuit is detected based on time. 4. The first detection means uses a pulse generation time in which it is stored in advance that the change of the operation rate of the internal logic realizing means of the pulse generation means changes from coarse to fine.
Detecting based on a third set time, the second detecting means, from the pulse generation time stored in advance that the change of the operating rate of the internal logic realizing means of the pulse generating means changes from dense to coarse. 2. The IC with pulse generation function according to claim 1, wherein the current consumption means is operated / stopped in multiple stages by detecting based on the second and fourth set times of
circuit. 5. The pulse generating function according to claim 1, wherein a plurality of the current consuming means are provided, and the operating / stopping cycles of the plurality of current consuming means are made different. IC circuit. 6. The IC circuit with a pulse generating function according to claim 1, wherein a bypass capacitor is provided between a power supply voltage pin and a ground pin of an LSI that realizes the pulse generating circuit. 7. A pulse generating circuit for generating a desired pulse, and a current consuming circuit for consuming a predetermined current as necessary, the current consuming circuit of the pulse generating circuit and the current consuming circuit of the current consuming circuit. An IC circuit with a pulse generation function, characterized in that the sum is controlled to fall within a predetermined range. 8. The sum of the consumption current of the pulse generation circuit and the consumption current of the current consumption circuit is within a predetermined range with respect to a period including a period before and after the pulse generation circuit generates a pulse. 8. The IC circuit with a pulse generating function according to claim 7, wherein 9. A data calculation means for generating a pulse generated at a desired cycle or a pulse delayed for a desired time from a reference signal, and an integer multiple of the master clock is counted by the first data from the data calculation means. A clock counting means for generating a pulse, a pulse generating means having a delay means for generating a delay amount by the second data from the data calculating means, and a change in the operation rate of the pulse generating means from coarse to dense. First detecting means for detecting in advance, and second detecting means for detecting in advance that the change of the operating rate of the pulse generating means changes from dense to coarse, the first detecting means or the first detecting means. A current consuming unit that consumes a predetermined current based on the detection signal of the second detecting unit, and operates the current consuming unit based on the detection signal from the second detecting unit, That the said current consumption unit based on the detection signal stops outputting the test waveform to be tested and from the LSI test device according to claim. 10. A data calculation means for generating a pulse generated at a desired cycle or a pulse delayed for a desired time from a reference signal, and an integer multiple of a master clock is counted by the first data from the data calculation means. A clock counting means for generating a pulse, a pulse delay means for generating a delay amount by the second data from the data calculating means, and a cycle other than the master clock cycle at which the counting end signal of the clock counting means is output. And a clock generating means for generating an output of the logical product of the output of the detecting means and the master clock or a clock having a desired generation period.
An LSI test apparatus characterized by outputting a test waveform to a device under test by means of a pulse generation circuit comprising a stage and a current consumption means operated by the clock generation means. 11. The first detecting means detects that the change of the operating rate of the pulse generating means changes from coarse to dense on the basis of a first set time from a pulse storing time stored in advance. The second detecting means detects that the change of the operating rate of the pulse generating means changes from dense to coarse based on a second set time from a pulse storing time stored in advance. The LSI test apparatus according to claim 9. 12. The first detection means is based on first and third set times from pulse generation times stored in advance that the change in the operating rate of the pulse generation means changes from coarse to dense. The second detection means is based on the second and fourth set times from the pulse generation time stored in advance that the change in the operating rate of the pulse generation means changes from dense to coarse. 10. The LSI test apparatus according to claim 9, wherein the current consumption means is operated / stopped in multiple stages by detecting. 13. The LSI according to claim 9, wherein a plurality of the current consuming means are provided and the operating / stopping cycles of the plurality of current consuming means are different.
Test equipment. 14. The LSI test apparatus according to claim 9, further comprising a bypass capacitor provided between a power supply voltage pin and a ground pin of the LSI that realizes the pulse generation circuit. 15. A pulse generating circuit for generating a desired pulse, and a current consuming circuit for consuming a predetermined current as required, the current consuming circuit of the pulse generating circuit and the current consuming circuit. An LSI test apparatus, wherein the pulse generation circuit outputs a test waveform to a device under test by controlling the sum to fall within a predetermined range. 16. The sum of the consumption current of the pulse generation circuit and the consumption current of the current consumption circuit is within a predetermined range with respect to a period including a period before and after the pulse generation circuit generates a pulse. The control is performed according to claim 1.
5. The LSI test device described in 5. 17. A data calculation means for generating a pulse generated at a desired cycle or a pulse delayed from a reference signal by a desired time, and an integer multiple of the master clock is counted by the first data from the data calculation means. Pulse counting circuit for generating a pulse, a pulse generating circuit having a delaying means for generating a delay amount by the second data from the data calculating means, and a detecting circuit for detecting whether the pulse generating circuit is operating or not. And an LSI test apparatus having a current consumption circuit that consumes a current based on a signal detected by the detection circuit. 18. The LSI test apparatus according to claim 17, wherein the current consumption circuit operates when the pulse generation circuit is stopped, and the current consumption circuit stops when the pulse generation circuit operates. LSI test equipment.