JP3453618B2 - Processor for division and square root using polynomial approximation of root - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a mathematical processor for performing floating point division and square root operations.

[0002]

BACKGROUND OF THE INVENTION Generally speaking, division and square root operations are performed in a mathematical coprocessor with a redundant method of subtraction and feed, much like manually calculating long divisions. Has been done. The drawback of this method is that it takes a long time to complete all the necessary subtraction and feeding operations.

One method used to improve the speed of division and square root operations is to take advantage of quadratic convergence. If we try to determine y / x, then 1 / x is first determined, which is done by a method other than redundant long computations. Then, a multiplication operation (y times 1 / x) can be used. This speeds up the calculation. One way to determine the value of 1 / x would be to store all possible values in memory.

However, when an accurate number of bits is required, a large capacity memory must be used. Therefore, a value of 1 / x will be calculated each time for a different value of x. One way is to start with a low accuracy initial approximation and improve it using the Newton-Raphson iterative solution. Such a method is described by S. It is described in "Introduction to Arithmetic for Digital System Designers" by Weiser and MJ Flynn (1982, New York, CBS College).

This iterative solution method is F _{K + 1} = F _K (2-x
F _K ), is used. Where F _K is 1 / x
Is an approximate expression of. The accuracy can be improved to the required point through quadratic convergence by using the initial approximation formula of F _K and performing several iterative solving methods. The x operands are generally normalized within the range 1≤x <2, and the first 1 / x can be selected from the values stored in ROM. This technique first calculates 1 / √x and then √x
Multiply x to create 1 / √x if desired
The initial approximation for can be improved by a Newton-Raphson iterative method similar to that described above.

[0006]

The present invention determines the values of 1 / x and 1 / √x for a given operation number x,
It provides an improved apparatus and method for determining the values of y / x and √x. This is achieved by utilizing polynomial equations. The coefficients of the polynomial equation are stored in ROM. Different coefficients are used for different values of x. X as input to ROM to select appropriate coefficient
The most significant bit of the operand is used.

In the preferred embodiment, the polynomial equations are in second order, and the coefficients are sufficiently precise to give a final result of single precision accuracy.
For double precision, the polynomial result is used as an initial approximation for the Newton-Raphson iterative solution. This gives a higher degree of accuracy to the first Newton-Raphson approximation without having to increase the ROM size for the first approximation. Therefore,
The Newton-Raphson iterative solution is required only once to obtain double-precision accuracy.

The polynomial used is preferably of the form Ax ² + Bx + C. The present invention also uses a split multiplier array to speed up the calculation of this polynomial. After the initial x ² calculation, multiplying A by x ² and B by x is done simultaneously by half of the multiplier array. This is possible because the stored coefficients need not be perfectly accurate. In this way
They need only part of the multiplier array to do the multiplication. The magnitude of the coefficients corresponds to what is needed to produce the result of appropriate precision for each of the elements of Ax ² + Bx + C. In the preferred embodiment, A is
15 bits, B is 24 bits, and C is 32 bits. 1 / x
Separate values for the coefficients of A, B and C must be stored in the approximate expression for and 1 / √x.

As a further aspect of the invention, a special multiplier is provided which is capable of accepting operands in carry / hold format. This eliminates the need to convert the partial product to normal binary format by propagating the carry completely. In this way the speed of the multiplication sequence can be improved. this is,
This is accomplished by providing Booth recorder logic that can accept normal binary or carry / hold formats.

The present invention also provides an improved rounding method to IEEE that provides exact rounding by an operation involving a single multiplication. The present invention thus speeds up processor functionality in several ways. First
The initial approximation to is very accurate by using the polynomial approximation. Second, the split multiplier array allows two or more operations to be performed simultaneously. Third, the Booth Recorder logic is designed to accept intermediate operands in a carry / hold format so that it does not have to be put in pure binary format before the next multiplication is done. Finally, the special rounding method of the present invention has very few calculation steps.

The technique of the present invention, except for special rounding methods that are not used for reciprocal and reciprocal square root operations, divide, square root,
Used for reciprocal and reciprocal square root operations.

[0012]

1 is a block diagram of an entire semiconductor chip incorporating the present invention. A set of operands is provided on input buses 12 and 14. These are provided in the registration file 16. Registration files are separated one after another ALU 18
And the multiplier unit 20. These outputs are
It is supplied to the output 24 through the multiplexer 22. This configuration allows the ALU and multiplier unit to be used in parallel. The invention pointed to in this application is contained within multiplier unit 20.

Polynomial Approximation Formula FIG. 2 is a graph showing a 1 / x curve between x = 1.0 and 2.0. As discussed in the background,
To do with a given operand x, it is advantageous to calculate 1 / x first and then multiply by the numerator operand y. The determination of 1 / x starts with an approximation for a given value of x between 1.0 and 2.0. All operations (reciprocal, division, reciprocal square root, and square root) are always the first operation according to IEEE Standard 754, unless otherwise noted.
Takes a normalized number between 1.0 and 2.0.

In the present invention, the 1.0 and 2.0 intervals are divided into 256 smaller intervals, and each interval i in FIG.
The 1 / x curve at can be accurately approximated by A _i x ² + B _i x + C _i . A _i , B _i and C _i
The coefficients for each of these 256 intervals of are separately predetermined.

For each interval, the polynomial Ax ² + Bx
The coefficient of + C is determined by selecting the midpoint of the interval and the other two points in the respective direction from the midpoint at √3 / 2 times half the interval. These three points are then A _i , B
It is used to create three equations that are solved together to create _i and C _i . The values of the coefficients A ₁ to A ₂₅₆ , B ₁ to B ₂₅₆ and C ₁ to C ₂₅₆ are stored in ROM 30 as shown in FIGS. 3 and 4 and further described below. It is supposed to be. ROM 30 is x on line 32
Addressed by the 8 most significant bits of the operand.
One peculiar embodiment is to use the eight most significant x's at each interval.
It takes advantage of the fact that the bits are constant.

This is done by defining x = x ₀ + Δx. Where x ₀ is the most significant 8 bits of x (which is constant throughout each interval) and Δx is the eight zeros with the remaining bits of x. When this expands to the equation Ax ² + Bx + C, and the conditions are grouped again, the resulting equation is (A) Δx ² + (2Ax ₀ + B) Δx + (Ax ₀ ² + B
x ₀ + C). The values in brackets are constant throughout the interval and can be stored in ROM as modified A, B and C.

When the initial approximation formula is made, the calculation is AΔx ²
+ BΔx + C. Where A, B and C are their modified values. The advantage of this is that it handles significant figures. Δx has eight leading zeros,
Δx ² has 16 leading zeros, but they are transferred and leading to the product made from them. So, the most significant bit of A can only affect the 17th and lower significant bits of the approximation, and the most significant bit of B only affects the 9th and lower significant bits of the approximation. You can This is because it is necessary for this initial approximation to be accurate up to 28 bits, so it is not necessary to store all the coefficients exactly.

In the preferred embodiment, there are exactly 15 bits for A, 24 for B, and C for
There are 32 bits. This would provide for Ax ² + Bx + C all exactly 31 bits, since there is at least 31 bits of accuracy in each of the three additional elements. The coefficients A, B and C corresponding to this value x are then supplied to registers 31, 33 and 34, respectively.

FIGS. 3 and 4 show a multiplier divided into two halves, 36 and 38, respectively. For polynomial calculations, each half is concatenated to work as one multiplier in the x ² condition, and used as two separate multipliers in the simultaneous multiplication of Ax ² and Bx, as discussed below. To be done.

Referring to FIG. 13, the inspection of the modified A, B and C is done during cycle 1. At the same time, the multiplication of Δx itself is done by moving the two half arrays together to create a squared condition. Number of operations Δx
The high-order bits of the carry through the arithmetic multiplexer 40 and multiplexer 52 are carry / hold adder (CSA) multipliers
It is supplied to the "A" input of half 36 of the array . Meanwhile, the remaining low order bits are provided to array half 38. The Δx operation number is also increased by the booth recorder 50 through the multiplexer 41.
Is supplied to. The booth recorder 50 then calculates the booth record version of the bits in the high order of Δx as the multiplier array.
Feeds the "B" operand of 36 and the low order bits feed the "B" input of array 38 . The low-order multiply products and carry forms (CS) are provided to multiplexers 42 and 43, respectively.

As will be appreciated, the control signals for this cycle select those inputs which have a "0" indication. These are then digitized and applied to the inputs 44,45 of array half 36, just as they are in the multiplier array. Array 36 completes the calculation. The result of Δx ² is provided to register 47 from the product output of array half 36 through multiplexer 46 for the "first" pipeline.
("Second" pipeline carry / propagate (CP)
It consists of an adder 48 and a second pipeline register 49. ) The Δx ² operation number at this stage is stored in the carry / hold / format.

In the second cycle shown in FIG. 13 and with the control signals for cycle 2, shown in FIGS. 5 and 6, the Δx ² condition and operation of register 47 to calculate the AΔx ² condition. The number A and is provided to the multiplier array 36. At the same time, the B operation number and the Δx operation number are supplied to the multiplier array 38 so that the BΔx multiplication can be performed at the same time. Since not all 64 bits of the coefficient are needed, it is possible to do this simultaneously using two parts of the partitioned multiplier array. At the same time, this happens in cycle 2 in the second pipeline consisting of carry / propagate (CP) adder 48 and register 49, and for the CP rounding operation to input in pure binary format, for Δx ^2. Is done. This pure automatic CP rounding is not required until the time of the final result, but also the binary form of Δx ² and other intermediate results are ignored.

Although the details will be discussed below, the Δx ² condition of the register 47 is the same as that of the booth recorder 50.
It is supplied in CS format to multiplexers 41, 51 which are connected to the CS input. Two multiplexers are used because of the S, C format. The Booth coded output is then provided to the "B" operand of array 36. This output is the 36 most significant bits of Δx ² and the remaining bits of the Booth Recorder are provided to array 38. The A coefficient is provided to the "A" operand of array 36 through multiplexer 52.

The B coefficient is transferred from the register 33 to the multiplexer.
41 through the Booth recorder 50 to the "B" operand input of array 38. The Δx condition on MA input 32 is applied to the "A" operand of array 38 through multiplexer 40.

Also during cycle 2, BΔx of array 38
The product is combined with the C coefficient from register 34 in a carry / hold adder (CSA) 53 to provide the BΔx + C condition. This output is provided to CSA 54, where it is added to the AΔx ² product of array 36, but the result is stored in register 47.

As will be appreciated, the x ² condition is in carry / hold format without conversion through CP adder 48 to the normal format, since this requires additional time. Yes-used. This capability is provided by special Booth recorder logic that accepts either the normal binary format or the CS format described below in detail, which supplies all necessary information for one of the operands to the multiplier arrays 36 and 38. Do)
Be prepared by.

In the third cycle of the single precision calculation shown in FIGS. 7 to 13, the number of operations is the polynomial Ax ² + B.
It can be applied x + C times. This is done when the polynomial is still in CS format, again saving decoding time. The Newton-Raphson iterative solver is not needed for single-precision computations, because the polynomial provides the necessary level of precision that can be directly multiplied by the 1 / x condition by the y condition. The control signals used for the remaining cycles are shown in FIGS. 9, 10, 11 and 12.

For a double precision divide operation, the operation proceeds similarly until the third cycle, as illustrated in the timing chart of FIG. In the third cycle, the Newton-Raphson iterative method uses the polynomial Ax ² +
Started by multiplying the negative x value by Bx + C (in CS form). The iterative solution method completes in cycle 4 to provide the required precision. Next, in cycle 5, the operation number y is multiplied by the Newton-Raphson approximation of 1 / x. Here, for double precision, the use of the polynomial of the present invention requires the Newton-Raphson iterative solution only once.

The booth recording referred to above is AD Booth's "Established Binary Multiplication Technique".
(Quarterly, Mechanical and Applied Massmatics, Vol. 4, Part 2, 1951 Edition). The logic of the present invention enables the Booth Recording logic to receive operands in a carry / hold format. In this way, there is no need to enter the normal format, as described further below for x ² and other conditions, but to speed up the operation.

The determination of the square root is also a polynomial Ax ² + Bx +
This is done by using C, but the 1 / √x curve between x = 0.5 and 2.0 is used for the approximation calculation. 512
Intervals are used to store the coefficients for this reciprocal square root approximation calculation using separate ROMs or separate fields of the same ROM 30. The actual square root is determined from the reciprocal by multiplying it by x, similar to the division procedure above.

Although the split array multiplier Ax ² and Bx conditions have been shown to be calculated above,
That method takes advantage of another aspect of the invention.
These conditions are used to calculate the 1 / x single precision value. This single precision result is calculated with a precision of only 28 bits, so the values used for the calculation do not require a precision of more than 28 bits. Calculation of Ax ² condition and Bx condition requires one multiplication operation each, but again, since the result of the precision of only 28 bits is required, use only the arithmetic number with the precision of 28 bits. Is also good. In this way, the full 60 × 64 array is not required to calculate these two conditions, and it may be split so that the conditions can be calculated simultaneously. The particular embodiment shown in FIGS. 3-12 illustrates this, where the multiplier array is
It is divided into two sub-arrays of 36 and 38, each with a 60-bit MA operand, and with a 36-bit and a 28-bit MB operand respectively. During the second stage of the second polynomial approximation calculation, the product Ax ² is calculated on the 60 × 36 sub-array and at the same time Bx is calculated on the 60 × 28 sub-array, each using the full array. This saves a full cycle compared to the case where

In general, multi-stage calculations often involve two intermediate calculations, each having an operand that is independent of the result of the other calculation. If so, the intermediate calculation must be examined to see how many bits of precision the result and operand require. If the sum of the number of bits required for one intermediate computation operation plus the number of bits required for another intermediate computation operation does not exceed the maximum number of bits available in the array, The array may be split and both intermediate calculations may be done simultaneously. The same analysis suggests that for more complex calculations, the array can be split to handle three or more calculations at once.

Partitioning the array is fairly straightforward, each sub-array 36 and 38 is designed as a conventional independent multiplier array. For a split array operation, each sub-array is therefore supplied with its number of operations and distributes the result in the usual way. To combine the sub-arrays into a larger integrated array, logic is given to do the following: Supplying one of the two operands to each sub-array as a whole. The other operand, one is divided into pieces for each sub-array. In this particular embodiment, the fragmentation and provision of operands is done by multiplexers 41, 51 and Booth recorder 50. The values calculated by these sub-arrays 36 and 38 are used as partial products. They are digitized according to the position of the least significant digit of the fractional operand of the total number of operands previously divided.

This is shown in FIGS. 15 and 16. A is 64
60 × 28 multiplier array by the bit operation number B
(38) and a 60 × 36 multiplier array (36) to multiply by 60 bits. A is multiplied by the least significant 28 bits of B to produce a 88 bit result C in a 60 × 28 array. At the same time, A is multiplied by the most significant 36 bits of B to produce a 96-bit result D in a 60 × 36 array. D then logically moves 28 bits to the left (the actual hardware does this by moving C to the right to simplify placement) -creating a 124-bit F. -The left 96 bits are 96 bits of D, and the rightmost 28 bits are zero (E ₂₈ ... E ₁ ). Then C and F
Are added to each other to produce the result G. Figure 16 illustrates the fact that C and D are partial products, and also D can be fed to the input of the adder by the left shift method without the actual separate shifter, or C is right. It makes clear that it can be fed to the input of the adder by a moving method.

In this particular embodiment, the multiplexers 42,43 perform the inversion of the array 38 by applying it to the inputs 44,45 of the array 36.

The process of Booth recording multiplication can be considered in two main stages: the first stage is the production of partial products, and the second stage is the reduction of these partial products into the final product. . First we need one adder to add the two partial products,
And generally one additional adder is required for each additional partial product. The simplest form of multiplication is the bitwise operation of the multiplier, and the multiplier creates one partial product for each bit.

The n × m bit multipliers along these lines produce m partial products to add. A brief general example is shown in Figure 17. To make up this multiplier, a group of m adders sums the products. Each partial product is either A or 0 and is determined by the individual bits of B. This multiplier is simple, yet costly in scale, and m additions are required to produce the product. It is possible to reduce the number of partial products to add. Booth recording (but by using a Booth recorder) can skip the multiplication process through adjacent columns of 1s and adjacent columns of 0s in the multiplier, for n-bit multipliers, n / Do not create more than 2 products.

The more commonly used modified Booth recording processes superimposing groups of bits at a time, the new number b of bits per group being represented by the radix 2 ^b . Radix 2 ^b Booth recording is (n
/ B) produces +1 partial products and adds itself to the parallel hardware device. The modified recording method encodes these overlapping groups based on whether they start, continue, or are the ends of a row. To ensure proper termination of a sequence of ones, the number to be recorded must be padded with one least significant zero and at least one most significant zero. Radix 4
(2 ² ) Booth recording, each group has 3
Bits, two are the major ones, plus one overlapping bit from the right (not the top).

FIG. 18 (a) shows how 8-bit unsigned numbers are grouped with one zero on the right and two zeros on the left, and FIG. 18 (b). To 3
It shows whether the bit groups are coded through standard radix-4 Booth recording. FIG. 19 (a) shows a block diagram in which the Booth recording logic accepts three inputs r ₀ , r ₁ and r ₂ . These are bits y _i-1 , y _i and y _{i + 1 in} FIG. 18 (b).
It corresponds to each. So an 8-bit number can produce 5 partial products, requiring 4 adders. Figure 19 (b)
Figure 19 (a) shows how the five booth recorders
It shows how it can be used to compute Booth recording information for an unsigned 8-bit number in 18 (a).

FIG. 20 illustrates the total of A × B partial products. Here, B has m bits. Note that only m / 2 adders are needed. The limiting feature of standard booth recording is that it only deals with numbers in binary format. This is a drawback in operations that require successive multiplications, where the result of one multiplication is used as the number of operations in the next multiplication operation.
When the partial products of one multiply operation are added first, the result is initially in an extra format such as carry / hold. Before this result undergoes standard Booth recording it must be included in the binary format by the CP adder-this consumes valuable time. The CP adder must signal the transfer from the rightmost position to the leftmost position, resulting in n delays in including the n-bit number in the binary format. The CP adder of the present invention has to perform the CP estimation over a 100-bit number, that is, a CP addition transmission delay exceeding 100 times. Performing such a CP addition after each multiplication in a series of multiplications would be valuable time consuming.

[0041] While one aspect of the present invention to increase significantly the speed of the successive multiplication calculations are pre-coding of the number of surplus format supplied to the Booth recoding the input does not require a long delay of the CP adders, Is the method. In accordance with this aspect of the invention, the circuit accepts a number of carry / hold formats and processes them to create an input to a group of standard booth recorders as in Figure 19 (a). The Booth Recorder is basically organized in the same manner as Figure 19 (b), except that the numbers are processed by a logical middle layer in a carry / hold form rather than a binary system. This layer of logic is made up of several identical units, and the logical components for such as carry / hold record units are illustrated in FIG. 21 and generally designated by the reference numeral 200.

The carry / hold recording (CSR) logic layer does not simply determine the corresponding binary format of the carry / hold number, because it is for n pairs of outstanding carry / hold numbers. Is delayed by n times. Rather, the CSR unit is composed of two pairs of carry / hold bits of primary interest (S ₁ combined with a ₁ a _0).
Accept C ₁ C ₀ ) combined with S ₀ and b ₁ b ₀ ) as input, and the two inputs Ca and Cb of the CSR unit to the right (next higher group) Each CSR unit outputs r ₀ , r ₁ and r ₂ (information needed by the Booth recording logic) and also the next CSR
It outputs the two bits Ca out and Cb out required by the unit.

The logic is that Cb out is designed to be determined by the sum of S ₁ S ₀ and C ₁ C ₀ and is completely independent of Ca and Cb. The total amount of S ₁ S ₀ and C ₁ C ₀ can range from 0 to 6, and Cb out is set when the total amount is greater than 1. Ca out is S ₁ S ₀ and C ₁ C ₀
Is determined and set by the total amount of Cb and Cb, if Ca is 6 or the total amount of Cb is 5
Or, it is set when 1. (The mathematical justification for this is explained below.) Ca out is affected by Cb, but Cb is completely CS by the previous CSR unit.
Without referring to the R unit much earlier
(Handling less significant bits) has been decided. Also note that Ca is directed directly to r ₀ , which is its only use. The CSR unit can then instruct more directly to output Ca out to the booth recorder's r ₀ input, and the CSR unit can then output Ca out.
No input required.

The CSR unit does not have to have valid Ca before calculating its Cb out. Therefore, each CSR unit need only wait for the input that occurs in the unit next to it. No matter how many bits are included , how many CS
It doesn't matter if the R units are linked together,
There is only one CSR unit propagation delay in total before each CSR unit has all the inputs needed to calculate the information needed by the booth recorder.

FIG. 22 illustrates how a carry / hold recorder and a booth recorder are combined to provide booth recording information for a number of eight carry / hold bits. The carry / hold reorder can also handle normal binary numbers by setting the carry bit to zero.

The circuit of FIG. 21 is the only possible circuit where the CSR unit can provide input to the radix-4 Booth recording logic. As will become apparent below, Ca and Cb outputs can occur differently. And the CSR unit can also be configured for booth recording logic with radix 8, 16, etc.

To understand the arithmetic theory of this aspect of the invention, we use radix-4 Booth recording. Then, as an alternative for expressing the information in FIG. 18 (b), y _{i + 1} bit has a weight of −2, y _i bit has a weight of 1, and
And it has to be noted that the y _{i -1} bits also have a weight of 1. (For radix 2 ^b Booth recording, bit y _i-1 has a weight of +1, bit y _{i + b-1} has a weight of -2 ^b-1 , and bit y _{i + j} ( Where 0 ≦ j ≦ (b−
2)) has a weight of 2 ^j .

The direct method to the Booth Record 4 carry / hold bit pair is shown in FIG. 23 (a). Carry-in / hold bits are carry-in C _in and carry-out C
fed into the 4-bit adder 200 with _out, and T
The total amount of bits from ₀ to T ₃ is supplied to the booth recorder 100 in a standard manner. A very similar means is shown in Figure 23 (b), where two 2-bit adders with an intermediate carry C are used. This intermediate carry C still relies on C _in , so no propagation delay is saved in this arrangement.

However, it is possible to make the intermediate carry C a predictive carry. It will be determined entirely by preemptive carry by adding two extra format bits without reference to carry-in. Of course, predictive carry does not always correspond to true carry, but it can be corrected. This is because the carry added to the y _i position carries the same weight and has the same net effect on the final product so that y _i-1 makes input r ₀ . (The net effect of the booth recording output will be the same, even if different booth recording outputs are generated.)

Next, in order to use the overlapping out-bits y _i-1 of the higher booth recorders correctively, however, without disconnecting from the T ₁ output going to the y _{i + 1} input r ₂ of the current Booth recorder. must not. This is Figure 24
The carry / hold recorder (CS
R) Unit 200 replaces 2-bit adder 210 in Figure 23 (b). These CSR units generate a total of T ₁ and T ₀ , and then also a pre-determined carry Cb-out, which is used as a carry-in in the higher order unit, and a corrective carry or next higher booth recording. It also produces an overlapping bit Ca out, which is decoupled from the T ₁ output used as the y _i-1 input.

Keeping in mind that in the arrangement of FIG. 23 (b), carry C also has the same weight (+1) for the T ₁ bit (which is then combined as the y _i-1 input to the higher order Booth recorder). We can group their combined effects in three cases. (A) Both true carry and T ₁ are +1 (combined weight +2) (B) Either true carry or T ₁ is +1 (weight +1) (C) Both true carry and T ₁ are +1 This is the case where the weight is not included (combined weight +0). Therefore, the predictive carry Cb out and the corrective carry Ca out are generated in these cases so as to generate the correct connection weight. Preliminary carry Cb out must be generated with an arrangement of a ₁ b ₁ a ₀ b ₀ that results in case (A) (depending on carry in), and as a result of case (C). It cannot be created in any arrangement, or it can be created arbitrarily. Corrective carry Ca out depends on the actual result case (A), (B) or (C), and the corresponding connection weights (+2), (+1), (+0) are Ca out and Cb out respectively. Will be generated together.

Thus, the outline of carry generation of the circuit of FIG. 21 can be understood. As mentioned above, this circuit uses S ₁ S
Whenever the total amount of ₀ and C ₁ C ₀ is 2, 3, 4, 5 or 6, the Cb out signal is generated. A total amount of 0, such as the total amount 1 when the carry in Cb is not set, always results in the above case (C). So no Cb out should be generated. As in the case of the total amount 5, the result of the case (A) always occurs when the total amount is 6. So Cb out must be generated for these. Total 2, 3, or 4
, The result of case (B) will always occur, and Cb out will be set. Ca out then takes into account the effect of carry-in Cb and is set whether the result is case (A) or the result is case (B) and Cb out was not set. When Cb is set and the total amount is 6 or 5, the result is case (A), so Ca out is set for these. When Cb is set and the total amount is 1, the result is case (B), and Cb out is the total amount 1
Ca Out is set if not set for. In all other situations Ca out is not set. As mentioned above, various other carry generation schemes can be used as long as the correct weights result for cases (A), (B) and (C). The unique carry generation scheme in Figure 21 simplifies the circuit layout.

This scheme can now be generalized to replace the b-bit adder with a b-bit CSR unit to generate inputs for pre-determined carry and Booth recording logic. The generalized scheme has the same three cases with the same weight. Again, the case is determined by the final total amount Tsum plus carry-in plus extra format bits. Case (A) occurs when both Tsum ≧ 2 ^b (there is a true carry out) and T _b−1 (corresponding to overlapping bits) are set. Case (B) occurs when exactly one of these conditions is true, and case (C) occurs when neither of them is true.

If we now apply these generalized rules to a 3-bit CSR unit, the circuit of Figure 25 is constructed, where the 3-bit CSR unit is padded with the required zeros and carried up. Used in conjunction with a radix-8 booth recorder to booth record 16-bit numbers in / reserved format. Case (A) has Tsum ≧ 8 and T ₂
Occurs when is set. Case (C) is Tsum
<4, case (B) occurs at all other times. The 3-bit CSR unit is designed along the same line as the 2-bit CSR unit in Figure 21: a ₂ a ₁ a ₀ and b
Generate a Cb out whenever the total amount of ₂ b ₁ b ₀ (carry / hold input) is greater than 3. Ca out is when Cb is set and the total amount is 14, 13, 12, or
It is always generated at 11 and all correspond to case (A). Alternatively, when Cb is set and the total amount is 3, it corresponds to the case (B) where Cb out is not set.

The CSR unit is thus replaced by an adder for applying numbers in carry / hold format to the Booth recording logic without requiring any transmission delay as required by the adder.
The CSR unit, although this is not the most efficient, can even mix CSR units or adders of other sizes. The only important requirement is that the Cb out carry correspond to the y _i input of the booth recorder, and Ca
Corrector overlaps the booth recorders (y _i-1 )
It means to be paired with a bit. As an example of a different arrangement that is just possible, in Figure 26, a 1-bit CSR unit 300 and a 2-bit adder 310 to supply input to a radix-4 Booth recorder 100 for a 100-bit number in carry / hold format. It is coupled to the 3-bit adder 320. If only the adder is used and no CSR unit is used, then 100 CP add transfer is required. CSR
The use of unit 300 creates a premature carry in the middle of the number, effectively reducing the propagation delay by half. One possible alternative for CSR Unit 300 is shown in Figure 27. Reducing this transmission delay by half suggests the power of a predictive carry.

IEEE Accurate Rounding The preferred embodiment of the present invention incorporates another aspect towards providing IEEE precise rounding . By this we mean rounding that meets the requirements promulgated in ANSI / IEEE Standard 754, 1985. The IEEE standard promulgates two formats for floating point numbers-single precision and double precision. Floating point numbers have an exponent part e and a fractional part f, and their size is fx2.
^It can be represented as ^e . Here, f is 1. f ₁ f ₂ f
₃ ... f _n , where n represents the number of bits in the fractional part. Single-precision numbers have 23 bits in the fractional part, and double-precision numbers have 52 bits in the fractional part.

The IEEE standard generally considers rounding as a number that is infinitely precise, while warning that the result is inexact, stating that if necessary it will be modified to fit the desired format. Most of the mathematical operations require that the intermediate result be first created with infinite precision and boundless bounds, and that it be performed as if it were rounded according to one of a set of rounding modes. ing.

The first rounding mode is called the closest rounding. Under this mode, an infinitely accurate representative value that is closest to the result is given. If the two nearest representative values are close to equal, the one with the least significant bit zero is given. There are also three user-selectable rounding modes: + Rounding towards infinity-where the result is the closest value in the format, not less than the infinitely precise result; -Approximate towards infinity -In this case, the result is the closest value in the format, which does not exceed the infinitely precise result; and rounding to zero-in this case, the result is the closest value in the format, infinitely precise result It does not exceed the size of.

The IEEE standard applies the same method for single and double precision numbers; the reference point is always the least significant bit of the target format. For single precision numbers this is the 23rd bit and for double precision numbers it is the 52nd bit. For ease of discussion, these two cases are not distinguished, and the term "LSB" shall mean the least significant bit of the appropriate format.
Also, with minor exceptions, the rounding procedure is the same for division as it is for square root. So
All arguments directed to the quotient also apply to the square root except where noted.

For the closest rounding, in the worst case, the present invention determines whether the actual quotient falls just below the 1/2 LSB point, just above it, or directly above it. There is a need to. In the worst case of the other rounding modes, the present invention needs to determine whether the real quotient falls just below the LSB point, just above it, or directly above it. This is a subset of 1/2 LSB points, where
The value of the bit at 1/2 LSB is zero. So we will allow all rounding modes to determine the relationship between the real quotient and the 1/2 LSB point.

Whatever calculation is performed, the present invention uses LS
Compute the first result with an accuracy that is not a few bits higher than B. At this point the quotient is the original calculated quotient Q ₀
Truncated at 1/4 LSB to generate Error is termed ε and is defined through the equation Q _r = Q ₀ −ε ₁ . Here Qr is the true quotient. The data path is implemented as | ε | <1/4 LSB. It is also that the magnitude of the error is smaller than that, but the description clearly holds the truth, so -1/4 LSB <ε <+1
/ 4 LSB.

Now, a further error of 1/4 LSB is deliberately introduced by adding 1/4 LSB to Q ₀ to create the calculated quotient Q _C. The range of ε is now 0 <ε <1/2 LS
It is B. This guarantees that the quotient now calculated is strictly larger than the actual quotient. We now have a better idea of where to look to find the true quotient.

For purposes of recording, let N be any number whose least significant bit of the LSB is 0 or 1. We now general theory _{N ≦ Q C <N + 1} ( where units are understood to be one of the LSB and doing so in the future). This can be divided into two cases. One is (1)
N ≦ Q _C <N + 1/2 and the other is (2) N +
1/2 ≦ Q _C <N + 1. Let's consider each of these individually.

In all cases, 0.ltoreq..epsilon. <1/2, so in case (1) N-1 / 2 < _Qr <N + 1/2. All that is needed to determine from the above is the grounding of Q _r with respect to the 1/2 LSB point. The only such point in this range is at N. Q of case (1)
Note the range of _C : the only 1/2 LSB contained in it.
The point is also at N. So, Q _C is of being cut off by 1/2 LSB point to generate equal Q _t in N.

In case (2), N + 1 / 2≤Q _C <N
+1 and the range of Q _r is N <Q _r <N + 1. The only 1/2 LSB point in this range is N + 1/2 LSB. Again, this is also the only 1/2 LS within Q _C
It is point B, so Q _C is equal to N + 1/2 LSB Q
Note that it is cut off at the 1/2 LSB point to generate _t . In both case (1) and case (2), the critical value that Q _r must be compared with is 1/2 to generate Q _t.
It is know fact that is obtained by cutting off the Q _C in LSB points.

Once this critical value is confirmed, the relationship of Q _r to it can be determined by calculating the partial remainder PR. For division, PR = y−x · Q _t ;
For the square root is a _{PR = x-Q t · Q} t. If PR
If = 0, then Q _r = Q _t . If PR <0, then Q
_t −1/2 <Q _r <Q _t .

If PR> 0, then Q _t <Q _r <Q _t + 1 /
It is 2.

For multiplication of x · Q _t , all the high order bits of the result are kept for comparison with y, and y is not sufficiently higher order to be the same size as the x · Q _t product. The number is zero-padded. Therefore, in all cases it is possible to determine whether Q _r is exactly below the 1/2 LSB point, exactly above it, or just above it. It provides enough information for the IEEE's exact rounding.

It should be understood that the above description is illustrative and not restrictive. Many examples will be apparent to those of skill in the art upon reviewing the above description. The scope of this invention is
Accordingly, reference is made to the appended claims and such claims are determined along with their full scope of equivalents to which they are entitled.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a chip electronic component incorporating the present invention.

FIG. 2 is a graph illustrating the selection of coefficients for the polynomial Ax ² + Bx + C.

FIG. 3 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 4 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 5 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 6 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 7 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 8 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 9 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 10 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 11 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 12 is a block diagram illustrating the logic used for polynomial calculations according to the present invention.

FIG. 13 is a timing chart illustrating operations performed during different cycles of a polynomial calculation for single precision numbers.

FIG. 14 is a timing chart illustrating a polynomial calculation for double precision numbers.

FIG. 15 is a block diagram and a mathematical presentation of the use of two sub-array multipliers to calculate a larger partial product.

FIG. 16 is a mathematical presentation of a block diagram and the use of two sub-array multipliers to calculate the partial product of a larger multiplication.

FIG. 17 consists of M pairs of multiplexers and adders,
FIG. 3 is a diagram of a prior art NxM multiplier.

FIG. 18 (a) is an illustration showing how 8-bit unsigned numbers are padded with zeros and grouped into a radix-4 Booth recording; FIG. 18 (b) is a 3-bit representation. FIG. 6 is a diagram illustrating whether a group is encoded through standard radix-4 Booth recording.

19 (a) is a block diagram representing a Booth recorder of radix 4; FIG. 19 (b) is a block diagram of FIG. 19 (a) arranged so that Booth recording information of number B without 8-bit code can be calculated. It is a figure of one booth recorder.

FIG. 20 is an explanatory diagram showing how a multiplier is composed of five sets of input muxes and adders, and is controlled by Booth recording information of radix 4.

FIG. 21 is a block diagram of a carry / hold recorder.

FIG. 22: Carry / carry in order to be able to calculate booth recording information of number B without eight carry / hold codes
It is a block diagram in which a hold recorder and a booth recorder are arranged.

FIG. 23 is a block diagram in which 4-bit and 2-bit adders are used to apply carry / hold formats to a booth recorder, respectively.

FIG. 24 is a block diagram of the 2-bit adder of FIG. 23 replaced with a 2-bit carry / hold recorder.

FIG. 25 is a block diagram of a 3-bit carry / hold recorder used to generate input to a radix-8 Booth recorder.

FIG. 26 is a block diagram of a 1-bit carry / hold recorder that is used in combination with an adder to apply a carry / hold format number to a Booth recorder.

FIG. 27 is an explanatory diagram showing an outline of one possible circuit of a 1-bit carry / hold recorder.

[Explanation of symbols]

16 register file 18 ALU 20 multiplier unit

Front Page Continuation (72) Inventor Larry Hugh United States, 94040 California, Mountain View, Escuela Avenue 333 (72) Inventor Inyane Schwar Prabhu United States, 95121 California, San Jose, Eaglehurst Drive 1770 (72) Invention Person Frederick A. Ware United States, 94022 California, Los Alt Hills, Freemont Pines Lane 13961 (56) Reference JP-A-2-181822 (JP, A) JP-A-63-163630 (JP, A) JP-A-3-94328 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 7/52 G06F 7/552 G06F 17/10

Claims (22)

(57) [Claims] 1. A multiplier array comprising: a first array section, a second array section, and means for enabling or inhibiting the propagation of intermediate results from the first array section to the second array section; Means for providing a set of numbers to the first array section and the second array section , wherein the first array section and the second array section include the first array section and the second array section.
Propagation of intermediate results from the ray section to the second array section is prohibited
In the state in which the
As two products, each of which is calculated in parallel
And the first array section and the second array section are connected to the first array section.
Propagation of intermediate results from the ray section to the second array section
In such a state, the set of operands given to each is 1
As a product of the first array portion and the second array portion,
A device for multiplying the number of operations, which is characterized by being divided and calculated . 2. A multiplier array calculates a first product by calculating a product of a first operation number of m bits and a second operation number of (n + p) bits, and the first array unit includes: A second product is calculated by multiplying an m-bit third operation number by an n-bit fourth operation number, and the second array unit is configured by the m-bit fifth operation number and the p-bit sixth operation number. When the unified array mode is selected, the third product is calculated by multiplying by and means for enabling or inhibiting the propagation of the intermediate result is provided with means for selecting the split array mode and the unified array mode. Is allowed to be propagated, and propagation is prohibited when the divided array mode is selected. Means for giving a set of operation numbers to the first and second array units are as follows: a) divided array mode is selected If so, supply independent operands to the secondary array, b) When the unified array mode is selected, i) the first operation number is supplied to the first array unit as the third operation number and is supplied to the second array unit as the fifth operation number, and ii) the second operation number. Supplying the group of n bits on the least significant side as the fourth operation number to the first array section, and iii) supplying the group of p bits of the most significant side of the second operation number as the sixth operation number to the second array section The apparatus of claim 1, comprising: 3. An initial result of the operation is rounded to calculate a rounded value having a bit equivalent to a predetermined least significant bit LSB, and the initial result is a bit higher than the LSB. A device having at least 1/2 LSB and 1/4 LSB lower than the LSB by 1 bit and 2 bits, respectively, and wherein the operation has a real result, and the initial result is a 1/4 LSB point. To truncate to calculate the initial number Q ₀ , to add 1/4 LSB to Q ₀ to calculate the calculation result Q _c, and to truncate Q _c at the point of 1/2 LSB to truncate the result Q _t And means for determining the partial surplus for the operation, using Q _t as the result to obtain the partial surplus, and rounding from the initial result based on whether the partial remainder is positive, negative, or zero. A means for determining the obtained result. 4. The apparatus according to claim 3, wherein the operation is division of the number y by the number x, and the partial remainder is equal to y−x · Q _t . 5. The apparatus of claim 3, wherein the operation is a square root operation of the number x and the partial remainder is equal to x−Q _t · Q _t . 6. A method for rounding an initial result of an operation to calculate a rounded value having a bit equivalent to a predetermined least significant bit LSB, wherein the initial result has a bit higher than the LSB. , 1 bit and 2 bits lower than LSB, respectively, and at least 1/2 LSB and 1/4 LSB, and the operation has a real result. The initial result is truncated at the 1/4 LSB point. calculating a Q _0, 1/4 the steps of the LSB to calculate the calculation result Q _c is added to the Q _0, truncate the Q _c in terms of 1/2 LSB truncation results Q _t
To calculate the partial remainder for the operation, using Q _t as the result to obtain the partial remainder, and rounding from the initial result based on whether the partial remainder is positive, negative, or zero. Determining the result obtained. 7. A value of a function of x is determined with a specified accuracy, and x
Is the group of the most significant bit x _h and the least significant bit x _l
A device for holding a plurality of coefficients for each of a plurality of values of x and an input bus of x having a plurality of bit lines.
an input bus having a portion of the bit line corresponding to _h connected to an address input of the memory; and a data output of the memory and the input bus,
Within the interval defined by x _h , the polynomial “Ax ² + Bx +
According to the function of “C” , this polynomial “Ax ² + Bx +
And a calculation means for determining an approximate expression of the function of x by using the coefficients A, B and C of "C" . 8. The coefficient C is larger than the coefficient B in the memory.
, The coefficient B is higher than the coefficient A.
8. The apparatus of claim 7 having a number of high precision bits . 9. The calculation means is a result of the specified accuracy.
A multiplier array that is large enough to determine
The multiplier array comprises a first array section, a second array section, and an intermediate result from the first array section to the second array section.
A means for inhibiting propagation, and a means for differentiating the coefficient between the first array part and the second array part.
Given two numbers at the same time, calculate the two elements of the polynomial in parallel.
A device according to claim 7, comprising means for calculating . 10. The function of x is 1 / x.
The described device. 11. Overall effect of x _{h on} polynomial approximation
Is pre-factored to the coefficient, and the calculating means uses a coefficient having only x _l . 12. The value of a function of x is determined with a specified precision.
A method for holding a plurality of coefficients for each of a plurality of intervals of x.
According to the polynomial approximation of the function, using the step of giving the memory and the coefficient of the interval.
To determine an approximation of the function in one of the x intervals.
A method consisting of steps . 13. A newt for the function of the approximate expression
The improved approximation formula is obtained by implementing the Itinerson's iterative solution method.
13. The method of claim 12 including the step of calculating . 14. x is a group of most significant bits x _h
And a group of least significant bits x _l , the supplying step supplies the coefficient with an interval corresponding to bit x _h.
And so that x _h is constant within that interval.
Yes, the total effect of x _{h on} the polynomial approximation is
, And the decision step uses coefficients with only x _l
The method of claim 13, wherein comprising. 15. The polynomial is Ax ² + Bx + C, and the decision step is performed in parallel with A, B, and x ₁ ^2.
Find the finely C, and Ax _l ² in parallel as to calculate the Bx _l
15. The method of claim 14, comprising calculating . 16. The supplying step comprises the first lower order function.
The number of higher precision for the second higher coefficient
15. The method of claim 14 comprising providing a degree bit . 17. A carry hold format operation number bit
Independent and predictive carry for all input , carry input, and all carry inputs
Using the output and the above-mentioned operand bit input and carry input,
A means of calculating the recorder input information, and a bit of the operand in the carry pending format with
A device that calculates booth recorder input information about . 18. A correction dependent on the carry input.
Bei Eteori a positive carry output, booth recorder information before
Correction derived from carry input and arithmetic bit input
It consists of carry output and total output bit.
Raised output contains booth recording overlap bits
18. The device of claim 17, which is force . 19. The number of operations in the carry hold format
With the device that calculates the booth recorder input information for the part
So, the part of the operation number is n total bits and n digits.
Has carry bit, said sum bit and carry bit
Has a composite total S, and n is the number-of-operations partial total bit input, n is the number-of-operations-partized carry bit input, and carry input, and at least the total S is greater than (2 ⁿ +2 ^n-1 -2). When
Means for generating a pre-determined carry output, and when the sum S is greater than (2 ⁿ +2 ^n-1 -1), the sum S is equal to (2 ⁿ +2 ^n-1 -1)
When the input is true, and the predictive carry generation means is predictive
No carry is generated, or the total S is (2 ^n-1 -1)
And the carry input is true, or the sum S is
The corrected carry output is larger than (2 ^n-1 -1).
Source recording overlap bit input
In addition, the means for issuing the corrected carry output, the bits of the arithmetic part and the carry input are summed, and the
Instrumentation <br/> location of and means for calculating a Surekoda input information. 20. The booth recorder input information is a radix 2 ⁿ
20. The apparatus according to claim 19, which is information of booth recording of . 21. When n is 2 and the predictive carry generation means has a sum S greater than 1.
To generate a predictive carry output, and when the correct carry generation means produces a sum S equal to 6,
When the total S is equal to 5 and the raised input is true, and
When the total S is equal to 1 and the raised input is true,
21. The apparatus of claim 20 , producing a corrected carry output . 22. The predictive carry generation means has a total S
Preemptive carry output when larger than (2 ^n-1 -1)
Generated and corrected carry generation means, the sum S is (2 ⁿ +2 ^n-1 −
1) is larger than, the sum S becomes (2 ⁿ +2 ^n-1 -1)
Equal, when the raised input is true, and the total S
When (2 ^n-1 -1) is equal and the added input is true
20. The apparatus of claim 19 , wherein the apparatus produces a corrected carry output .