JP3413015B2 - CR oscillator - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a capacitor C and a resistor R.
The present invention relates to a CR oscillator that obtains an oscillation output by, and particularly to a CR oscillator that can obtain a stable oscillation frequency even at a low power supply voltage.

[0002]

2. Description of the Related Art Conventionally, as this type of CR oscillator, for example, the one shown in FIG. 8 is known.

In FIG. 8, the CR oscillator has an input terminal 1
00 between output terminal 101 and Schmitt trigger circuit 1
Inverter circuits 103 and 104 including 02 have an odd number of stages (3
Stage), the input terminal 100 and the oscillation capacitor 105 are connected to the ground, and the input terminal 100 and the output terminal 10 are connected.
1 and an oscillation resistor 106 are connected between them.

In such a CR oscillator, as shown in the input / output waveform diagram of FIG. 9, an input signal applied to the input terminal 100 oscillates within a predetermined potential width (Schmitt width, VthH) of the Schmitt trigger circuit 102. Amplitude is repeated at a cycle determined by the time constant of the capacitance 105 and the oscillation resistance 106,
The output signal applied to the output terminal 101 oscillates a pulse signal in synchronization with the input signal. Therefore, the frequency of the oscillation output in the CR oscillation circuit having such a configuration is set by the time constants of the oscillation capacitor 105 and the oscillation resistor 106.

However, when the power supply voltage of the oscillator drops, a P-channel or N-channel FET (electric field) that constitutes an inverter circuit 104 (hereinafter referred to as an output buffer) that constitutes an output stage of an inverter circuit connected to an odd number of stages The on-resistances of the effect transistors) 107 and 108 are apparently increased. This is because the Schmitt width of the Schmitt trigger circuit 102 becomes narrower as the power supply voltage decreases.
The operating point A of the FET in the output buffer 104 is shown in FIG.
This is because the non-linear region shifts to the linear region on the voltage (source / drain voltage) current (drain current) characteristic of 0. That is, the output buffer 104 operating in the non-linear region operates like a stabilized power supply and the flowing current is almost constant, whereas the output buffer 104 operating in the non-linear region has the current-voltage characteristic shown in FIG. As shown, since the flowing current changes, the output buffer 1 that operates in the non-linear region due to the decrease in the power supply voltage
The on-resistance of 04 will apparently increase.

Since the on-resistance of the output buffer 104 is connected in series to the oscillation resistor 106 for the charging / discharging operation by the oscillation capacitor 105 and the oscillation resistor 106, if the on-resistance of the output buffer increases, the output terminal 104 and the output terminal Terminal 10
The apparent resistance value connected between 1 and 1 increases. This increases the time constant of the oscillator and prolongs the oscillation cycle.

[0007]

As described above,
In the conventional CR oscillator, the on resistance of the output buffer is apparently increased due to the decrease in the power supply voltage, and the time constant of the oscillation circuit is increased. As a result, the oscillation cycle becomes longer. That is, in the conventional CR oscillator,
The fluctuation of the power supply voltage causes the fluctuation of the oscillation frequency due to the fluctuation of the ON resistance of the output buffer.

Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a CR oscillator having a small fluctuation in oscillation frequency even at a low power supply voltage.

[0009]

In order to achieve the above object, the invention according to claim 1 is characterized in that an inverter circuit including a Schmitt trigger circuit is cascade-connected in an odd number of stages between an input terminal and an output terminal, In a CR oscillator in which an oscillation capacitor is connected between an input terminal and a power supply and an oscillation resistor is connected between the input terminal and the output terminal, the CR oscillator is connected between the input terminal and the output terminal, A first conductivity type FET (field effect transistor) which is controlled to be in a conductive state for a certain period within a charging period of the oscillation capacitance, and is connected between the input terminal and the output terminal, and within a discharging period of the oscillation capacitance. Second conductivity type FET controlled to be conductive for a certain period of time
And a control circuit for controlling conduction of the both FETs based on an input signal given to the input terminal.

According to a second aspect of the present invention, an inverter circuit including a Schmitt trigger circuit is cascaded in an odd number of stages between an input terminal and an output terminal, and an oscillating capacitance is connected between the input terminal and a power source. In a CR oscillator in which an oscillation resistor is connected between the input terminal and the output terminal, a first inverter circuit that receives an input signal applied to the input terminal, and the Schmitt trigger circuit that receives the input signal A second inverter circuit that is connected in cascade in an even number stage, a logical sum (OR) gate that inputs the output signal of the first inverter circuit and the output signal of the second inverter circuit, and the first inverter circuit. AND gate for inputting the output signal of the inverter circuit and the output signal of the second inverter circuit, and the gate terminal is connected to the output terminal of the OR gate. A first conductivity type FET connected between the input terminal and the output terminal, and a gate terminal connected to the output terminal of the AND gate, and connected between the input terminal and the output terminal Second conductivity type FET
And is configured.

According to a third aspect of the present invention, an inverter circuit including a Schmitt trigger circuit is cascaded in an odd number of stages between an input terminal and an output terminal, and an oscillating capacitance is connected between the input terminal and a power source. In a CR oscillator in which an oscillation resistor is connected between the input terminal and the output terminal, a first inverter circuit that receives an input signal applied to the input terminal, and the Schmitt trigger circuit that receives the input signal Including a second inverter circuit cascade-connected to even-numbered stages, a first conductivity type FET having a gate terminal connected to an output terminal of the first inverter circuit, and a gate terminal of the second inverter circuit. A first conductivity type FET connected to an output terminal of the circuit is connected in cascade between the input terminal and the output terminal, and a gate terminal is an output terminal of the first inverter circuit. A second conductive type FET connected to the output terminal of the second inverter circuit and a second conductive type FET connected to the output terminal of the second inverter circuit are connected in cascade between the input terminal and the output terminal. It

The invention according to claim 4 is the C according to claim 1.
In the R oscillator, the first conductivity type FET and the second conductivity type F whose conduction is controlled similarly to the first conductivity type FET.
A second conductivity type FET whose conduction is controlled similarly to ET is connected in series between a high power source and a low power source, and a series connection point is connected to the output terminal.

The invention according to claim 5 is the C according to claim 2.
In the R oscillator, a first conductivity type FET whose gate terminal is connected to the output terminal of the OR gate and a second conductivity type F whose gate terminal is connected to the output terminal of the AND gate
The ET is connected in series between the high-potential power source and the low-potential power source, and the series connection point is connected to the output terminal.

According to a sixth aspect of the present invention, an inverter circuit including a Schmitt trigger circuit is cascade-connected in an odd number of stages between an input terminal and an output terminal, and an oscillating capacitance is connected between the input terminal and a power source. In a CR oscillator in which an oscillation resistor is connected between the input terminal and the output terminal, a first inverter circuit that receives an input signal applied to the input terminal, and the Schmitt trigger circuit that receives the input signal Of the first inverter circuit, the second inverter circuit connected in cascade in an even number of stages, the OR gate for inputting the output signal of the first inverter circuit and the output signal of the second inverter circuit, and Output signal and the second
AND gate for inputting the output signal of the inverter circuit, and a first conductivity type FET string in which each gate terminal is connected to the output terminal of the OR gate and cascade-connected between the input terminal and the output terminal. And a second conductivity type FET string in which each gate terminal is connected to the output terminal of the AND gate and which is cascade-connected between the input terminal and the output terminal, and the gate terminal is the first inverter circuit. Of the first conductive type FET connected to the output terminal of the first conductive type FET and connected between the cascade connection point of the first conductive type FET row and the high-potential power source, and the gate terminal to the output terminal of the first inverter circuit. FETs of the second conductivity type that are connected and are connected between the cascade connection point of the second conductor type FET row and the low-potential power source.
And is configured.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a CR oscillator according to an embodiment of the invention described in claim 1 or 2, and FIG. 2 is a diagram showing a timing chart of the oscillator shown in FIG.

In FIG. 1, in the CR oscillator of this embodiment, inverter circuits 4 and 5 including a Schmitt trigger circuit 3 are cascade-connected in an odd number of stages (3 stages) between an input terminal 1 and an output terminal 2, and In the CR oscillator in which the oscillation capacitance 6 is connected between the terminal 1 and the ground and the oscillation resistance 7 is connected between the input terminal 1 and the output terminal 2, the input terminal 1
An inverter circuit 8 for receiving an input signal applied to the inverter circuit, an inverter circuit 9 for receiving the input signal and cascade-connected in an even number of stages including the Schmitt trigger circuit 3, an output signal of the inverter circuit 8 and an output signal of the inverter circuit 9. And a NOR gate 1 for inputting
An inverter circuit 11 that receives an output signal of 0; a NAND gate 12 that inputs the output signal of the inverter circuit 8 and the output signal of the inverter circuit 9;
An inverter circuit 13 that receives the output of the gate 12 and a gate terminal connected to the output terminal of the inverter circuit 11 are connected between the input terminal 1 and the output terminal 2 and are in a conductive state for a certain period within the charging period of the oscillation capacitor 6. The P-channel FET 14 controlled by the control circuit and the gate terminal are connected to the output terminal of the inverter circuit 13, and are connected between the input terminal 1 and the output terminal 2 to be in a conductive state for a certain period within the discharge period of the oscillation capacitor 6. It is configured to include a controlled N-channel FET 15.

In such a configuration, the inverter circuit 5 connected to the output terminal 2 (hereinafter referred to as an output buffer)
The FET 16 of the P channel changes from the OFF state to the ON state and the FET 14
Is turned on, and the ON resistance of the FET 14 changes the oscillation resistance 7
Are connected in parallel with each other, thereby offsetting an increase in the ON resistance of the FET 16 of the output buffer 5 and suppressing fluctuations in the apparent resistance value connected between the input terminal 1 and the output terminal 2. On the other hand, on the other hand, the N-channel FET 17 of the output buffer 5 is turned on from the off state to the on state, and the FET 15 is turned on for a certain period of time during which the oscillation capacitance 6 is discharged. So that the FE of the output buffer 5 is connected.
The increase of the on-resistance of T17 is offset to suppress the fluctuation of the apparent resistance value connected between the input terminal 1 and the output terminal 2.

Specifically, as shown in FIG. 2, the threshold voltage (Vth) of the inverter circuit 8 is set to the Schmitt voltage width (VthH) of the hysteresis characteristic of the Schmitt trigger circuit 3.
Try to set it at about the midpoint of. As a result, FIG.
As shown in FIG. 3, the inverter circuit 11 is provided at the rising of the input signal until the input signal reaches VthH of the Schmitt trigger circuit 3 after reaching the Vth of the inverter circuit.
A pulse signal is output from the FET 14, and the FET 14 is turned on during this period.

On the other hand, at the falling edge of the input signal, a pulse signal is output from the inverter circuit 13 until the input signal reaches VthH of the Schmitt trigger circuit 3 after reaching the Vth of the inverter circuit 8, and during this period the FET 15
Is turned on.

FET1 whose conduction is controlled in this way
The on-resistances of 4 and 15 are set as described below.

The cycle of the CR oscillator is T, and the FETs 14 and 15 are
Is Rt, the resistance value of the oscillation resistor 7 is R, the on resistance value of the output buffer 5 in the linear operation region is Rd, and the oscillation capacitance value is C, the cycle T is (CR ) Was proportional to.

However, in the operating region where the ON resistance of the output buffer 5 is affected by the decrease in the power supply voltage, the time constant is C.multidot.
(R + Rd), and the cycle T increases. In the above embodiment, the time constant is C · (R · Rt · (R + Rt) + R by inserting the FETs 14 and 15 between the input and output terminals.
d). Here, by setting 1 >> Rt / (R + Rt), the increased Rd is offset.

The ON resistance of the FETs 14 and 15 is, for example, roughly 0.05, assuming a delay of about 5%.
It is calculated from × C · R = C · (R · Rt / (R + Rt), and Rt = R / 20, which is set to about 1/20 or less of the resistance value of the oscillation resistor 7.

In this way, during the charging / discharging period of the oscillation capacitor 6, the FE is inverted after the inverter circuit 8 is inverted according to the input signal and before the Schmitt trigger circuit 3 is inverted.
The T14 or the FET 15 is turned on. As a result, the apparent oscillation resistance connected between the input and output terminals decreases, the output buffer 5 always operates in the non-linear operation region, and a stable oscillation frequency can be obtained even if the power supply voltage decreases. You can

FIG. 3 is a diagram showing a configuration of a CR oscillator according to an embodiment of the invention described in claim 3, and FIG. 4 is a diagram showing a timing chart of the oscillator shown in FIG.

Referring to FIG. 3, in the CR oscillator of this embodiment, inverter circuits 4 and 5 including a Schmitt trigger circuit 3 are cascade-connected in an odd number of stages between an input terminal 1 and an output terminal 2, and the input terminal 1 and the ground are connected. In the CR oscillator in which the oscillation capacitance 6 is connected between the input terminal 1 and the output terminal 2, and the oscillation resistor 7 is connected between the input terminal 1 and the output terminal 2, an inverter circuit 18 that receives an input signal applied to the input terminal 1 A P-channel FET 22 having a gate terminal connected to the output terminal of the inverter circuit 18 and a gate terminal of the inverter circuit 20 is provided having an inverter circuit 20 that receives the signal and that is connected in cascade to an even number of stages including the Schmitt trigger circuit 3. The P-channel FET 23 connected to the output terminal is connected in cascade between the input terminal 1 and the output terminal 2, and the gate terminal is the output of the inverter circuit 18. FE of connected N-channel to a terminal
An N-channel FET 25 having a gate terminal connected to the output terminal of the inverter circuit 20 is connected in cascade between the input terminal 1 and the output terminal 2.

Even in such a configuration, the FETs 22 and 23 or the FETs 24 and 25 are controlled in conduction as in the configuration shown in FIG. 1, and the same effect as that of the embodiment shown in FIG. 1 can be obtained.

FIG. 5 is a diagram showing the configuration of a CR oscillator according to an embodiment of the invention as defined in claim 4 or 5.

The feature of the embodiment shown in FIG. 5 resides in that in the CR oscillator shown in FIG.
A buffer circuit is provided in which the ET 26 and an N-channel FET 27 whose gate terminal is connected to the output terminal of the inverter circuit 13 are connected in series between a high-potential power source and a low-potential power source, and the series connection point is connected to the output terminal 2. It is in.

With such a structure, the same effect as that of the embodiment shown in FIG. 1 can be obtained, and the load of the output buffer 5 is increased due to the decrease of the power supply voltage.
A new buffer circuit is provided to compensate for this and a larger output current can be taken.

FIG. 6 is a diagram showing a configuration of a CR oscillator according to an embodiment of the invention described in claim 6, and FIG. 7 is a diagram showing a timing chart of the oscillation circuit shown in FIG.

The feature of the embodiment shown in FIG. 6 lies in that the FET shown in FIG. 1 is added to the CR oscillator shown in FIG.
P-channel FET 28 and FET in which 14 is connected in cascade
Instead of 29, a P-channel FET 30 having a gate terminal connected to the output terminal of the inverter circuit 8 is inserted between the cascade connection point (node a) of the FETs 28, 29 and the high-potential power source, and the FET 15 shown in FIG. Instead of the N-channel FETs 31 and 32 connected in cascade, FETs 31 and 32
This is because an N-channel FET 33 having a gate terminal connected to the output terminal of the inverter circuit 8 is inserted between the cascade connection point (node b) of FIG.

In such a configuration, when the output buffer 5 is switched, the FETs 28, 29 or FE are
When T31 and T32 are not cut off yet, the current may flow back to the oscillation capacitor 6 connected to the input terminal 1. Therefore, when the output buffer 5 switches,
By turning on the ET 30 or the FET 33 and letting the reverse current flow to the power supply, the reverse current can be prevented, whereby a stable oscillation frequency can be obtained.

[0035]

As described above, according to the present invention, the on resistance of the FET is inserted in parallel with the oscillation resistance so as to offset the increase in the on resistance of the output buffer. The output buffer can be operated in a non-linear region, and a stable oscillation frequency can be obtained even at a low power supply voltage.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a CR oscillator according to an embodiment of the invention described in claim 1 or 2.

FIG. 2 is a diagram showing a timing chart of the oscillator shown in FIG.

FIG. 3 is a diagram showing a configuration of a CR oscillator according to an embodiment of the invention as set forth in claim 3;

FIG. 4 is a diagram showing a timing chart of the oscillator shown in FIG.

FIG. 5 is a diagram showing a configuration of a CR oscillator according to an embodiment of the invention described in claim 4 or 5;

FIG. 6 is a diagram showing a configuration of a CR oscillator according to an embodiment of the invention as set forth in claim 6;

7 is a diagram showing a timing chart of the oscillator shown in FIG.

FIG. 8 is a diagram showing a configuration of a conventional CR oscillator.

9 is a diagram showing input / output waveforms of the oscillator shown in FIG.

FIG. 10 is a diagram showing a voltage-current characteristic of an FET.

[Explanation of symbols]

1 Input Terminal 2 Output Terminal 3 Schmitt Trigger Circuit 4, 5, 8, 9, 11, 13, 13, 18, 20 Inverter Circuit 6 Oscillation Capacity 7 Oscillation Resistance 10, 12 Logic Gates 14, 15, 16, 17, 22, 22-33 FET

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-266373 (JP, A) JP-A-5-80874 (JP, A) JP-A-7-131300 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03K 3/00 H03B 5/00

Claims (6)

(57) [Claims] 1. An inverter circuit including a Schmitt trigger circuit is cascade-connected in an odd number of stages between an input terminal and an output terminal, and an oscillating capacitor is connected between the input terminal and a power source.
In a CR oscillator in which an oscillation resistor is connected between the input terminal and the output terminal, the CR oscillator is connected between the input terminal and the output terminal and is controlled to be conductive for a certain period within a charging period of the oscillation capacitance. A first conductivity type FET (field effect transistor), and a second conductivity type FET that is connected between the input terminal and the output terminal and is controlled to be conductive for a certain period within a discharge period of the oscillation capacitance. A CR oscillator comprising: a FET; and a control circuit for controlling conduction between the FETs based on an input signal given to the input terminal. 2. An inverter circuit including a Schmitt trigger circuit is cascaded in an odd number of stages between an input terminal and an output terminal, and an oscillating capacitance is connected between the input terminal and a power source.
A CR oscillator having an oscillation resistor connected between the input terminal and the output terminal, comprising: a first inverter circuit receiving an input signal applied to the input terminal; and a Schmitt trigger circuit receiving the input signal. A second inverter circuit that is connected in cascade in an even number of stages, a logical sum (OR) gate that inputs the output signal of the first inverter circuit and the output signal of the second inverter circuit, and the first inverter circuit. AND gate for inputting the output signal of the inverter circuit and the output signal of the second inverter circuit, and a gate terminal connected to the output terminal of the OR gate, between the input terminal and the output terminal. A first conductivity type FET connected to, and a gate terminal connected to the output terminal of the AND gate,
A CR oscillator having a second conductivity type FET connected between the input terminal and the output terminal. 3. An inverter circuit including a Schmitt trigger circuit is cascade-connected in an odd number of stages between an input terminal and an output terminal, and an oscillating capacitance is connected between the input terminal and a power source.
A CR oscillator having an oscillation resistor connected between the input terminal and the output terminal, comprising: a first inverter circuit receiving an input signal applied to the input terminal; and a Schmitt trigger circuit receiving the input signal. A second conductivity type FET having a second inverter circuit cascade-connected in an even number of stages, the gate terminal of which is connected to the output terminal of the first inverter circuit, and the gate terminal of which is the second inverter. F of the first conductivity type connected to the output terminal of the circuit
ET is connected in cascade between the input terminal and the output terminal, and the second conductivity type FET having the gate terminal connected to the output terminal of the first inverter circuit and the gate terminal of the second inverter circuit. A CR oscillator, wherein a second conductivity type FET connected to an output terminal is connected in series between the input terminal and the output terminal. 4. A first-conductivity-type FET and a second-conductivity-type FET whose conduction is controlled similarly to the first-conductivity-type FET.
2. A CR according to claim 1, wherein a second conductivity type FET whose conduction is controlled in the same manner as is connected in series between a high level power source and a low level power source, and a series connection point is connected to the output terminal. Oscillator. 5. A first conductivity type FET having a gate terminal connected to the output terminal of the OR gate and the gate terminal of the A-type FET.
FET of the second conductivity type connected to the output terminal of the ND gate
3. The CR oscillator according to claim 2, wherein is connected in series between a high-potential power source and a low-potential power source, and a series connection point is connected to the output terminal. 6. An inverter circuit including a Schmitt trigger circuit is cascade-connected in an odd number of stages between an input terminal and an output terminal, and an oscillating capacitor is connected between the input terminal and a power supply.
A CR oscillator having an oscillation resistor connected between the input terminal and the output terminal, comprising: a first inverter circuit receiving an input signal applied to the input terminal; and a Schmitt trigger circuit receiving the input signal. A second inverter circuit that is cascade-connected to an even number of stages, an OR gate that inputs the output signal of the first inverter circuit and the output signal of the second inverter circuit, and AND gates for inputting the output signal and the output signal of the second inverter circuit, and gate terminals of the AND gates are connected to the output terminals of the OR gates and are connected in cascade between the input terminals and the output terminals. A FET column of one conductivity type, each gate terminal of which is connected to an output terminal of the AND gate, and a cascade connection is provided between the input terminal and the output terminal. A second conductive type FET string and a gate terminal connected to an output terminal of the first inverter circuit, and a second conductive type FET string connected between a cascade connection point of the first conductive type FET string and a high potential power source. A first conductivity type FET, a gate terminal connected to the output terminal of the first inverter circuit, and a second conductivity type FET connected between a cascade connection point of the second conductor type FET row and a low potential power source. A CR oscillator having an FET.