JP3392439B2 - Input circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit in a semiconductor device, and more particularly to an input circuit having a malfunction prevention function.

[0002]

2. Description of the Related Art A semiconductor device is provided with an input circuit for taking in a signal input from the outside into the device. FIG. 11 shows an input circuit in this conventional semiconductor device. The input circuit 50 includes an inverter IN1 including a P-channel MOS transistor P1 and an N-channel MOS transistor N1, an inverter IN2 including a P-channel MOS transistor P2 and an N-channel MOS transistor N2, and a P-channel MOS transistor. P3 and.

The input terminal T _IN is connected to the gate of the P-channel MOS transistor P1 and the gate of the N-channel MOS transistor N1, and the output terminal T _NOUT is the drain of the P-channel MOS transistor P1 and the drain of the N-channel MOS transistor N1. P channel MOS
It is connected to the gate of the transistor P2, the gate of the N-channel MOS transistor N2 and the drain of the P-channel MOS transistor P3. The sources of the P-channel MOS transistors P1, P2 and P3 are connected to the power supply V _CC , and the N-channel MOS transistors N1 and N2 are connected.
The source of is connected to ground. P channel MO
The gate of the S transistor P3 is connected to the drain of the P channel MOS transistor P2 and the drain of the N channel MOS transistor N2.

The signal input to the input terminal T _IN is logically inverted by the inverter IN1 and output from the output terminal T _NOUT . The P-channel MOS transistor P3 has an output terminal T
It is a pull-up transistor that pulls up _NOUT , and the inverter IN2 is a feedback inverter that turns on / off the P-channel MOS transistor P3.

The input / output characteristics of the input circuit 50 are shown in FIG. The voltage change of the output signal due to the voltage change of the input signal will be described below. (1) When the input voltage changes from high level to low level When the input voltage is high level (logical value 1), the output voltage is low level (logical value 0), the node S1 is high level, P The channel MOS transistor P3 is off. Therefore, the threshold voltage of the logic change from the high level to the low level of the input circuit 50 is the P channel MO.
S transistor P1 and N channel MOS transistor N
It is determined by the size ratio of 1. Here, when the input voltage gradually decreases, the output voltage gradually increases, the node S1 gradually decreases, and changes along the transfer curve A in FIG. Along with this logical change, P channel M
The OS transistor P3 is gradually turned on, and when the logic change ends, the OS transistor P3 is completely turned on and the output voltage is pulled up to V _CC .

(2) When the input voltage changes from low level to high level When the input voltage is low level, the node S1 is low level, and the P-channel MOS transistor P3 pulls up the output voltage to high level. There is. Here, the inverter IN1 logically inverts due to the increase of the input voltage to change the output voltage to the low level, but the P-channel MOS
Since the transistor P3 pulls up the output voltage to the high level, the threshold voltage of the logic change of the input circuit 50 from the low level to the high level is the ratio of the sizes of the P-channel MOS transistor P1 and the N-channel MOS transistor N1. The value is shifted upward by the amount that the P-channel MOS transistor P3 is turned on than the value determined by. Therefore, when the input voltage gradually rises, as shown in FIG.
The logical change follows the transfer curve B in 2. As described above, since the input circuit 50 has an input / output characteristic with hysteresis, it is a circuit in which a logical malfunction due to the level fluctuation of the input signal does not easily occur.

[0007]

FIG. 13 shows a semiconductor device package. The semiconductor chip 51 is housed inside the package 52 and inputs and outputs various signals via the lead frame 53. As shown in the figure, the lead frame 53 has a parasitic inductance 54. In a semiconductor device that outputs a large current, a semiconductor device that operates at high speed, and the like, a large current flows from the power supply terminal 53a to the ground terminal 53b during the operation. When a large current flows between the power supply terminal 53a and the ground terminal 53b, induction generated by the parasitic inductances 54a and 54b even if the external power supply and the external ground to which the power supply terminal 53a and the ground terminal 53b are connected are in a steady state. The electromotive force causes noise (potential fluctuation) in the power supply V _CC and the ground inside the semiconductor chip 51. The noise becomes larger when the input signal or the output signal changes all at once. Due to the influence of this noise, there is a problem that the input circuit 50 shown in FIG. 11 erroneously determines the input signal level and causes a logic malfunction.

FIG. 14 shows how the threshold voltage of the input circuit 50 changes, which is the cause of the logic malfunction. V _CC is a power supply potential inside the semiconductor chip, and GND is a ground potential inside the semiconductor chip. V _IH is the high level of the input signal, V _IL is the low level of the input signal, and V _TH is the threshold voltage when the input circuit 50 is considered as a simple inverter.

Below, due to the above noise, the ground potential G
A case where ND rises and a case where power supply potential V _CC falls will be described. (1) When the ground potential GND rises When the ground potential GND rises, the threshold voltage V _TH of the input circuit 50 is determined by the voltage between the power supply potential V _CC and the ground potential GND. Therefore, as the ground potential rises, the threshold voltage also rises, and when the threshold voltage exceeds the high level (V _IH ) of the input signal as indicated by C in FIG. 14, the originally high level input signal goes low. The output signal changes to a high level because it is determined to be a level.
After that, when the ground potential decreases, the threshold voltage also decreases, the input signal is determined to be high level, and the output signal changes to low level. As a result, due to the rise of the ground potential, a logic malfunction occurs in which a pulse-like high level appears in the output signal although the high level input signal (V _IH ) has not changed.

(2) When the power supply potential V _CC is lowered Even when the power supply potential V _CC is lowered, the threshold voltage V _TH of the input circuit 50 is determined by the voltage between the power supply potential V _CC and the ground potential GND. To be done. Therefore, as the power supply potential decreases, the threshold voltage also decreases, and when the threshold voltage falls below the low level (V _IL ) of the input signal as indicated by D in FIG. 14, the input signal originally at the low level goes high. The output signal changes to the low level because it is determined to be the level. After that, when the power supply potential rises, the threshold voltage also rises, the input signal is determined to be low level, and the output signal changes to high level. As a result, a logic malfunction occurs in which a pulse-like low level appears in the output signal although the low-level input signal (V _IL ) has not changed due to the decrease in the power supply potential. As described above, in the input circuit 50 shown in FIG. 11, power supply noise (power supply potential V _CC and ground potential GN) is increased when high current output and high-speed input / output are achieved.
A logic malfunction is likely to occur due to (variation of D), and if the logic malfunction is prevented, there is a problem that a large current output and high speed input / output are sacrificed.

Therefore, an object of the present invention is to provide a high-speed operation, large-current output input circuit in which logic malfunction due to power supply noise is prevented.

[0012]

In order to achieve the above object, an input circuit of the present invention is provided with an input terminal and an output terminal.
The connected first circuit and the input of the first circuit
The second circuit connected to the output and the high-potential side power supply voltage
The control terminal is connected between the terminal and the output of the first circuit.
Conduction according to the output signal of the second circuit applied to the child
The first switching element to
Is a power supply noise detection that detects potential fluctuations in the low-potential-side power supply voltage.
Of the output circuit, the high-potential-side power supply voltage terminal, and the first circuit
The above-mentioned power supply noise detection that is connected between and is applied to the control terminal.
Current supply to the first circuit according to the output signal of the output circuit
And a second switching element for shutting off.

[0013]

SUMMARY OF] The input signal input to the circuit is input to the first circuit, is output from the first circuit. The second circuit is first
The first switch according to the logic state of the output terminal of the first circuit
The switching element is controlled, and the first switching element is turned on when the output terminal of the first circuit is at a high level .
The output terminal of the circuit is pulled up to the power supply potential. The power supply noise detection circuit detects a change in the power supply potential or the ground potential, and when the change is larger than a predetermined value, the first
The second switching element is turned off and the
The current supply to the circuit of No. 1 is cut off. The threshold voltage of this input circuit is substantially determined by the voltage value between the power supply potential and the ground potential. When noise occurs in the power supply potential or the ground potential, the power supply noise detection circuit detects the power supply noise and turns off the second switching element , thereby cutting off the current supply from the power supply potential to the first circuit . Therefore, when power supply noise occurs, the first
The voltage between the power supply potential and the ground potential is not applied to the path , and the threshold voltage determined by the voltage value between the power supply potential and the ground potential does not change. Since the threshold voltage does not fluctuate due to power supply noise, logical fluctuation due to power supply noise does not easily occur in this input circuit.

[0014]

EXAMPLES The present invention will be described below with reference to examples. A first embodiment of the input circuit of the present invention is shown in FIG. The input circuit 10 includes a signal input circuit 1 and a power supply noise detection circuit 2. The signal input circuit 1 includes an inverter IN1 including a P-channel MOS transistor P1 and an N-channel MOS transistor N1, an inverter IN2 including a P-channel MOS transistor P2 and an N-channel MOS transistor N2, and a P-channel MOS transistor. P3 and P channel MOS transistor MP1
Composed of and. The power supply noise detection circuit 2 is composed of a P-channel MOS transistor P11, an N-channel MOS transistor N11, a diode D1, and a capacitor C1.

The input terminal T _IN is connected to the gate of the P-channel MOS transistor P1 and the gate of the N-channel MOS transistor N1, and the output terminal T _NOUT is the drain of the P-channel MOS transistor P1 and the drain of the N-channel MOS transistor N1. P channel MOS
It is connected to the gate of the transistor P2, the gate of the N-channel MOS transistor N2 and the drain of the P-channel MOS transistor P3. Sources of P-channel MOS transistors P2, P3 and MP1, diode D
The anode of No. 1, the gate of the P-channel MOS transistor P11 and the gate of the N-channel MOS transistor N11 are connected to the power supply V _CC , and one electrode of the capacitor C1 and the N-channel MOS transistors N1 and N1.
The sources of 2, N11 are connected to ground. The gate of the P-channel MOS transistor P3 is connected to the drain of the P-channel MOS transistor P2 and the N-channel M.
It is connected to the drain of the OS transistor N2. P
The drain of the channel MOS transistor MP1 is connected to the source of the P channel MOS transistor P1, and the gate of the P channel MOS transistor MP1 is P
The drain of the channel MOS transistor P11 and N
It is connected to the drain of the channel MOS transistor N11. The cathode of the diode D1 is a capacitor C
The other electrode of 1 and the P-channel MOS transistor P
Connected to 11 sources.

The signal input to the input terminal T _IN is logically inverted by the inverter IN1 and output from the output terminal T _NOUT . The P-channel MOS transistor P3 has an output terminal T
It is a pull-up transistor that pulls up _NOUT , and the P-channel MOS transistor MP1 is a switch that cuts off the current supply to the inverter IN1. The inverter IN2 is a feedback inverter that turns on / off the P-channel MOS transistor P3. The power supply noise detection circuit 2 detects noise generated in the power supply and the ground and controls the P-channel MOS transistor MP1 to control the current supply to the inverter IN1.

Since the gate of the P-channel MOS transistor P11 and the gate of the N-channel MOS transistor N11 are connected to the power supply V _CC , the P-channel MOS transistor
The transistor P11 is always off, and the N-channel MOS transistor N11 is always on. Therefore, the node ND is at low level (logical value 0), and the P-channel MOS transistor MP1 is always on. In a steady state in which power supply noise does not occur, the P-channel MOS transistor MP1 is always on, so that the input circuit 10 has an input / output characteristic with hysteresis as in the conventional input circuit 50 shown in FIG. .

The internal voltage waveform of the power supply noise detection circuit 2 is shown in FIG. V _CC is the power supply potential and GND is the ground potential. When there is no power supply noise (changes in power supply potential V _CC and ground potential GND), the potential of the node S11 is V
_CC -V _f: a (V _f forward voltage drop of the diode D1), the capacitor C1 the voltage V _CC -V _f is charged. As described above, since the P-channel MOS transistor P11 is always off and the N-channel MOS transistor N11 is always on, the node N
D is low level.

The operation of the power supply noise detection circuit 2 when the ground potential GND rises and when the power supply potential V _CC falls will be described below. (1) When the ground potential GND rises In a steady state where there is no potential fluctuation in the ground potential GND, the potential of the node S11 is V _CC -V _f . The capacitor C1 is connected to this voltage V _CC between the ground and the node S11.
Since it tries to maintain −V _f , the node S11 also rises when the ground potential GND starts to rise. Node S11
When the potential of the diode starts to rise, the diode D1 is turned off. Further, the ground potential GND rises, and the node S1
When the potential of 1 becomes V _CC + V _TP (V _TP : threshold value of P-channel MOS transistor P11), P-channel MOS
The transistor P11 turns on. N channel MO
Since the gate of the S-transistor N11 is connected to the power supply V _CC , the N-channel MOS transistor N1 is always connected.
1 ON state. If the on-resistance value of the P-channel MOS transistor P11 is smaller than the on-resistance value of the N-channel MOS transistor N11, the potential of the node ND changes from the ground potential GND to the power supply potential V _CC due to the turn-on of the P-channel MOS transistor P11. It will be. In reality, the potential of the node ND is almost V
_Although it is _CC - _Vf , since _Vf is a small value, it is logically at a high level. Therefore, when the ground potential GND rises by V _f + V _TP or more, the power supply noise detection circuit 2 detects this rise in the potential as noise and changes the node ND from low level to high level to generate power supply noise. To notify.

(2) When the power supply potential V _CC decreases In the steady state where the power supply potential V _CC does not fluctuate, the potential of the node S11 is V _CC -V _f and the function of the capacitor C1 is as described above. Thus, the voltage between node S11 and ground potential GND is maintained at V _CC -V _f .
Here, when the power supply potential V _CC begins to drop, the diode D
1 is turned off. Further lowering the power supply potential V _CC, when the potential is V _CC -V _f -V _TP, P-channel MOS transistor P11 is turned on. Then, similarly to the case where the ground potential GND rises, the node N
The potential of D changes from the ground potential GND to V _CC -V _f . Therefore, when the power supply potential V _CC drops by V _f + V _TP or more, the power supply noise detection circuit 2 detects this potential drop as noise and changes the node ND from low level to high level to generate power supply noise. Notify 1.
In addition, the power supply potential V _CC is very low and the N-channel MOS
Even if the transistor N11 is turned off, it does not affect the operation of the power supply noise detection circuit 2.

As described above, the power supply noise detection circuit 2 has the potential increase of the ground potential GND and the power supply potential V.
The potential decrease of _CC is detected, and the signal input circuit 1 is notified as a level change of the node ND. As the power supply noise, there are cases where the ground potential GND drops and the power supply potential V _CC rises, but these power supply noises are a reaction after the rise of the ground potential GND or the drop of the power supply potential V _CC. Occurs as. Therefore, the ground potential G
It is sufficient if the rise in ND or the fall in power supply potential V _CC can be detected as power supply noise.

Next, the operation of the signal input circuit 1 when the power supply noise detection circuit 2 detects power supply noise will be described. (1) When the input voltage (input terminal T _IN ) is at low level In a steady state in which no power supply noise is generated, the node ND is at low level, so the P-channel MOS transistor MP1 is on. When the input voltage is low level, the output voltage (output terminal T _NOUT ) is high level, the node S1 is low level, and the P channel MOS
The transistor P3 is in the ON state and pulls up the output voltage. When power supply noise occurs, the node ND changes to high level, the P-channel MOS transistor MP1 is turned off, and the current supply to the output terminal T _NOUT is stopped. However, since the P-channel MOS transistor P3 is in the ON state and the output voltage is kept at the high level, the input circuit 10 does not cause a logic malfunction.

(2) When the input voltage (input terminal T _IN ) is at high level In a steady state in which no power supply noise is generated, the node ND is at low level, so the P-channel MOS transistor MP1 is on. When the input voltage is high level, the output voltage (output terminal T _NOUT ) is low level, the node S1 is high level, and the P-channel MOS
The transistor P3 is off. Here, when power supply noise occurs, the node ND changes to high level and P
The channel MOS transistor MP1 is turned off.
Here, since the P-channel MOS transistor P3 is also in the off state, no current is supplied to the output terminal T _NOUT , the output voltage does not change to the high level, and the input circuit 1
0 does not cause a logic malfunction. As described above, the input circuit 10 does not cause a logic malfunction even if power supply noise occurs.

A second embodiment of the input circuit of the present invention is shown in FIG. The input circuit 10a includes a signal input circuit 1a and a power supply noise detection circuit 2a. Inverter I
The transistor that cuts off the current supply to N1 is the N-channel MOS transistor MN1 and the P-channel MO transistor.
A connection point between the drain of the S transistor P11 and the drain of the N channel MOS transistor N11 and the N channel M
The inverter I is connected between the gate of the OS transistor MN1 and
The point where the NV1 is connected is that the input circuit 1 shown in FIG.
The difference is 0. The operation of the input circuit 10a is the same as that of the input circuit 10. The node ND is at a high level in a steady state where there is no power supply noise, and becomes a low level when power supply noise occurs, turning off the N-channel MOS transistor MN1 and cutting off the current supply to the inverter IN1.

FIG. 4 shows a third embodiment of the input circuit of the present invention. The input circuit 10b includes a signal input circuit 1b and a power supply noise detection circuit 2a. Inverter I
The difference from the input circuit 10a shown in FIG. 3 is that the transistor for cutting off the current supply to N1 is the NPN bipolar transistor Q1. The operation of the input circuit 10b is the same as that of the input circuit 10 and the input circuit 10a.
The node ND is at a high level in a steady state where there is no power supply noise, and goes to a low level when power supply noise occurs to turn off the NPN bipolar transistor Q1 and cut off the current supply to the inverter IN1.

A modification 1 of the power supply noise detection circuit applied to the input circuit of the present invention is shown in FIG. In the power supply noise detection circuit 2b, the diode D1 of the power supply noise detection circuit 2 shown in FIG. 1 is replaced with an NPN bipolar transistor. The diode D1 of the power supply noise detection circuit 2 is a P-channel MOS if it is an element exhibiting diode characteristics.
It may be a transistor or an N-channel MOS transistor.

A modification 2 of the power supply noise detection circuit applied to the input circuit of the present invention is shown in FIG. This power supply noise detection circuit 2c changes the diode D1 of the power supply noise detection circuit 2 shown in FIG.
Has been changed to. These power supply noise detection circuits 2b and 2c
The operation of is the same as that of the power supply noise detection circuit 2 shown in FIG.

FIG. 7 shows a fourth embodiment of the input circuit of the present invention. The input circuit 10d is composed of a signal input circuit 1d and a power supply noise detection circuit 2d, and is applied to an input circuit of a semiconductor device. The ground of the input circuit 10d is divided into two, and NGND is the input circuit 10d.
Is a ground for discharging a large current that flows during the switching operation, and GND is a logic-determining ground. The reason for dividing the ground into two is that a large current flowing at the time of switching of the input circuit 10d causes power source noise. By dividing the ground into two, the potential fluctuation of the ground GND for logic determination is small. Become.

The signal input circuit 1d includes an inverter IN1 including a P-channel MOS transistor P1 and an N-channel MOS transistor N1, an inverter IN2 including a P-channel MOS transistor P2 and an N-channel MOS transistor N2, and a P-channel MOS transistor N2. Channel MOS transistor P3 and NPN bipolar transistor Q
1, Q2, a resistor R1, and a diode D2. The power supply noise detection circuit 2d includes an NPN bipolar transistor Q11 and a P channel MOS transistor P.
11, and N-channel MOS transistors N11 and MN2
Composed of and.

The input terminal T _IN is connected to the gates of the P-channel MOS transistor P1 and the N-channel MOS transistor N1, and the output terminal T _NOUT is of the P-channel M.
The drain of the OS transistor P1, the drain of the N-channel MOS transistor N1, the drain of the P-channel MOS transistor P3, the P-channel MOS transistor P
2 and the gate of the N-channel MOS transistor N2. NPN bipolar transistor Q1 collector, P-channel MOS transistor P3
Of the N channel MOS transistor N1 and the emitter of the NPN bipolar transistor Q2 are connected to the power source V _CC.
N-channel MOS transistor N connected to D
The source of 2 is connected to NGND. P channel M
The gate of the OS transistor P3 is connected to the drain of the P-channel MOS transistor P2 and the drain of the N-channel MOS transistor N2. The base of the NPN bipolar transistor Q1 is the cathode of the diode D2.
And the collector of the NPN bipolar transistor Q2. The anode of the diode D2 is connected to the other end of the resistor R1.

NPN bipolar transistor Q11 collector and base, P-channel MOS transistor P11
Of the N-channel MOS transistor N11 and the gate of the N-channel MOS transistor N11 are connected to the power supply V _CC.
The source of the transistor N11 is connected to GND. The emitter of the NPN bipolar transistor Q11 is the gate of the N-channel MOS transistor MN2 and P
It is connected to the source of the channel MOS transistor P11. The drain of the P-channel MOS transistor P11 and the drain of the N-channel MOS transistor N11 are connected to the base of the NPN bipolar transistor Q2. The drain and source of the N-channel MOS transistor MN2 are connected to NGND, and this N-channel MOS transistor MN2 functions as a capacitor.

The signal input circuit 1d has substantially the same configuration as the signal input circuit 1b shown in FIG. 4, and its operation is similar to that of the signal input circuit 1b. The power supply noise detection circuit 2d has substantially the same configuration as the power supply noise detection circuit 2b shown in FIG. 5, and its operation is similar to that of the power supply noise detection circuit 2b. A resistor R1 and a diode D2 are connected in series between the base of the NPN bipolar transistor Q1 and the power supply V _CC , and the node S5 is pulled up to a high level. The node S5 is kept at a potential lower than the power source potential V _CC by the forward voltage drop (V _f ) of the diode D2. Since the node ND is at the low level in the steady state where the power supply noise is not generated, the NPN bipolar transistor Q2 is in the OFF state, the NPN bipolar transistor Q1 is in the ON state, and the power supply V _CC is supplied to the inverter IN1. It When power supply noise occurs and the node ND becomes high level, the NPN bipolar transistor Q2 is turned on and the node S5 is made low level, so that the NPN bipolar transistor Q1 is turned off and the inverter IN1 is disconnected from the power supply V _CC . The basic operation of the input circuit 10d is the same as that of the input circuit 10 shown in FIG.

FIG. 8 shows how power supply noise is generated in the simultaneous switching operation of the eight input circuits 10d. The horizontal axis represents time (unit: nsec), and the vertical axis represents voltage (unit: nsec).
V). In this simulation, are switched simultaneously enter (T _IN) of the input circuit 10d inputs of the input circuit 10d (T _IN) was kept at a high level, seven (7 bits) of one (1 bit) . Note that FIG.
The output at is the output signal of the inverter 60 connected to the output terminal ( _TNOUT ) of the input circuit 10d. As is clear from FIG. 8, the outputs (OU) of the seven input circuits 10d are
GND) when T) changes from high level to low level
And a large potential fluctuation occurs in NGND, and when the outputs (OUT) of the seven input circuits 10d change from low level to high level, a large potential fluctuation occurs in the power supply V _CC . At this time, one input circuit 10d whose input does not change
The output (OUT) has undergone a slight level fluctuation due to the power supply noise, but a logic malfunction has not occurred due to the function of the power supply noise detection circuit 2d. Although not shown in FIG. 8, it has been confirmed that a logical malfunction occurs in the conventional input circuit.

FIG. 9 shows the internal voltage of one input circuit 10d in which the input (T _IN ) does not change when the ground potential greatly changes in the simulation shown in FIG. The output (T _NOUT ) of the input circuit 10d has risen to about 2V due to the potential fluctuations of GND and NGND, but has not reached the level causing a logic malfunction.

In the simulation shown in FIG. 8, the internal voltage of one input circuit 10d in which the input (T _IN ) does not change when the power supply potential (V _CC ) greatly changes is shown in FIG.
It shows in 0. Despite the potential fluctuation of the power supply V _CC , the input circuit 1
The output (T _NOUT ) of 0d has a potential fluctuation of about 1V.

Needless to say, the input circuit of the present invention can have various configurations other than those mentioned as examples, and the above-mentioned examples are merely examples.

[0037]

As described above, the input circuit of the present invention does not cause a logic malfunction due to power supply noise which is a fluctuation of the power supply potential (V _CC ) or the ground potential. Further, since the input circuit of the present invention does not cause a logic malfunction even by a large power supply noise, by using the input circuit of the present invention in a semiconductor device, a large current output in the semiconductor device and a high-speed circuit operation of the semiconductor device are realized. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of an input circuit of the present invention.

FIG. 2 is a diagram showing an internal voltage waveform of the power supply noise detection circuit 2 shown in FIG.

FIG. 3 is a diagram showing a second embodiment of the input circuit of the present invention.

FIG. 4 is a diagram showing a third embodiment of the input circuit of the present invention.

5 shows a modification 1 of the power supply noise detection circuit 2 shown in FIG.
FIG.

6 shows a modification 2 of the power supply noise detection circuit 2 shown in FIG.
FIG.

FIG. 7 is a diagram showing a fourth embodiment of the input circuit of the present invention.

FIG. 8 is a diagram showing how power supply noise is generated in a simultaneous switching operation of eight input circuits 10d.

9 is a diagram showing the internal voltage of one input circuit 10d in which the input (T _IN ) does not change when the ground potential greatly changes in the simulation shown in FIG.

10 is a diagram showing the internal voltage of one input circuit 10d in which the input (T _IN ) does not change when the power supply potential (V _CC ) greatly changes in the simulation shown in FIG.

FIG. 11 is a diagram showing a conventional input circuit.

12 is a diagram showing input / output characteristics of the conventional input circuit shown in FIG.

FIG. 13 is a diagram showing a package of a semiconductor device.

FIG. 14 is a diagram showing how the threshold voltage of the conventional input circuit shown in FIG. 11 changes.

[Explanation of symbols]

1, 1a, 1b, 1d ... Signal input circuit 2, 2a, 2b, 2c, 2d ... Power supply noise detection circuit 10, 10a, 10b, 10d, 50 ... Input circuit 51 ... Semiconductor chip 52 ... Packages IN1, IN2 ... Inverters N1, N2, N11 ... N-channel MOS transistors P1, P2, P3, P11, MP1 ... P-channel M
OS transistor D1 ... Diode C1 ... Capacitor

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/00

Claims (5)

(57) [Claims] 1. A connection between an input terminal and an output terminal
A first circuit and a second circuit whose input is connected to the output of the first circuit.
Between the high voltage side power supply voltage terminal and the output of the first circuit
Output of the second circuit connected and applied to the control terminal
The first switching element that conducts according to the signal and the potential fluctuation of the high-potential-side power supply voltage or the low-potential-side power supply voltage
The power supply noise detection circuit for detection is connected between the high potential side power supply voltage terminal and the first circuit.
Output from the power supply noise detection circuit applied to the control terminal.
Cut off the current supply to the first circuit according to the force signal
An input circuit having a second switching element . 2. The power supply noise detection circuit is connected between a first node connected to a control terminal of the second switching element and the first node and a second node for control. A third switching element whose terminal is connected to the high-potential-side power supply voltage terminal and which is in a non-conducting state in a steady state; and a rectifying element connected between the high-potential-side power supply voltage terminal and the second node, The input circuit according to claim 1, further comprising a capacitive element connected between the second node and a low-potential-side power supply voltage terminal. 3. The power supply noise detection circuit is connected between the first node and a low potential side power supply voltage terminal, the control terminal is connected to the high potential side power supply voltage terminal, and is in a conductive state in a steady state. The input circuit according to claim 2, further comprising a fourth switching element. 4. The third switching element is a P-channel MOS transistor, the fourth switching element is an N-channel MOS transistor, and the anode of the rectifying element is connected to a high potential side power supply voltage terminal. The input circuit according to claim 3, which is a diode. 5. The first circuit and the second circuit are inverters each composed of a P-channel MOS transistor and an N-channel MOS transistor, and the first switching element and the second switching element are P-channel MOS. The input circuit according to claim 1, which is a transistor.