JP3316448B2 - Semiconductor power converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor power conversion device used for a main circuit of various devices such as an industrial machine and a railway car, and more particularly to a series multiple-coupled pulse width (PWM).
The present invention relates to a control power converter (inverter).

[0002]

2. Description of the Related Art Conventionally, a pulse width (P
WM) Control power converters (inverters) are known,
For example, JP-A-5-221775, JP-A-8-1403
No. 59 etc. exist. Hereinafter, with reference to FIG. 2, the serially multiplex-coupled pulse widths (P
The basic configuration of the WM) control inverter will be described. (FIG. 2 is a prior art, but is a basic configuration diagram of an inverter circuit to which the present invention is applied.) FIG. 2 shows a configuration of a general three-level inverter used for UVW three-phase power (voltage). is there. In the figure, DC voltages E and −E are supplied from terminals 1 and 2 to a capacitor bank unit 3.
Enter 9 The capacitor bank unit 39 includes:
A large two sets of large capacitors 4 and 5 are connected in series, and a terminal 3 having a neutral point potential NP and a terminal 1 having the potential E and a terminal 2 having the potential -E, which are the connection points, are provided. Input to the three-level inverter circuit 40.

Next, the three-level inverter circuit 40 will be described. In the three-level inverter circuit 40, the anodes of gate turn-off thyristors (hereinafter, referred to as GTO elements) 6, 10, and 14 are connected to the terminal 1 having the potential E. Diodes 18, 22, and 26 are connected in anti-parallel to the GTO elements 6, 10, and 14, respectively. The cathodes of the GTO elements 6, 10, and 14 are connected to the terminal 3 having the neutral point potential NP via clamp diodes 30, 32, and 34.
Similarly, the cathodes of the GTO elements 9, 13, and 17 are connected to the terminal 2 having the potential -E. And the G
Each of the TO elements 9, 13, and 17 has a diode 21,
25 and 29 are connected in anti-parallel. In addition, the GTO
The anodes of the elements 9, 13, 17 are connected to the neutral point connection terminal 3 via clamp diodes 31, 33, 35.

Further, between the GTO elements 6 and 9, GTO elements 7 and 8 and their antiparallel diodes 19 and 20 are connected in series.
Are connected to the load 41 from the connection terminal 36 between the GTO elements 7 and 8 to output a U-phase voltage. Similarly, between the GTO elements 10 and 13, the GTO elements 11, 12,
And its antiparallel diodes 23 and 24 are connected,
A connection terminal 37 between the elements 11 and 12 is connected to a load 41 to output a V-phase voltage. GTO elements 14 and 17
GTO elements 15, 16 and their anti-parallel diodes 27, 28 are connected in series between the GTO elements 15, 16,
A connection terminal 38 between the terminals 6 is connected to a load 41 to output a W-phase voltage.

In the three-level inverter circuit 40, a gate drive circuit 42 is connected to the gates of the GTO elements 6 to 17 constituting the circuit. The gate drive circuit 42 is driven by a gate pulse signal 45 output by a control circuit (or microprocessor) 43, and performs the switching operation of the GTO elements 6 to 17 described above.

A method of modulating a three-level inverter by the control circuit 43 is an asynchronous P-type modulation using a triangular wave comparison PWM modulation.
The WM modulation method is widely used. For GTO inverters with low switching frequency, those that require a wide modulation rate operation such as VVVF for electric vehicles, use synchronous / asynchronous switching control in which synchronous control is performed in the high inverter frequency region and asynchronous PWM control is switched in the low frequency region. There is also.

In general, these three-level inverters require only half the breakdown voltage of the switching element as compared with the conventional inverter because the neutral point potential NP is used, and have three stages of voltage levels. There are advantages such as a low rate.

[0008]

However, on the other hand, the neutral point created by the capacitor partial voltage fluctuates due to switching asymmetry due to asynchronous modulation and a large neutral point current. Has disadvantages. In order to suppress such neutral point fluctuation, by adding a zero-phase component to each phase voltage command given to the triangular wave comparison modulation circuit, the usage rate of the positive side capacitor and the negative side capacitor is suppressed, and the neutral point voltage fluctuation is reduced. A correction method has conventionally been used. (Japanese Unexamined Patent Publication No. 5-221775, etc.)

However, when asynchronous operation is performed by a three-level inverter of a low switching element such as a GTO element, there is a problem that the neutral point fluctuates, and the on / off switching of a thin pulse (several tens of microseconds) is prohibited depending on the element characteristics. , Causing large distortion due to harmonics. In particular, when using the synchronous or asynchronous switching method, an operation pattern having switching symmetry can be selected in the synchronous operation region, so that the neutral point fluctuation and harmonic distortion can be reduced. However, the carrier frequency is still large in the asynchronous PWM operation. Therefore, the problem of the harmonic distortion cannot be sufficiently avoided.

Further, it has been found that when switching from asynchronous PWM to synchronous control, large torque oscillation occurs, and a method for avoiding it has not been established in any conventional technology.

According to the present invention, in a conventional power converter employing a synchronous / asynchronous switching method, when switching from asynchronous PWM to synchronous control, a large torque vibration occurs. In the asynchronous PWM operation, the problem of the harmonic distortion is reduced. It is an object of the present invention to provide a semiconductor power conversion device capable of performing synchronous control of all operations and taking a control form that minimizes waveform distortion of all operations, noting that it cannot be sufficiently avoided.

[0012]

SUMMARY OF THE INVENTION The technical features of the present invention are as follows. In order to enable synchronous control of all operations and minimize waveform distortion of all operations, all of them exhibit switching symmetry. Alternatively, the distortion rate is calculated in advance for some of the waveforms, and the modulation rate and the value of the time variable that minimizes the distortion rate at the modulation rate are stored in order to calculate the waveform data that minimizes the distortion rate. In other words, a time data table is provided.

That is, according to the present invention, a control circuit (microprocessor) for performing a switching operation of a GTO element constituting a series multiplexed three-level inverter circuit whose output voltage is controlled by pulse width modulation control has one or more data tables. And a switching power supply for the GTO element based on a gate pulse signal generated based on data read from the data table. The waveform data table of the switching pattern indicating the ON / OFF state for one control cycle of each of the UVW-phase GTO elements includes the waveform data table of the UVW-phase GTO elements.
Symmetry is maintained under the condition of odd multiple (n ≧ 1) of small switching.
While suppressing the neutral point potential fluctuation affected by the load
A shape data table is created, and a relationship between a modulation rate at the time of minimum distortion and a variable relating to the state output time thereof is converted into a time data table, and a variable relating to a state output time at a certain modulation rate is read from the time data table. The gate pulse signal is generated based on data obtained by setting the variable value of the gate pulse signal.

According to this invention, a simple waveform data table of the switching pattern is created, and the relationship between the modulation rate at the time of the minimum distortion and the variable relating to the state output time is converted into a time data table. By reading variables from the time data table and setting the variable values in the waveform data table, all modulation is possible only by synchronous control, switching symmetry is maintained, low switching frequency and low harmonics Driving becomes possible. Further, since the neutral point fluctuation is suppressed from the time of determining the switching pattern, a complicated neutral point suppressing circuit becomes unnecessary.

A technical feature of the invention according to claim 2 is that, in order to enable synchronous control of all operations and minimize waveform distortion of all operations, all of the elements exhibiting switching symmetry are provided.
Alternatively, the distortion rate is calculated in advance for some of the waveforms, and in order to calculate the waveform data that minimizes the distortion rate, the relationship between the modulation rate and a variable related to the time at which the distortion rate is minimized at the modulation rate is calculated. Is to formulate.

That is, according to the present invention, a control circuit (microprocessor) for performing a switching operation of a GTO element constituting a series multiplex type three-level inverter circuit in which an output voltage is controlled by pulse width modulation control is provided. Alternatively, a plurality of data tables are incorporated, and the three-phase voltage of the UVW is configured to perform a switching operation of the GTO element based on a gate pulse signal generated based on data read from the data table. In the semiconductor power conversion device, as a waveform data table of a switching pattern indicating an ON / OFF state for one control cycle of the GTO element of each of the UVW phases,
Odd number (n ≧ 1) of the minimum switching of the GTO element
Neutrality potential change affected by load while maintaining symmetry
Create multiple waveform data tables to suppress motion, and linearly approximate the relationship between time variable and modulation rate at minimum distortion
The time for a certain modulation rate is obtained from the approximate expression
The gate pulse signal is generated based on data obtained by calculating and substituting the time into the waveform data table.

According to this invention, a simple waveform data table showing a switching pattern is created, a relational expression between a time variable at the time of minimum distortion and a modulation factor is obtained, and the time is substituted into the waveform data table. All modulation is possible only by synchronous control, the switching symmetry is maintained,
Operation at a low switching frequency and low harmonics becomes possible. Further, since the neutral point fluctuation is suppressed from the time of determining the switching pattern, a complicated neutral point suppressing circuit becomes unnecessary.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to an embodiment shown in the drawings. However, the dimensions, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention but to merely illustrative examples unless otherwise specified.

[First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS. FIG.
FIG. 2 is a control block diagram showing an internal configuration of a control circuit 43 used in the level inverter circuit, which is configured as a control circuit or a microprocessor (hereinafter, referred to as a microprocessor 43). 1, an A / D converter 46, a V / f converter 47, a data table 49, and a pulse converter 50 are built in a microprocessor 43, and the microprocessor 43 operates the three-level inverter circuit 40. When the frequency command 45 is input, the operating frequency command 45 is A / D-converted by the A / D converter 46 and then converted into a modulation rate voltage command 48 by the V / f conversion function of the V / f converter 47. Is converted. The operation frequency command 45 and the modulation rate voltage command 48 from the V / f converter 47
From the data table 49 of the state (switching pattern) for one control cycle and the state output time for outputting the state
Is read.

As will be described later, the data table 49 suppresses the neutral point fluctuation while maintaining the switching symmetry by the synchronous control under the input conditions of the operation frequency command 45 and the modulation rate voltage command 48, and suppresses the output waveform distortion. Is a data array that can be improved as much as possible. The data read from the data table 49 is input to the pulse converter 50, and the converter 50 outputs the gate pulse signal 4
4 is output to the gate drive circuit 42.

Next, the data table 49 of the microprocessor 43 can adopt a data array which can suppress the neutral point fluctuation and improve the output waveform distortion while maintaining the switching symmetry. Is specifically described.

First, the switching pattern of the three-level inverter and the switching conditions will be described with reference to FIG. FIG. 3 shows GT in each phase of U, V and W.
It is a table | surface figure which shows the state definition of the 3 level switching pattern of O element 6-17. According to the state definition table of FIG.
The U-phase switching pattern for setting the potential of the phase output terminal 36 to + E is such that the GTO elements 6 and 7 conduct, the GTO element 8
9 is in a non-conductive state. State =
Defined as 1. Further, the potential of the U-phase output terminal 36 is set to -E
The switching pattern of the U-phase is GTO element 6,
7 is in a non-conductive state, and the GTO elements 8 and 9 are in a conductive state. This is defined as state = -1. Furthermore,
The U-phase switching pattern for setting the potential of the U-phase output terminal 36 to the neutral point potential NP is such that the GTO elements 6 and 9 are non-conductive,
This is a case where the GTO elements 7 and 8 are conducting.
This is defined as state = 0. The same applies to the three-level switching patterns of the V-phase GTO elements 10 to 13 and the W-phase GTO elements 14 to 17.

FIG. 4 is a table showing the correspondence between the U, V, and W phase states and the line voltage of the three-level inverter based on FIG.
As can be understood from this figure, there are 27 switching states of the three-level inverter according to the definition of FIG. Now, among the state numbers indicating the 27 cases, 0 to 7,
In each of the state numbers 26, since the neutral point potential 3 is not connected to the load 41, the neutral point voltage does not change.
3 connects + E, -E, and NP to the load.
The rise and fall of the neutral point potential 3 are the U phase 36 of the load output voltage,
It is determined by the phases of the V phase 37 and the W phase 38 and the load power factor. The neutral point voltage of the state numbers 14, 16, 18, 20, 22, 24 is (1, 0) or (0, 0) between the U / V / W phases.
Ascending due to the state of 1), state numbers 15, 17, 1
The neutral point voltage of 9, 21, 23, 25 drops because there is a (-1, 0) or (0, -1) state between the U / V / W phases.

Next, conditions for determining the switching pattern of the three-level inverter will be described. One of the factors that must be considered in determining a switching pattern is that only one switching state can transition. For example, in FIG.
It is possible to shift from (U / V / W phase state (1, -1, -1)) because the state number 8 in which only the V phase level is changed from -1 to 0
(U / V / W phase state: 1, 0, -1), 13 where only the W phase level is changed from -1 to 0 (U / V / W phase state: 1,-)
1, 0), 15 (0, 0) where only the U-phase level is changed from 1 to 0
-1, -1) only. That is, since the U-phase level changes by two levels (1 → −1) from state numbers 1 to 0, it is impossible to shift, and from state numbers 1 to 14, the V-phase level and the W-phase level are simultaneously − Since it changes from 1 to 0 and simultaneous switching of a plurality of phases occurs, it is impossible to shift.

The next consideration is the restriction of the simultaneous switching inhibition time and the minimum pulse time. Next, how to create a data table that suppresses neutral point fluctuation while maintaining the switching symmetry will be described with reference to FIGS. FIG. 5 (A)
Is a graph of the U, V, W phase potentials and UV line voltage waveforms for one cycle of the three-level inverter with the minimum number of switching times (12 state changes) output from the data table shown in the control block diagram of FIG. ) Is a state transition table at that time. FIG. 5 shows the U, V, W phase potentials, UV line voltage, and UV voltage for one cycle at the time of three-level minimum switching (n = 1) in consideration of the above-described restrictions and the symmetry of the waveform by the synchronous control. An example of the state transition table is shown. In the neutral point variation in the state transition table, only the component affected by the load remains. Another pattern in the number of times of switching may be that the neutral point rising period and the falling period in one cycle cancel each other out, and the fluctuation becomes equivalently approximately zero.

FIG. 6A shows a state change (36 state changes) three times (n = 3) the minimum switching time outputted by the data table shown in the control block diagram of FIG.
-Level inverters U, V, W phase potential and UV when
A voltage waveform graph showing the line voltage waveform, and (B) is a state transition table at that time. In particular, switching is required to be three times as large as that in FIG. 5 in consideration of the switching restriction and the symmetry of the waveform by the synchronous control. U, V, W phase potential for one cycle, U
An example of the V line voltage is shown.

The neutral point fluctuation in the state transition table of FIG. 6B includes a component influenced by the load and a component in which the neutral point potential rising period and the falling period in one cycle cancel each other. I do. Other state transition patterns include only the component affecting the load, or only the case where the rising component and the falling component are mixed. In general, when considering a line voltage waveform having symmetry under the condition of an odd multiple of the minimum switching shown in FIG. 5, only the load-dependent component needs to be considered for the fluctuation of the neutral point potential.

Therefore, if the line voltage waveform is patterned in advance to create a data table such as the state transition table shown in FIG. 6B, the neutral point fluctuation can be maintained while maintaining the switching symmetry. It can be said that a gate pulse signal output that suppresses only the load-dependent component is possible. Next, a method of creating a data table that minimizes waveform distortion will be described with reference to FIG.
And FIG.

FIG. 7 shows the relationship between the modulation factor and the distortion factor in the UV line voltage during the state transition of FIG. 6 in a dot-like pattern. 8 shows an example of the relationship between the modulation factor and the distortion factor in the UV line voltage during the minimum distortion operation shown in FIGS. 5 and 6, and a thin solid line of n = 1 corresponds to the case of the minimum number of switching times in FIG. The n = 3 square dot connection line indicates a state three times as large as the minimum switching. Next, the respective graphs will be described.

At the time of the minimum (12 times) switching shown in FIG.
= 1), each state output time is represented by f (operating frequency command 46) indicating a frequency command and a indicating modulation rate.
(Modulation rate voltage command 48). That is, there is only one waveform for a given modulation factor operation.

On the other hand, according to the state transition table at the time of switching 36 times in FIG. 6, each state output time can be considered in several ways by two variables d and q relating to the state output time in addition to the frequency command f and the modulation factor a. Can be. That is, it can be said that various waveforms exist for a certain modulation rate operation. (In general, the number of output time variables at the time of minimum switching × n (n ≧ 1 is an integer) is n−1).

When the distortion rates are calculated for all the waveform patterns determined in this way, and the relationship between the modulation rate and the distortion rate is plotted, a dot pattern as shown in FIG. 7 is obtained. At this time, in the case of n = 1 shown in FIG. 5, the distortion rate is also determined to be 1: 1 with respect to the modulation rate. Therefore, for a certain modulation rate operation, there is only one waveform as shown by the solid line in FIG. Although not present, as shown in FIG. 6, when n = 1 is not satisfied, as is apparent from the plot of the relationship between the UV line voltage modulation rate and the distortion rate at n = 3 in FIG. Thus, there are a plurality of distortion rates. Here, the plot is limited to only the point having the smallest distortion rate in each modulation rate when n = k (k is an integer greater than 1). The line indicated by the square dot connection line in FIG. 7 corresponds to the minimum distortion point of n = 3.

In this way, if the relationship between the modulation rate and the minimum distortion rate for n ≧ 1 is blotted and the waveform data with the smallest distortion is used as a data table, operation with minimum waveform distortion is possible. 8, a solid line (n = 1) and a square dot connection line (n = 3) in FIG.
The operation pattern is switched at the intersection (modulation rate: A), and in the region where the modulation rate ≧ A, the solid line (n =
The operation is performed according to the operation pattern shown in 1), and when the modulation ratio <A, the operation pattern may be switched to the operation pattern along the square dot connection line (n = 3) having the minimum distortion rate at n = 3.

Therefore, according to the present embodiment, a simple waveform data table of the switching pattern is created as shown in FIG. 8, and the modulation rate at the time of the minimum distortion and the state output time (see FIG. 5B) are changed. Is converted into a time data table, a variable relating to the state output time at a certain modulation rate is read from the time data table, and only by setting the variable value in the waveform data table, all modulation can be performed only by synchronous control. Switching symmetry is maintained, and operation with low harmonics and low switching frequency becomes possible. Further, since the neutral point fluctuation is suppressed from the time of determining the switching pattern, a complicated neutral point suppressing circuit becomes unnecessary.

[Embodiment 2] However, according to the above embodiment, a waveform data table of the switching pattern and a time data table of the relationship between the modulation factor at the time of the minimum distortion and the variable relating to the state output time are required. Therefore, in the second embodiment, the relationship between the modulation rate and the time variable is converted into a substantially linear approximation without forming a time data table. Since the specific configuration of the present embodiment is the same as that of the first embodiment, FIGS. 1 to 8 are applied as they are, and thus the operation of the present embodiment will be described based on FIGS. In the present embodiment, after obtaining the relationship between the modulation rate and the minimum distortion rate when n ≧ 1 in the first embodiment, the relationship between the modulation rate and the time variable at the time of the minimum distortion is plotted to obtain a linear approximation. is there.

FIG. 9 is a graph diagram in which the relationship between the time variables d and q and the modulation factor a in the minimum distortion operation of n = 3 in FIG. 8 is linearized. For example, in this figure, n = 3 in FIG. Plots the relationship of the variables d and q (refer to FIG. 6B for d and q) with respect to the modulation rate and time at the time of the minimum distortion, and a triangular plot diagram shows a linear approximation line of the time variable d and a square. The plot is a linear approximation of the time variable q.

Therefore, as shown in FIGS. 8 and 9, the relationship between the minimum distortion data diagram and the time variable plot diagram can be approximated by a linear approximation. FIG. 10 shows a waveform obtained by using this approximate expression in accordance with the waveform data table of FIG. 6 and calculating the distortion rate.

FIG. 10 shows a linear approximation of the relationship between the modulation factor and the distortion factor during the minimum distortion operation and the relationship between d, q and the modulation factor.
FIG. 8 shows the relationship between the UV line voltage modulation rate and the distortion rate obtained from the (n = 3) data table.
Is a diagram of minimum distortion data, and a white square dot connection line is a diagram obtained by linearly approximating the relationship between d and q and the modulation factor.

According to this, the distortion of the waveform simplified by the linear approximation (white square dot connection line) and the minimum distortion data read from the table (the minimum distortion data diagram shown in FIG. 8) are almost similar. . From these results, it can be said that by expressing the modulation rate and the time variable by a certain approximate expression, an operation close to the minimum waveform distortion can be performed.

Therefore, according to the present embodiment, a simple waveform data table showing the switching pattern is created, a relational expression between the time variable at the time of minimum distortion and the modulation factor is obtained, and the time is substituted into the waveform data table. Therefore, all the modulation can be performed only by the synchronous control, the switching symmetry is maintained, and the operation with a low switching frequency and few harmonics can be performed. Further, since the neutral point fluctuation is suppressed from the time of determining the switching pattern, a complicated neutral point suppressing circuit becomes unnecessary.

[0041]

According to the first aspect of the present invention, the simple waveform data table of the switching pattern is read from the time data table showing the relationship between the modulation factor at the time of the minimum distortion and the variable relating to the state output time. By simply setting the variable value of the state output time at the modulation rate, all modulation can be performed only by synchronous control, switching symmetry is maintained, and operation at a low switching frequency and low harmonics becomes possible. Further, since the neutral point fluctuation is suppressed from the time of determining the switching pattern, a complicated neutral point suppressing circuit becomes unnecessary.

According to the second aspect of the present invention, a simple waveform data table showing a switching pattern is created,
On the other hand, by simply obtaining the relational expression between the time variable and the modulation factor at the time of the minimum distortion and substituting the time into the waveform data table, all the modulation can be performed only by the synchronous control, the switching symmetry is maintained, and the low switching is maintained. Operation with less harmonics at the frequency becomes possible. Further, since the neutral point fluctuation is suppressed from the time of determining the switching pattern, a complicated neutral point suppressing circuit becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a control block diagram showing an internal configuration of a control circuit (microprocessor) in FIG. 2 according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a three-level inverter circuit which is also a prior art and to which the present invention is applied.

FIG. 3 shows a GTO element 3 in each of U, V, and W phases in FIG. 2;
It is a state definition table figure of a level switching pattern.

FIG. 4 shows U, V, three-level inverters based on FIG.
It is a correspondence table figure of a W-phase state and line voltage.

FIG. 5 is a diagram showing the U-, V-, and W-phase potentials and UV line voltage waveforms (A) for one cycle of a three-level inverter with the minimum number of switchings output by the data table shown in the control block diagram of FIG. It is a figure which shows a state transition table (B).

6 shows three-level inverters U, V, W-phase potentials and UV rays when a state change (36 state changes) three times the minimum switching time outputted by the data table shown in the control block diagram of FIG. FIG. 6 is a diagram showing an inter-voltage waveform (A) and a state transition table (B) at that time.

FIG. 7 is a dot pattern graph showing an example of a relationship between a modulation factor and a distortion factor in a UV line voltage during the state transition of FIG.

FIG. 8 is a dot pattern graph showing an example of a relationship between a modulation factor and a distortion factor in a UV line voltage during the minimum distortion operation in FIGS. 5 and 6;

FIG. 9 is a graph showing the relationship between the time variables d and q and the modulation factor during the minimum distortion operation when n = 3 in FIG. 8;

10 linearly approximates the relationship between the modulation factor and the distortion factor during the minimum distortion operation and the relationship between d and q and the modulation factor, and obtains the modulation ratio and the distortion factor of the UV line voltage obtained from the data table of FIG. It is a graph which shows a relationship.

[Explanation of symbols]

 1, 2 DC power input terminal 3 Neutral terminal 4, 5 Capacitor 6-17 GTO element 18-29 Anti-parallel diode 30-35 Clamp diode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-140359 (JP, A) JP-A-5-211775 (JP, A) JP-A-64-50766 (JP, A) JP-A-9-99 294375 (JP, A) JP-A-10-4696 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02M 7/48 H02M 7/515

Claims (2)

(57) [Claims] 1. A control circuit (microprocessor) for performing a switching operation of a GTO element constituting a series-multiplexed three-level inverter circuit in which an output voltage is controlled by pulse width modulation control includes one or a plurality of data tables. A UVW configured to perform a switching operation of the GTO element based on a gate pulse signal generated based on data read from the data table .
In the semiconductor power conversion device used for three-phase voltage, the on / off operation for one control cycle of the GTO element of each of the UVW phases is performed.
As the waveform data table switching pattern indicating a full state, the minimum switch of the UVW phases each of the GTO element
While maintaining the symmetry under the condition of odd number times (n ≧ 1)
Multiple waveforms to suppress neutral point potential fluctuations affected by load
As well as a data table, the minimum distortion at the time of the modulation rate and to time data table the relationship variable for that state output time, reads the variables relating to the state output time at a modulation rate from the time data table, the double
From the number of waveform data tables,
Switching pattern waveform data that reduces distortion
Wherein the gate pulse signal is generated based on data obtained by selecting a table and setting the variable value in the table . 2. A control circuit (microprocessor) for performing a switching operation of a GTO element constituting a series-multiplexed three-level inverter circuit whose output voltage is controlled by pulse width modulation control, wherein one or a plurality of data tables are incorporated. A UVW configured to perform a switching operation of the GTO element based on a gate pulse signal generated based on data read from the data table .
In the semiconductor power conversion device used for three-phase voltage, the on / off operation for one control cycle of the GTO element of each of the UVW phases is performed.
As the waveform data table switching pattern indicating a full state, the minimum switch of the UVW phases each of the GTO element
While maintaining the symmetry under the condition of odd number times (n ≧ 1)
Multiple waveforms to suppress neutral point potential fluctuations affected by load
In addition to creating a data table , the relationship between the time variable and the modulation factor at the time of minimum distortion is obtained as a linear approximation, and the approximation
A semiconductor power conversion device, wherein a time corresponding to a certain modulation factor is calculated, and the gate pulse signal is generated based on data obtained by substituting the time into the waveform data table.