JP3247724B2 - Bit field operation processing device and microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit for a bit field operation operation and an operation method thereof, and more particularly to a technique effective when applied to an integer operation unit of a processor.

[0002]

2. Description of the Related Art As a bit field operation operation, for example, there is a process for extracting an arbitrary region of data or replacing an arbitrary region of data. For example, there is an Extract instruction as an instruction to extract an arbitrary area of data. In response to this extract instruction, basically, processing as shown in FIG. 16 is performed. That is, (i) a data shift process for shifting the region to be extracted to the right end of the data, (ii) a mask data generation process for generating mask data in which a bit corresponding to each bit of the region to be extracted is set to “1”, (Iii) From the shifted data, only an area having a bit value of 1 in the mask data is extracted, and an extension process of filling the remaining area with 0 or a sign bit is performed. More specifically, the h-th bit of the input data is shifted right-justified, and sign extension or sign 0 is extended to the area other than the area specified by the area width LEN by sign bit S or bit 0. , The output data obtained by extracting the required area LEN from the input data. The area to be sign-extended or 0-extended at this time is specified by mask data. As an instruction to instruct the latter replacement processing, for example, there is a Deposit instruction. According to this instruction, basically, processing as shown in FIG. 17 is performed. That is, (i) a data shift process for shifting the area to be replaced to the left position to be replaced, and (ii) mask data generation for generating mask data in which a bit corresponding to each bit of the area to be replaced is set to “1”. Processing and (iii) mask execution processing for extracting only an area having a bit value of 1 in mask data from shifted data and writing the data read from a register or the like or data in which each bit is padded with 0s Is what you do. For example, the right end of the input data is shifted to the h-th bit, and a part of the data of the register or the data of all the bits “0” is replaced in an area having a width LEN from the h-th bit of the shifted data.
This is for obtaining output data. At this time, the area to be replaced is specified by the mask data. In this specification,
As the data, data having a width of 32 bits will be mainly described. The 32-bit data is not particularly limited, but the right end is defined as the least significant bit (LSB), the left end is defined as the most significant bit (MSB), the most significant bit is defined as the 0th bit, and the least significant bit is defined as the 31st bit. I do.

As a mask data generation circuit that can be used for generating both of the above mask data, a circuit as shown in FIG. 18 can be considered. This circuit includes a subtractor SUB, two mask bit generation logic circuits MLOG1 and MLOG2, and an AND circuit AND. The subtractor SUB generates the leftmost bit position of the region to be extracted or replaced from the data LEND indicating the region width LEN and the information hD indicating the lower bit position h of the region width. Mask bit generation logic circuit ML
OG1 generates data in which 1 is packed from the left end of the area to the least significant bit, and generates a mask bit generation logic circuit MLO.
G2 generates data in which 1 is packed from the right end of the area to the most significant bit. The logical product circuit AND obtains the logical product of these data to generate mask data used for mask execution and sign extension. FIG. 18 shows an example of a procedure for generating mask data for a deposit instruction. The mask data for the extract instruction is generated by setting the h-th bit to the 31st bit.

[0004]

In the processing of graphic data in which bits or areas of data correspond to pixels, for example, in graphic processing of moving images, the contents of one area of data are replaced with the required data of another data. And may be copied to the area. By applying the extract instruction and the deposit instruction to such processing, the number of instruction execution cycles can be significantly reduced. In the case where a bit-field manipulation operation device for executing these instructions is employed as dedicated hardware, a barrel shifter for shifting an arbitrary number of bits of data, a mask for barrel-shifted data, A circuit for sign-extending or masking based on data is required. The inventor of the present invention has proposed such a bit-field manipulation operation device as RISC
We considered to build it into a processor of the form. According to this, the area occupied by the mask data generation circuit shown in FIG.
% To increase the chip area.

Further, when the region width LEN extends to the left beyond the 0th bit of the input data in the above-mentioned extract instruction, the 0th bit is treated as a sign bit in the sign extension of the output data. If the area LEN is shifted to be right-justified by the shift processing, the 0th bit of the input data cannot be specified at the time of sign extension based on the mask data. Therefore, it has been considered to generate sign extension data in which the 0th bit of the input data is allocated to all bits in advance, and supply the extension data and the input data to the barrel shifter to perform barrel shift processing. However, if the barrel shift processing is performed after generating the sign extension data in which the 0th bit is allocated to all bits, the inventor has found that the execution speed of the extract instruction is delayed due to the dependent processing. Was.

Further, in order to specify a code bit to be extended in the sign extension circuit based on the mask data, it is necessary to find a position of a boundary bit at which a logical value of the mask data changes. For this reason, if logic that decodes input data to a complementary level is employed, a large number of logic circuits such as inverters for converting the input to the complementary level are required, and this also causes an increase in chip area. Revealed.

An object of the present invention is to provide an arithmetic unit which can reduce an area occupied in a chip by an arithmetic unit for extracting an arbitrary region of data or replacing an arbitrary region of data.

Another object of the present invention is to speed up a bit field operation operation for extracting an arbitrary area of data or replacing an arbitrary area of data.

It is still another object of the present invention to provide a decoder which contributes to a reduction in chip occupation area.

Still another object of the present invention is to increase the speed or / and
Another object of the present invention is to provide a barrel shifter circuit that can be downsized.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, in an arithmetic unit that performs a bit field operation such as extraction of an arbitrary region of data or replacement of an arbitrary region of data, the shift amount is controlled to be the same as that of the first barrel shifter that shifts input data by an arbitrary bit. A two-barrel shifter is employed in the mask data generation circuit. The mask data generation circuit has a mask bit generation circuit that generates second mask data based on information for specifying an area width in a bit string, and the second barrel shifter receives an output of the mask bit generation circuit and generates a second mask data. One mask data is generated. The first mask data is the first mask data.
The output of the barrel shifter and other data are used as a selection signal of selection means for selecting and outputting one of them for each bit, and the second mask data is a sign extension for data output from the first barrel shifter. Alternatively, it is used as extension area designation information for an extension circuit that performs extension with a predetermined logical value.

In order to suppress an increase in chip area caused by providing the first barrel shifter and the second barrel shifter, a transistor forming area for one row in each of the first barrel shifter and the second barrel shifter is temporarily stored in the memory. A 1-bit storage cell of storage means such as a register file to be held coexists in a region having the same width as the width occupied on a chip, and a common shift amount control line is used in both barrel shifters.

In the extension circuit, in order to suppress an increase in chip area caused by providing a specific circuit for specifying the position of a code bit to be sign-extended based on the second mask data, A logic gate circuit for comparing two adjacent logical values of two mask data with each other and outputting a boundary bit whose logical value is changed in the bit string of the second mask data as a logical value different from the other bits Is used. This logic gate circuit can be constituted by a plurality of exclusive OR circuits. Such a logic gate circuit can be used as another decode logic circuit, and converts n-bit data into 2 n
By processing the output of the means for expanding to multiplied bit data by the logic gate circuit, decoding logic for n-bit data can be configured.

In the process of extracting an arbitrary region of data by an extract instruction or the like, in order to improve the speed of sign extension processing on a portion other than the region to be extracted,
There is provided a sign extension circuit which receives the input data of the first barrel shifter, sign-extends all the bits based on a predetermined bit of the data, for example, a 0-th bit, and outputs this as the other data of the selecting means.

When a bit field operation for extracting and outputting an arbitrary area of input data is performed by using an arithmetic unit employing such a sign extension circuit, a process of shifting the input data by the first barrel shifter is performed. Parallelizing the process of sign-extending all the bits of the input data by the sign extension circuit, shortening a series of processing times required for both processes, and inputting both process results to the selection means, One mask data is selected to generate data including an area from which input data is to be extracted and the 0th bit.

The arithmetic unit can perform a process of replacing an arbitrary area of the another data with a predetermined area of the input data. The processing includes, using the first barrel shifter, performing a predetermined bit shift to a position where a replacement area of input data is to be replaced, and first mask data for specifying a replacement area in the shifted data. The process includes a process of generating by the second barrel shifter and a process of selecting output data of the first barrel shifter and another data based on the first mask data.

[0019]

According to the above-mentioned means, in the bit-field operation / operation device, barrel shifters are employed for shifting input data and for generating mask data, respectively.
The shift amounts of both barrel shifters are made equal to each other.
As a result, bit field operations such as extraction of an arbitrary area of data and replacement of an arbitrary area of data are relatively simplified, and the processing described below is speeded up and enhanced in function.

By laying out the two sets of barrel shifters so as to be folded in accordance with the width of the storage cell of one bit of the register file, the chip occupation area of the arithmetic unit for the bit field operation operation is reduced.

The time parallelization of the sign extension and the data shift for the input data is intended to increase the operation speed for extracting an arbitrary area of the data.

By obtaining a decoding result using the mask bits, a circuit for converting input data into a signal of a complementary level is not required, and the circuit scale or chip occupation area is reduced. Here, a more specific mode of the bit field operation calculation device will be described. The bit field operation arithmetic unit (SMU) includes a data supply unit (EXT2, SEL1) for supplying predetermined data (base data, etc.) including a plurality of mask bits, and a shift control signal (shift0, shift0, ..) And a first means for coupling the control means for shifting the bits of the input data according to the shift amount and outputting the shifted input data including a plurality of input bits. A barrel shifter (BSFT1),
The control means is coupled to the control means, shifts bits of the control data in accordance with the shift amount, outputs mask data (MASKD1) including a plurality of control bits, and each of the plurality of control bits corresponds to the plurality of input bits. A second barrel shifter (BSF), corresponding to each, indicating whether the corresponding input bit is a bit to be masked or not.
T2) and are coupled to the first barrel shifter (BSFT1), the second barrel shifter (BSFT2), and the data supply means (EXT2, SEL1), and are masked by the mask data from the second barrel shifter (BSFT2). Supply means (MASKE) for selectively supplying the mask bit instead of the input bit indicated as a bit to be input, and a plurality of input data supply circuits (SEL2, SEL) each having an output terminal for outputting an input signal
3) and a plurality of control data supply circuits each having an output terminal for outputting a control signal, and are formed on a semiconductor substrate. Then, the first barrel shifter (BS)
FT1) includes a plurality of output terminals for outputting the shifted input data, a plurality of input terminals respectively coupled to the output terminals of the plurality of input data supply circuits, and a first matrix. One matrix includes a plurality of first insulated gate field effect transistors arranged in a matrix, and each of a plurality of columns in the first matrix includes:
At least one of the plurality of output terminals, at least one of the plurality of input terminals, and at least one first insulation coupled between the at least one output terminal and the at least one input terminal. Each of the plurality of rows in the first matrix includes a gate type field effect transistor, and each of the plurality of rows is coupled to a shift control line in common, and the shift control signal is transmitted via the coupled shift control line. Includes a plurality of first insulated gate field effect transistors to which one of them is supplied. The second barrel shifter includes a plurality of output terminals for outputting the mask data, a plurality of input terminals coupled to each of the output terminals of the plurality of control data supply circuits, and a second matrix. The matrix includes a plurality of second insulated gate field effect transistors arranged in a matrix, and each of a plurality of columns in the second matrix includes at least one of the plurality of output terminals and the plurality of output terminals. And at least one second insulated gate field effect transistor coupled between the at least one output terminal and the at least one input terminal; and In each of the plurality of rows, the respective gates are commonly coupled to the shift control line, and the shift control signal is transmitted through the coupled shift control line. It includes a plurality of second insulated gate field effect transistor in which one is supplied of the. The rows of the first insulated gate field effect transistors of the first barrel shifter and the rows of the second insulated gate field effect transistors of the second barrel shifter are alternately arranged in parallel. A microprocessor (M
CU) is formed on the semiconductor substrate, and performs a bit field operation in response to a bit field command. The microprocessor comprises a control means (IU) for forming a control signal in response to an instruction, and an internal bus (SB1, SB2, SB1).
LB, WB), a plurality of registers (REGF) coupled to the internal bus, and a bit field operation / operation device (bit field operation / operation device) coupled to the internal bus and the control means for executing a bit field operation in accordance with the bit field instruction ( SUM). A data supply means coupled to the internal bus for supplying predetermined data having a plurality of mask bits in accordance with the bit field instruction (EXT2, SEL1);
And a shift amount indicating means (SDEC) for providing a decode signal indicating a shift amount to be shifted in response to the bit field instruction, and a plurality of selection circuits each having an output terminal. Selecting means (SEL2, SEL3) for selectively inputting data from the internal bus in response to a predetermined signal among the control signals; A first barrel shifter (BSFT1) for shifting output data from the selection means according to the shift amount designated by the designation means and outputting shifted data including a plurality of input bits, and mask control according to the bit field instruction Mask control data forming means (MBG) for forming data, the mask control data forming means and the shift Coupled to the instruction unit, in accordance with the shift amount designated by the shift amount indicating means to shift the mask control data, the second to output the shifted mask control data is having a plurality of mask control bits
Of the input bits coupled to the first barrel shifter, the second barrel shifter, and the data supply means and indicated as bits to be masked by a mask control bit from the second barrel shifter. Instead, a supply means (MASKE) for supplying the mask bit is included. Each of the plurality of mask control bits corresponds to each of the plurality of input bits, and indicates whether the corresponding input bit is a bit to be masked. The mask control data forming means includes a plurality of control data supply circuits each having an output terminal. The first barrel shifter includes a plurality of output terminals for outputting the shifted input data, a plurality of input terminals coupled to output terminals of the plurality of selection circuits, and a first matrix. Includes a plurality of first insulated gate field effect transistors arranged in a matrix, and each row of the first matrix has at least one of the output terminals and at least one of the input terminals. And at least one first insulated gate field effect transistor coupled between the at least one output terminal and the at least one input terminal, wherein each column of the first matrix has its gate And a plurality of first insulated gate field effect transistors to which one of the decode signals is commonly supplied via the shift control wiring. Including the register. The second
A barrel shifter including a plurality of output terminals for outputting the shifted mask control data, a plurality of input terminals coupled to output terminals of the plurality of control data supply circuits, and a second matrix; Comprises a plurality of second insulated gate field effect transistors arranged in a matrix, wherein each row of the second matrix has at least one of the output terminals and at least one of the plurality of input terminals. And at least one second insulated gate field effect transistor coupled between the at least one output terminal and the at least one input terminal, wherein each column of the second matrix has its gate And a plurality of second insulated gate electrodes to which the one decode signal is supplied via the shift control wiring. Including the effect transistor.

[0023]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of a bit-field manipulation operation device according to the present invention;

(1) Processor FIG. 1 shows an embodiment of a microprocessor to which the present invention is applied. Processor MCU shown in FIG.
Is not particularly limited, but the instruction cache memory CC,
Data cache memory DC, integer operation unit EU,
Floating point arithmetic unit FU, random logic unit IU for instruction control, random logic unit MU for memory control, random logic unit SU for secondary cache control, tag cache memory CA for instructions, tag cache memory DA for data, address conversion for instructions It includes a buffer CT, a data address conversion buffer DT, an input / output unit I / O, and the like. These are formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique. Although not particularly limited, this processor MCU is a RISC (Reduced Ins)
(StructureSet Computer) type architecture. This RISC architecture is known, and aims to speed up processing by simplifying the instruction set. For example, it is also possible to perform instruction decoding only with hard-wired logic such as random logic without using control storage. .

FIG. 2 shows an example of the integer operation unit EU. The integer operation unit EU is controlled according to the result of decoding read from the instruction cache memory CC and decoded by the instruction control random logic unit IU. And one of them is operated based on a control signal output from the instruction control random logic unit IU. The operation is performed on data held in the register file REGF included in the integer operation unit EU. The data read from the register file REGF is stored in the integer operation unit EU.
Are transmitted to the arithmetic and logic unit ALU and the bit field operation unit SMU through the source buses SB1 and SB2 in the internal memory. The arithmetic logic unit ALU or the bit field operation unit SMU that has received the data executes a predetermined operation, and writes the operation result back to the register file REGF via the write bus WB. Integer arithmetic unit EU
And the other units described above are transferred via the load bus LB. The arithmetic and logic unit ALU performs arithmetic / logical operations between registers and LOAD / S
The calculation of the address of the memory access at the time of executing the TORE instruction and the address of the branch destination by the branch instruction are performed. The bit-field manipulation arithmetic unit SMU performs, besides a normal shift instruction, extraction of an arbitrary area of data which is not provided in another RISC processor, replacement of an arbitrary area of data, and the like. Such an arithmetic device.

The bit field manipulation arithmetic unit SMU
The instructions to be executed are roughly classified into a shift instruction, an extract instruction [Extract instruction (extraction of an arbitrary area of data), and a deposit instruction [Deposit instruction (replacement of an arbitrary area of data)]. The basic operation of the extract instruction is shown in Fig. 16, and the basic operation of the deposit instruction is shown in Fig. 17. These instructions are the other RIs.
It is for dedicated operation not found in the SC processor. Although a similar function exists in the CISC processor, its operation requires more than ten cycles by microprogram control (control using the control storage). The extract instruction shifts an arbitrary area of data to the right end,
The remaining area is filled with 0 or sign bits. The arbitrary area of the data to be extracted is specified by the area width LEN and the rightmost bit position h of the area. The deposit instruction is the reverse operation of the extract instruction,
This is an instruction to write an area specified by the width LEN at the right end of the data to an arbitrary area of another data. At this time, the underlying data to be written is not particularly limited, but the data supplied from the register file REGF or all bits are logical 0 data.

FIGS. 19A and 19B show the format of the extract instruction. Whether the remaining area is filled with "0" or a code bit is determined by the operation code. Therefore, there are two types of instruction. For example,
The extract instruction shown in FIG.
An operation instruction OP-EX1 for instructing the remaining area to be filled with "0" is provided, and the extract instruction shown in FIG. 19B indicates that the remaining area is to be packed with the sign bit. Operation code OP
EX2. In the present embodiment, the bit position h is held in the data & or shift amount control register (not shown, but included in the instruction control random logic unit IU) included in the extract instruction. Determined by the data. Data held in control registers (coded data)
Or use the data (coded data) held in the field & in the instruction
It is determined by the value of the control field S in the extract instruction. For example, by setting "1" in the control field S, the value of the field & in the instruction is used as data representing the bit position h, and by setting "0" in the control field S, the shift amount is set. Is used as data representing the bit position h. The field LEND in the extract instruction is
This is a field for holding data (coded data) representing the area width LEN.

FIGS. 19C and 19D show the format of the deposit instruction. In the case of this deposit instruction, two kinds of instructions are prepared.
For example, the deposit instruction shown in FIG. 19C has an operation code OP-DE1 indicating that data held in a register in the register file REGF is used as background data to be written. On the other hand, the deposit instruction shown in FIG. 19D has an operation code OP-DE2 indicating that "0" is used as the underlying data. In the case of the deposit instruction shown in FIG. 19C, it is necessary to specify the register holding the base data. Therefore, the deposit instruction in FIG. 19C has a field for holding data REG-No indicating the number of the register. The fields LEND, S, & shown in (C) and (D) of FIG. 19 are the same as those of the extract instruction.

The operation of replacing an arbitrary area of data with an arbitrary area of another data is frequently used in graphic processing or the like. When the operation does not use the bit-field manipulation arithmetic unit SMU according to the present embodiment, That is, when a RISC processor different from that of the present embodiment is used, it is necessary to execute the following six instructions shown in FIG. Shift instruction: Shift until the area to be replaced reaches the position to be replaced (desired position). LOAD instruction: Reads mask data in which a bit corresponding to a bit of an area to be replaced is set to "1". AND instruction: ANDs the shifted data and mask data. Bit inversion command; creates bit inversion data of mask data. AND instruction: ANDs the bit-inverted data and the base data. OR instruction Takes the logical sum of the data created in; and the data created in.

On the other hand, in the bit field manipulation arithmetic unit SMU of this embodiment, the same operation is completed in two cycles of the extract instruction and the deposit instruction, the processing time is shortened by three times or more, and high-speed graphic processing is performed. Etc. become possible.

FIG. 4 shows a microprocessor M of this embodiment.
An example of a graphic processing system using a CU is shown. A display CRT, a keyboard KBD, a main memory MMRY, and the like are connected to the system bus SB, and are connected to the peripheral bus PB by a memory interface MITF such as a shared memory having dual ports. The peripheral bus PB has a microprocessor MC.
U is connected to each microprocessor MCU.
The next cache memory CMRY is connected.

(2) Bit Field Operation and Operation Unit FIG. 5 shows an embodiment of the bit field operation and operation unit SMU.

The bit field operation arithmetic unit SMU includes:
First barrel shifter BSF for shifting input data
T1, a mask data generation circuit MASKG, a mask execution circuit MASKE, an extension circuit EXT1, and a zeroth bit sign extension circuit EXT2. 1st barrel shifter BS
The FT1 performs an arbitrary bit shift of data, and inputs data of one word (each word is assumed to be 32 bits in this embodiment) from the selectors SEL2 and SEL3, and simultaneously shifts a total of two words to one bit. Outputs word data. As can be seen from FIGS. 6 and 8, each bit position of the output word corresponds to each bit position of the upper word. This is the barrel shifter BS
The same applies to FT2. The shift amount is the decoder SD
Determined by the output of the EC. The first barrel shifter BSFT1 is used not only for the extract command and the deposit command but also for a normal shift command. Other RI
Many SC processors are provided with only such a barrel shifter as a bit-field operation arithmetic unit.

The mask execution circuit MASKE is a circuit for executing a mask based on the first mask data MASKD1 generated by the mask data generation circuit MASKG. This circuit functions as a two-input selector in which one word of data is input to each input. According to the value of each bit of the first mask data MASKD1, the data output from the first barrel shifter BSFT1 and the selector SE
Data supplied from the L1 side is selected for each bit, and data of a total of one word is output.

The extension circuit EXT1 expands the data output from the mask execution circuit MASKE to 0 (logic 0) based on the second mask data MASKD2 generated by the mask data generation circuit MASKG when executing the extract instruction. Extension) or sign extension. The extension circuit EX
T1 is a mask execution circuit M when the deposit instruction is executed.
The data output from ASKE is output as it is.

[0036] AT: 1 = Select the output of the mask execution circuit MASKE. AT: 2 = Select from the output of the mask execution circuit MASKE according to the second mask data MASKD2 and the output of the selector SEL6. AT: 3 = Data shifted according to the first mask data MASKD1. Select from output of selector SEL1 AT: 4 = Select shifted data

The 0th bit sign extension circuit EXT2 is
All the bits of the input data are sign-extended with the value of the 0th bit of the input data and output to the selector SEL1.
The configuration of the 0th bit sign extension circuit EXT2 can be easily realized by using a part of the circuit of FIG. 20 described later.

The selectors SEL1 to SEL shown in FIG.
Each of the ELs 5 is controlled by a control signal formed by the command control random logic unit IU. Instruction control random logic unit IU
Although not particularly limited, the control signal is formed mainly based on an operation code of instructions (deposit instruction, extract instruction, shift instruction) supplied thereto.

The table includes an instruction and a selector SE.
The relationship with each state of L1 to SEL5 is shown. The table also shows control signals C00, C01, and C02 formed by the command. tabl
Column A in e shows a case where it is instructed to use data "0" as background data by a deposit instruction, and column B shows a case where it is instructed to use data held in a register as background data by a deposit instruction. Is shown. Column C shows the case where it is instructed to pack "0" in the remaining area by an extract instruction, and column D shows the case where it is instructed to pack code data in the remaining area by an extract instruction. ing. "-" in the table indicates that any state is acceptable. When the instruction is supplied, the selector SEL
The states of the signals 1 to SEL5 and the control signals C00, C01, and C02 will be described below.

When the deposit instruction is supplied to the unit IU, the selector SEL2 selects and outputs the data on the bus SB1. At this time, the selector SEL4
Selects the output of the MBG, and the selector SEL5 selects and outputs the data "0". The selector SEL1 selects the data “0” when the use of the data “0” is instructed as the base data (column A), and when the use of the data held in the register is instructed as the base data, The data on the bus SB2 is selected (column B) and output. In the case of a deposit instruction, "1" and "0" are output as the control signals C00 and C02. When the use of the data held in the register is instructed as the base data, the register number REG-N in the deposit instruction is used.
The register designated by o is selected, and the held data is output to the bus SB2. for that reason,
When the data of the register is designated as the base data, the selector SEL1 outputs the register number REG-N
The data held in the register designated by o is output.

When the extract instruction is supplied to the unit IU, the selector SEL2 selects data "0", the selector SEL3 selects data on the bus SB2, and the selector SEL4 selects data "0". The selector SEL5 selects and outputs data "1". When it is instructed to pack “0” in the remaining area, the selector SEL1 selects data “0”,
When it is instructed to pack codes in the remaining area, the selector SEL1 selects and outputs the output of the extension circuit EXT2. Further, the control signals C00 and C02 are
Both become "0". As will be described later with reference to FIG. 20, the control signal C01 is a signal for selecting data “0” when “0” is padded.
This signal is used to select BIT.

When the shift instruction is supplied to the unit IU, the selector SEL2 selects the bus SB1, the selector SEL4 selects the data "0", and the selector SEL5 selects and outputs the data "1". Selector SEL3
Is to perform a shift operation on 64-bit data.
The data on the data bus SB2 is selected, and in the case of a shift operation on 32-bit data, data "0" is selected and output. At this time, the control signals C00 and C02 are both "1".

In the mask bit generation circuit MBG, the field LEN representing the area width LEN included in the instruction is supplied from the instruction control random logic unit IU.
The value of D is supplied to the decoder SDEC, and the value of the field & representing the shift amount h included in the instruction control random logic unit IU instruction or the value held in the shift amount control register is also supplied to the decoder SDEC. Supplied.

The control signal C02 is supplied to the OR gate ORG1.
Is supplied to one input terminal, and the other input terminal is supplied with mask data MASKD1.

The control signals C00 and C01 are supplied to the extension circuit E
It is supplied to XT1. One embodiment of the extension circuit EXT1 is shown in FIG.

Extension circuit EXT1 shown in FIG.
Has a decoder BDEC, an OR gate ORG2, a tristate buffer TB, a code line SIN-BIT, and selectors SEL6 and SEL7.

The mask data MASKD2 is supplied to the decoder BDEC, and a boundary bit at which a logical value changes in the mask data MASKD2 is determined. I do. About such a decoder BDEC,
An example is shown in FIG. 15 and will be described later. The output of the mask execution circuit MASKE is supplied to a tri-state buffer TB. These tristate buffers T
The control of B is performed by the output of the decoder BDEC,
The output of each tri-state buffer TB is shared,
It is supplied to the code line SIN-BIT. Thereby, the tri-state buffer TB transmits the bit in the output data of the mask execution circuit MASKE corresponding to the boundary bit where the logical value changes in the mask data MASKD2 to the common code line SIN-BIT. Selector SEL6
, According to the control signal C01, the code line SIN-B
The value of IT or data “0” is selected and output. The OR gate ORG2 receives the control signal C00 and the mask data MASKD2 as inputs, and
A signal for controlling EL7 is formed. The above selector SEL
Reference numeral 7 selects and outputs the output of the selector SEL6 or the output of the mask execution circuit MASKE.

When the control signal C00 becomes "1", the OR gate ORG2 sets the mask data MASKD2
Outputs "1" regardless of the value of. As a result, the selector SEL7 selects and outputs the output of the mask execution circuit MASKE. On the other hand, when the control signal C00 is "0", the bit in the output of the mask execution circuit MASKE corresponding to the bit set to "1" in the mask data MASKD2 is output from the selector SEL7, "0" in MASKD2
The selector SEL7 operates so that the output of the selector SEL6 is output to the bit in the output data DD corresponding to the bit of.

When the control signal C02 is "1", the data "1" is output from the OR gate ORG1.
Is output to the mask execution circuit MASKE, and when the control signal C02 is "0", the mask data MA
The data according to the data of SKD1 is OR gate OR
G1 is supplied to the mask execution circuit MASKE.

The control signal C01 is, for example, "1" in the case of sign extension. In response to this, the selector SEL6
Selects data on the code line SIN-BIT.
As a result, a common value is output from all the selectors SEL6. On the other hand, when data "0" is packed in the remaining area, the control signal C01 becomes "0". As a result, the selector SEL6 outputs data “0”.
Select and output.

The extension circuit EXT1, the 0-th bit sign extension circuit EXT2, the mask data generation circuit MASKG, and the mask execution circuit MASKE are an extract instruction and a deposit instruction which are processes specific to the bit field manipulation arithmetic unit SMU of this embodiment. , And is not present in other RISC processors. It is necessary to reduce the area of these circuits and reduce the operation delay in order to realize performance superior to other RISC processors, and in the present embodiment, they are realized. Will be sequentially described.

(3) Mask Data Generation Circuit Employing Barrel Shifter As shown in FIG. 6, the mask data generation circuit MASKG includes a second barrel shifter BSFT2, a mask bit generation circuit MBG, and selectors SEL4 and SEL5. The mask bit generation circuit MBG includes, but is not limited to, 5-bit information LEND included in the instruction.
Then, the second mask data MASKD2 indicating the bit width (region width) LEN of logic 1 from the right end of the 32-bit bit string is generated based on the 5-bit value. The logic for generating the second mask data MASKD2 can be easily configured by hard-wired logic. The second barrel shifter BSFT2 performs an arbitrary bit shift of data in the same manner as the first barrel shifter BSFT1, inputs one-word data, shifts a total of two words at the same time, and shifts a total of two words simultaneously. One-word data having a bit position corresponding to the bit position on a one-to-one basis is output. The shift amount is determined by the decoder SD
Determined by the output of the EC. 2nd barrel shifter BS
The second mask data MASKD2 or data in which all bits are set to logic 0 are supplied to the upper input of FT2 via the selector SEL4. Second barrel shifter BSFT2
Is input to the lower side input through the selector SEL5.
Data of which all bits are logic 0 or data whose 32 bits are logic 1 are supplied. Second barrel shifter BS
The output shifted by FT2 is used as the first mask data MASKD1.

As shown in FIG. 6, the mask data generation circuit MASKG converts the second mask data MASKD2 in which the area given by the width LEN is set to 1 from the right end with the operation data supplied to the first barrel shifter BSFT1. Shift left by the second barrel shifter BSFT2 by the same amount (31
-H bit shift), it is possible to generate the first mask data MASKD1 used for a deposit instruction or the like. The second mask data MASKD2 is used as mask data for the extract instruction. Therefore, this mask data generation circuit MAS
The KG can generate mask data for a deposit instruction and mask data for an extract instruction in the same manner as in FIG. 18 without using a subtractor. Further, when executing the extract instruction, the second barrel shifter BSFT2 not used for generating the second mask data to be supplied to the extension circuit EXT1 is replaced with the first barrel shifter BSFT1.
At the same time, it becomes available for another processing of the extract instruction.

(4) Acceleration of Sign Extension Shift in Extract Instruction There are two cases of sign extension performed by the extension circuit EXT1 in the extract instruction as shown in FIG. 7 (i) and (ii). As shown in (i), the region width LEN
Does not exceed the 0th bit of the input data, the sign extension in the output data is performed according to the sign of the leftmost bit of the area width LEN. On the other hand, when the region width LEN extends to the left beyond the 0th bit of the input data as shown in (ii), the 0th bit of the input data is treated as a sign bit in the sign extension of the output data.

As shown in FIG. 8, when executing the extract instruction, the first barrel shifter BSFT1
Each of them receives 32-bit input data and arbitrary value data (for example, data), and performs barrel shift (31-h bit shift) such that the h-th bit of the input data is at the right end. In parallel with this, the 0-th bit sign extension circuit EXT2
Expands the value of the 0th bit of the input data to all bits. Further, the second barrel shifter BSFT2 receives one word data of all bits “0” and one word data of all bits “1” and performs a shift operation with the same shift amount as the first barrel shifter BSFT1. Generate mask data MASKD1. Mask execution circuit MASK
E receives the output of the first barrel shifter BSFT1 and the output of the zeroth bit sign extension circuit EXT2. The mask execution circuit MASKE selects and outputs the output of the first barrel shifter BSFT1 corresponding to the bit position of the bit having the logical value 1 in the first mask data MASKD1. On the other hand, the first mask data MAS
For a bit having a logical value of 0 in KD1, the output of the 0th bit sign extension circuit EXT2 corresponding to the bit position is selected and output. As a result, the data output from the mask execution circuit MASKE holds the values from the 0th bit to the hth bit of the input data on the lower side (right side), and the remaining bits hold the value of the 0th bit of the input data. Data. This mask execution circuit M
The output data of ASKE is supplied to the extension circuit EXT1, as shown in FIG. This extension circuit EXT1 includes
The second mask data MASKD2 is also supplied. The extension circuit EXT1 sign-extends the left bit of the area width LEN specified by the second mask data MASKD2 as a sign bit. In the case corresponding to (i) of FIG. 7, the bit position to be sign-extended is not the 0th bit of the input data, but the sign bit S existing within the width h indicated by oblique lines in the drawing. According to the sign of the sign bit S specified by the two mask data MASKD2, that is, the logical value, each bit on the left side (upper side) of the sign bit S is sign-extended according to the logical value of the sign bit S. As can be seen from FIG. 20, the bit corresponding to the boundary bit is the code line SIN-
The BIT is transmitted to the BIT,
-BIT data is transmitted. In the case corresponding to (ii) of FIG. 7, since the 0th bit of the input data is a sign extension bit, the output data from the extension circuit EXT1 is the same as the output of the mask execution circuit MASKE. In this case, since LEN exceeds the 0th bit,
By the selector SEL7, the mask execution circuit MASKE
Output is selected.

As described above, the first barrel shifter BSFT1
In parallel with the barrel shift process of the input data by the 0th bit sign extension circuit EX
At T2, a process of sign-extending all bits to the value of the 0th bit is performed, and both processing results are selected by the mask execution circuit MASKE, and the same process as the arithmetic shift can be performed.
That is, the second barrel shifter BSFT for generating mask data
In the upper input of 2, all bits have data of logical value 0, and in the lower input, data of all bits have logical value 1 and are shifted by the same amount as the shift amount of the input data by the first barrel shifter BSFT1. As a result, the first mask data MASKD1 is generated, and data obtained by previously sign-extending the 0th bit of the input data to all bits and the first barrel shifter B
If the mask processing with the SFT1 shift output data is executed by the first mask data MASKD1,
This is an operation equivalent to an arithmetic shift. Compared with the subordinate or serial processing of the 0th bit sign extension processing and the barrel shift processing on the input data shown in FIG. 10, the operation method of the present embodiment shown in FIG.
An arbitrary value may be supplied to the upper input of the first barrel shifter BSFT1, and there is no need to wait for the 0th bit sign extension processing on the input data. Therefore, according to this arithmetic shift operation, the execution speed of the extract instruction can be increased as compared with the process of generating the sign extension data by distributing the 0th bit of the input data to all bits in advance and then performing barrel shift. Can be.

(5) Reduction of Occupied Area of Barrel Shifter FIG. 11 shows first and second barrel shifters BSFT1, BSFT.
A circuit diagram of one embodiment of FT2 is shown. The transistor forming areas of one row of each of the first and second barrel shifters BSFT1 and BSFT2 coexist in an area having the same width as the width occupied by the one-bit storage cell of the register file REGF that temporarily holds operation information. In addition, a shift amount control line for transmitting a control signal for controlling the shift amount in both barrel shifters BSFT1 and BSFT2 is shared. In the figure, m1-in0,... Are the lower 32 input signal lines of the second barrel shifter BSFT2, m2-i.
n0,... are the upper 32 bits of the second barrel shifter BSFT2.
Are the 32 output signal lines of the second barrel shifter BSFT2, d1-in0,... Are the 32 lower input signal lines of the first barrel shifter BSFT1, d2-in0,. Is the first barrel shifter BSFT1
, Are the 32 output signal lines of the first barrel shifter BSFT1, and the upper 32 input signal lines, d-out0,.
ift0,... are control lines for instructing a shift amount commonly used by the first barrel shifter BSFT1 and the second barrel shifter BSFT2. The output signal line and the control line are arranged side by side in an intersecting arrangement, and a shift amount instruction signal is received from the control line by a selection terminal and controlled by a switch so that an input is conducted to a predetermined output signal line. The transistors TR are arranged in a matrix.

FIG. 11 is drawn in accordance with the layout on the actual chip. FIG. 3 also shows a part of the selector SEL3, a part of the selector SEL5, and the registers REGn-1 and REGn in the register file REGF.
EGn and REGn + 1 are shown, and these are also drawn according to the actual layout. The selector is configured by a plurality of unit selectors U-SEL, and the register is also configured by a plurality of storage cells U-REG. The memory cell and the unit selector are connected by a bus. As can be seen from FIG.
The storage cell U-REG and the unit selector U-SEL have substantially the same width.

The storage cells U-REG of the register file REGF are mainly composed of static flip-flops. For example, in the case of a CMOS circuit, at least six transistors including a transfer gate are required. The height at which these six transistors are arranged matches the height of the one-bit region shown in FIG. Assuming that both barrel shifters BSFT1 and BSFT2 are separated from each other and arranged in separate regions, the layouts shown in FIGS. 12 and 13 are considered. As can be seen from FIGS. 12 and 13, in this case, there are many useless areas that are not used at all.
As can be seen from FIG. 11, the barrel shifter BSFT1,
BSFT2 is supplied with data from the register file REGF via the selector and the buses SB1 and SB2.
At this time, in consideration of a layout method such as a standard cell, it is desirable in terms of layout to arrange transistors in a region defined as a rectangular region for a circuit block grasped for each function. In particular, the barrel shifters BSFT1 and BSFT2 are provided with data in parallel from the register file REGF and function closely. Therefore, if there is a signal propagation delay between bits of data supplied in parallel, it is not desirable in operation. Therefore, the register file REGF and the barrel shifters BSFT1 and BSF
It is advisable to prevent the complicated and unified bending of the signal wiring connecting T2 as much as possible. From this viewpoint, as shown in FIGS.
Even when the SFTs 2 are configured in separate areas, transistors and their input signal lines are arranged for each of the 1-bit areas so as to take a space that is considered useless at first glance. In this embodiment, both barrel shifters BSFT1 and BSFT2 coexist in the same area in order to effectively use the space. Thereby, two barrel shifters BSFT1, BSFT
Even if FT2 is adopted, a substantial increase in chip area due to it can be suppressed. As shown in FIG. 14, if the width dimensions of the barrel shifters BSFT1 and BSFT2 are reduced, the barrel shifter formation region can be relatively reduced by the vertical dimension X. Since a predetermined interval must be provided between the wirings, the dimension Y in the horizontal direction increases, and the chip occupation area of the integer arithmetic unit EU does not decrease as expected.

(6) Decode Logic for Extracting Code Bit Position In the extension circuit EXT1, the mask execution circuit MAS
The position of the sign bit for sign extension to the data output from KE is determined by logic gate circuit LG shown in FIG.
C (corresponding to the decoder BDEC in FIG. 20) detects it. The logic gate circuit LGC compares the logic values of the adjacent two bits of the second mask data MASKD2 output from the mask bit generation circuit MBG with the exclusive OR gate EOR, and compares the second mask data MASK with the second mask data MASK.
It has a logic to output a boundary bit whose logical value is changed in the bit string of D2 as a logical value different from other bits. Such a logic gate circuit LGC is provided with the second mask data MASK.
By passing each bit of D2 through the exclusive OR gate EOR of one stage, the position of the sign bit to be sign-extended can be cut out. Therefore, it is not necessary to newly provide another decoder for inputting and decoding the information LEN, and in this respect, the circuit scale of the extension circuit EXT1 is reduced. The decoding logic does not require a circuit for generating a complementary level from a signal to be decoded. In this respect, the wiring logic can be simplified and the number of circuit elements can be reduced as compared with a conventional decoding circuit. It contributes to layout area reduction.

The logic gate circuit LGC can be applied to other applications as a general decoder together with a circuit such as the mask bit generation circuit MBG. At this time, a circuit such as the mask bit generation circuit MBG converts the n-bit data into a bit string of 2 n and a bit of a constant logical value continuously arranged from the end of the bit string. It can be defined as a means for developing any data of 2 n powers different depending on the number, and in response to this, the logic gate circuit causes the data output from the developing means to be adjacent to each other. It is configured as a circuit that compares the logical values of the bits, and outputs a boundary bit whose logical value is changed in the bit string of the output data from the expanding means with a logical value different from the other bits.

According to the above embodiment, the following functions and effects can be obtained. (1) The barrel shifters BSFT1 and BSFT2 are used for shifting input data and generating mask data, respectively, and both barrel shifters BSFT1 and BSFT1 are used.
The shift amounts of FT2 are made equal to each other. This contributes to an increase in the function of the arithmetic unit SMU that supports bit field operations by a deposit instruction, an extract instruction, and the like, and to an increase in the speed of arithmetic processing. (2) One transistor row in each of the two sets of barrel shifters BSFT1 and BSFT2 is laid out so as to be folded in accordance with the width of one bit of memory cells in the register file REGF. This makes it possible to reduce the chip occupation area of the bit field manipulation arithmetic unit SMU. (3) The 0th bit sign extension for the input data and the barrel shift of the input data by the first barrel shifter BSFT1 can be processed in parallel in time. The result of the parallel processing is selected by the mask execution circuit MASKE based on the first mask data MASKD1 generated by the second barrel shifter BSFT2, and arithmetic shift is performed. Since the result of the arithmetic shift is sign-extended by the extension circuit EXT1, the operation speed for extracting an arbitrary region of data by an extract instruction can be increased. (4) A logic gate circuit LGC that inputs data such as the second mask data MASKD2 and outputs a decoded result
By adopting (BDEC), a decoder does not need a circuit for converting an input to a signal of a complementary level, and the circuit scale and chip occupation area of the extension circuit EXT1 and a general decoder can be reduced. it can. (5) By the above operation and effect, it is possible to obtain a high-performance RISC processor that suppresses an increase in the chip occupation area and increases the operation speed, and supports the deposit instruction and the extract instruction.

Next, another embodiment of the barrel shifter will be described. The barrel shifter described below can be used as the barrel shifters BSFT1 and BSFT2 in the above-described embodiment. Further, it can be used as a barrel shifter in a processor different from the above-described embodiment, for example, a coprocessor.

As shown in FIGS. 12 and 13, the conventional barrel shifter circuit can be configured by arranging a plurality of MOS transistors Q in a matrix as shown in FIG. For example, in a barrel shifter circuit that performs an arbitrary shift up to N = 2 ⁿ bits, N × N MOS transistors Q are arranged in a matrix, and
By the output of the decoder DEC for decoding the bit shift control data SF, all the MOS transistors Q in a predetermined column corresponding to the shift control data SF are turned on. This makes it possible to shift the input data for an arbitrary bit according to the shift control data SF.

As an example of a document describing a barrel shifter, there is JP-A-2-90318.

In the barrel shifter circuit shown in FIG. 30, the MOS transistors Q forming the barrel shifter circuit
, A decoder DEC for decoding the n-bit shift control data SF is required. The operation speed of the barrel shifter circuit is limited by the decoding time in the decoder DEC, that is, the time required from when the shift control data SF is supplied to the decoder DEC to when the decode output is determined. In addition, the inventor has found that the provision of such a decoder DEC prevents the reduction of the occupied area of the barrel shifter circuit in the LSI chip.

One of the above-mentioned objects is achieved by configuring the barrel shifter circuit as follows.

That is, when n is a positive integer, a barrel shifter is formed by combining n shift circuits capable of shifting data by 2 ⁱ (i = 0, 1, 2,..., N−1) bits. To form In order to enable shifting of an arbitrary number of bits up to 2 ⁿ bits for input data of two words in response to n-bit shift control data,
A first shift circuit group for shifting one word of input data to the upper or lower side of a word, and a second shift circuit for shifting another one word of input data in a direction opposite to the first shift circuit group. A barrel shift circuit is formed including the shift circuit group. In this case, each 2 ⁱ (i
= 0, 1, 2,..., N−1). The first shift circuit group and the second shift circuit group are formed by combining n shift circuits that enable data shift of bits. At this time, a shift output for one word can be obtained by combining the shift output of the first shift circuit group and the shift output of the second shift circuit group. Further, the shift control data input to the first shift circuit group is inverted,
In the case where the shift control data is input to the second shift circuit group, the shift control data may be appropriately combined with the shift output of the first shift circuit group and the shift output of the second shift circuit group. Regardless, a 1-bit shift circuit that shifts input data by 1 bit may be included in the second shift circuit group. The word may be 8, 16, or 32, or any other number of bits may be defined as one unit.

In a more specific mode, the n shift circuits can be formed to include a gate circuit for switching between a data through state and a data shift state in response to the shift control data.

According to the above configuration, each of the 2 ⁱ (i
= 0, 1, 2,..., N−1) -bit data can be shifted by 2 ^n- bit input data in response to n-bit shift control data. This eliminates the need for a decoder for decoding n-bit shift control data.

FIG. 28 shows a coprocessor to which a barrel shift circuit (barrel shifter) as one embodiment of the present invention is applied. Coprocessor 1 shown in FIG.
Although it is not particularly limited, it is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The coprocessor 1 is for complementing the operation capability of an external main processor (not shown) connected via the bus interface circuit 2 or reducing the operation capability load of the main processor. A predetermined calculation process is performed based on the instruction. As shown in FIG. 28, the coprocessor 1 includes a micro R storing a micro program in which a predetermined operation procedure and the like are described.
An OM (read only memory) 4 is provided. The micro ROM 4 is accessed by the controller 5, whereby the micro instructions constituting the micro program are sequentially read.

The controller 5 fetches a command given from a main processor (not shown) via the bus interface circuit 2 and the internal bus 6 and decodes a command code included in the command or an address signal obtained by decoding the command code. The micro ROM 4 is accessed based on the address information included in the command. As a result, the first microinstruction of a series of microinstructions for performing the arithmetic processing specified by the command is read from the micro ROM 4. As for the second and subsequent micro-instructions in the series of micro-instructions for performing the arithmetic processing indicated by the above-mentioned command, information of the next address field of the micro-instruction read immediately before is supplied to the controller 5. Directed by The microinstruction read from the microROM 4 in this manner is supplied to the microinstruction decoder 7. The microinstruction decoder 7 decodes a given microinstruction and generates a control signal for the execution unit 3 and the like. In addition, when the execution unit 3 performs arithmetic processing or the like according to the microinstruction, if the microflow needs to be branched, the execution unit 3 gives the instruction to the controller 5.

The execution unit 3 is connected to the internal bus 6 and has a pair of RAMs (random access memories).
9 and 10. The RAMs 9 and 10 store in advance data necessary for calculations supplied from the outside,
It is used as a temporary register during arithmetic processing. Access control to the RAMs 9 and 10 is performed based on a control signal 8 output from the micro instruction decoder 7. For example, at the time of floating point arithmetic,
When ten predetermined areas are used as temporary registers, the RAMs 9 and 10 read source data therefrom, and the read source data is processed, for example, and returned to the RAMs 9 and 10 as destination data. Perform read-modify-write operations.

FIG. 29 shows an example of the configuration of the execution unit 3.

The execution units 3 are not particularly limited, but have internal buses BUS1 and BU each having a 32-bit structure.
S2, BUS3. These internal buses BUS1 and BU
An arithmetic logic unit 11, a shift operation unit 12, a shift counter SCUNT, and a temporary register 13 are connected to S2 and BUS3. The temporary register 13 can be allocated to a predetermined area of the RAMs 9 and 10.

FIG. 29 also shows a shift control data forming circuit SFG included in the controller 5. For example, the command includes data indicating the shift amount in the command, similarly to the command of the above embodiment. The shift control data forming circuit SFG extracts the shift amount from a command, for example, and supplies the shift amount to the shift operation device 12 as shift control data SF.

FIG. 21 shows a detailed configuration of the shift operation device 12.

The shift operation device 12 shown in FIG.
Although not particularly limited, when N and n are positive integers,
n-bit shift control data (coded data)
There is a barrel shift circuit that can shift an arbitrary number of bits up to N = 2 ⁿ bits for two words of input data in response to S0,..., Sn-2, Sn-1. The barrel shift circuit includes a left shift circuit group 20 for left-shifting one word of input data indicated by I1 to IN,
A right-shift circuit group 21 for right-shifting one word of input data indicated by J1 to JN.

Here, although not particularly limited, the left shift means, for example, as shown in FIG.
2, I3, and I4, the shift result is the data string I2,
The right shift refers to the case where the input data is shifted to the upper side so as to be I3 and I4. The right shift refers to the shift result of the input data J1, J2, J3 and J4 as shown in FIG. Is a data string J1, J2, J3.

The left shift circuit group 20 and the right shift circuit group 21 do not need the decoder DEC for decoding the n-bit shift control data SF as shown in FIG. You.

The left shift circuit group 20 has 2 ⁱ
N shift circuits LSF0,..., LSFn- enabling data shift of (i = 0, 1, 2,..., N-1) bits.
2, LSFn-1 are connected in series. For example, the shift circuit LSFn-1 has a function of shifting the input data I1 to IN for ^one word to the left by 2 ^n-1 bits when the shift control data Sn-1 is asserted to a high level. The arranged shift circuit LSFn-2 has a function of shifting the input data left by 2 ^n-2 bits when the shift control data Sn-2 is asserted to a high level, and the shift circuit LSFn-2 arranged at the subsequent stage thereof. LSF0, when the shift control data S0 is asserted to a high level, a function of the input data 2 ⁰ bit (i.e., 1 bit) left shift.

The right shift circuit group 21 has 2 ⁱ (i = 0, 1, 2, 2), similarly to the left shift circuit group 20.
.., RSFn-2, RSFn-1 are connected in series, and an input first stage thereof has the above-mentioned shift circuits RSF0,. To properly combine the shift output of the left shift circuit group 20 and the shift output of the right shift circuit group 21,
Shifts the input data J1 to JN of one word to the right by one bit regardless of the shift control data S0,..., Sn-2, Sn-1.
A bit right shift circuit 23 is provided. The shift circuit RSFn-1 arranged at the subsequent stage of the shift circuit 23 receives data Sn-1 * (* indicates data inversion or low active) obtained by inverting the shift control data Sn-1 by the inverter INn-1. It has a function of shifting the input data right by 2 ^{n -1} bits when asserted to a high level, and a shift circuit RSFn-2 arranged at the subsequent stage thereof has an inverter INn- which inverts the shift control data Sn-2. 2 output data Sn-
When 2 * is asserted to a high level, it has a function of shifting the input data right by 2 ⁿ⁻² bits, and a shift circuit RSF0 disposed at the subsequent stage thereof outputs the output of the inverter IN0 which inverts the shift control data S0. data S0 * has a function of 2 ⁰ bit (i.e., 1 bit) right shift input data when it is asserted high.

The outputs of the left shift circuit group 20 and the right shift circuit group 21 are combined into one word to be the shift outputs O1 to ON of the barrel shift circuit of this embodiment. The shift circuits (excluding the 1-bit right shift circuit 23) included in the left shift circuit group 20 and the right shift circuit group 21 are provided with the shift control data S0,..., Sn-2, Sn-1.
, A gate circuit for switching between the data through state and the data shift state in a relatively simple manner.

For example, if one-word input data I 1 to IN are set to 2
^The shift circuit LSFn-1 that shifts left by ^n-1 bits is shown in FIG.
, A plurality of N-channel MOSFETs QI1 that are turned on / off by the output of an inverter INL that inverts the shift control data Sn-1, and a plurality of N that are turned on / off by the shift control data Sn-1.
And a channel type MOSFET QI2. The plurality of MOSFETs QI1 and the plurality of MOSFETs QI2 are turned on / off complementarily by the interposition of the inverter INL. A multiplexer for selecting the input data I1 to IN is formed by the pair of MOSFETs QI1 and QI2. You. That is, when the shift control data Sn-1 is at a low level, the plurality of MOSFETs QI1 are turned on and the plurality of MOSFETs QI2 are turned off, so that the input data I1 to IN remain unchanged (unshifted) and The signal is transmitted to the shift circuit LSFn-2 (through state). On the other hand, when the shift control data Sn-1 is at a high level, a plurality of MOSFETs QI1
Is turned off and the plurality of MOSFETs QI2 are turned on, whereby the bits of the input data I1 to IN are shifted and then transmitted to the subsequent shift circuit LSFn-2 (shifted state). Since the data shift amount in the shift circuit LSFn-1 is 2 ^n-1 bits, for example, the data I1
Data I31 is assigned in place of 5, and data I1 is similarly assigned.
Data IN is assigned in place of 6, and such data selection enables shifting of 2 ^{n -1} bits of input data I1 to IN.

Similarly, one word of input data J1 to JN
23. As shown in FIG. 23, a shift circuit RSFn-1 that shifts right by 2 ^n-1 bits has a plurality of N-channel types that are on / off controlled by the output of an inverter INR that inverts the shift control data Sn-1 *. It includes a MOSFET QJ1 and a plurality of N-channel MOSFETs QJ2 that are turned on / off by shift control data Sn-1 *. Multiple MOSFETs QJ1 with the intervention of inverter INR
And a plurality of MOSFETs QJ2 are turned on / off complementarily, and a pair of MOSFETs QJ1 and QJ2
A multiplexer for selecting the input data J1 to JN is formed by J2. That is, the shift control data Sn-
When 1 * is at the low level, the plurality of MOSFETs QJ1 are turned on and the plurality of MOSFETs QJ2 are turned off, so that the input data J1 to JN are left as they are (unshifted), and the subsequent shift circuit RSFn-2
(Through state). On the other hand, when the shift control data Sn-1 * is at a high level, a plurality of MOSFs
When the ETQJ1 is turned off and the plurality of MOSFETs QJ2 are turned on, the bits of the input data J1 to JN are shifted and then transmitted to the subsequent shift circuit RSFn-2 (shift state). Since the data shift amount in this shift circuit RSFn-1 is 2 ^n-1 bits, for example, data J2 is selected instead of data J18, and data J1 is similarly selected instead of data J17. By data selection, the input data J1 to JN can be shifted by 2 ^n-1 bits.

The other shift circuits included in the right shift circuit group 21 are configured in the same manner as described above except that the shift amounts there are different.

Next, a configuration example of the barrel shift circuit when the input data is 4 bits will be described with reference to FIG.

In FIG. 26, the left shift circuit group 20 includes
A shift control data S1 is 2 ¹ bit left shift circuit to enable 2-bit shift of the input data I1 to I4 by being asserted high level LSF1, disposed on the subsequent stage, asserts the shift control data S0 is at a high level composed of 2 ^0-bit left shift circuit LSF0 Prefecture to allow 2 ⁰ = 1-bit shift of the input data by being. Similarly to the left shift circuit group 20, the right shift circuit group 21 includes a 1-bit right shift circuit 23 that shifts the input data J1 to J3 by 1 bit, and an inverter IN1 that inverts the shift control data Sn-1. output data S1 * is a 2 ^1-bit right shift circuit RSF1 that enables 2-bit shift input data by being asserted high level, the output data S0 * is high the inverter IN0 for inverting the shift control data S0 to enable 1-bit shift of the input data by being asserted to the level and a 2 ⁰ bit right shift circuit RSF0.
The left shift circuits LSF1 and LSF0 and the right shift circuits RSF1 and RSF0 each include a gate circuit for switching between a data through state and a data shift state in response to the shift control data S1 and S0 as described above. Is done. That is, the left shift circuits LSF1 and LSF0 are
23, and the right shift circuits RSF1 and RSF0 are provided with a plurality of N-channel MOSFETs that are complementarily turned on / off in response to shift control data, respectively, as shown in FIG. It is comprised including. Note that the plurality of blocks B in FIG. 26 are multiplexers formed by a combination of MOSFETs in FIG. 22 or FIG. 23 or MOSFETs operated in a complementary manner.

Here, the 1-bit right shift circuit 23 operates as follows. For example, as shown in FIG. 27, when the shift control data "S1, S0" is set to "0, 1", the input data I1, I2, I3, I4 are shifted left by one bit. The shift result is the upper three bits I1, I2, I3. When the shift control data "01" in that case is inverted by the inverters IN1 and IN2, "S1 *, S2 *" becomes "1, 0", and a two-bit right shift is instructed. That is, other input data J
1, J2 and J3 are shifted to the right by 2 bits to be lower 2 bits J1 and J2. In this state, since I3 and J1 compete with each other, it is not possible to combine the left shift result and the right shift result into a 4-bit output. Therefore, the above 2
If the bit right shift result is further shifted right by one bit,
The result is the lower 1 bit J1, so the 4-bit shift combined output of the 2-word data (I1,
I2, I3, J1) can be obtained. In this sense, when the data shift outputs for two words are combined to obtain the one-word shift outputs O1 to O4 as in this embodiment, it is considered that the one-bit shift by the one-bit right shift circuit 23 is effective. Is done.

According to this embodiment, the following functions and effects can be obtained. (6) When n is a positive integer, 2 ⁱ (i =
Left shift circuit LSF as n shift circuits enabling data shift of 0, 1, 2, ..., n-1) bits
0,..., LSFn-2, LSFn-1, and right shift circuit RSF
By having 0,..., RSFn-2, and RSFn-1, n
The bit-coded shift control data is directly fetched without decoding, and a shift operation of an arbitrary number of bits up to 2 ⁿ bits of the input data is enabled in response. Therefore, a decoder D for decoding n-bit shift control data SF as shown in FIG.
EC is not required. (7) Since the decoder DEC for decoding the shift control data is not required due to the effect of the above item (6), a signal delay in the decoder DEC is eliminated, thereby improving the operation speed of the barrel shift circuit. It is possible. Also, by omitting the decoder DEC, L
The area occupied by the barrel shift circuit in the SI chip can be reduced. (8) The effect (7) can also be obtained in a coprocessor to which the barrel shift circuit of the present embodiment is applied. (9) When the data shift outputs for two words are combined to obtain a shift output for one word as in the present embodiment, the 1-bit shift circuit 23 that shifts the input data by 1 bit regardless of the shift control data is provided. By providing such a composite output, such a combined output can be obtained accurately.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, the unit of data processing in the bit field operation operation according to the present invention is not limited to 32-bit word data, but may be 16 bits or 64 bits. Further, the operation of bit field operation such as extraction of an arbitrary area of data or replacement of an arbitrary area of data is not limited to the deposit instruction or the extract instruction of the above-described embodiment, and can be appropriately changed. Is not limited.

In the above embodiments (FIGS. 21 to 24), n shift circuits capable of shifting data of 2 ⁱ (i = 0, 1, 2,..., N−1) bits are provided by N channel Although it is formed by a type MOSFET, a transfer gate and other semiconductor elements can also be applied. The location of the 1-bit right shift circuit 23 is not limited to the first input stage of the right shift circuit group 21, but may be provided at an appropriate location such as the last stage of the right shift circuit group 21. In the above-described embodiment, an example including the left shift circuit group and the right shift circuit group has been described, but either one of them may be omitted. In that case, the 1-bit right shift circuit 23 is not particularly required.

When the embodiment shown in FIGS. 21 to 29 is applied to the previous embodiment, data representing the shift amount from the instruction unit IU is used as the shift control data. In this case, the decoder SDEC of FIG. 5 is not required, and the barrel shifters shown in FIGS. 21 to 29 are used for the barrel shifters BSFT1 and BSFT2, respectively.

In the above description, the invention made mainly by the present inventor is described in the field of application RIS, which is the background of the application.
Although the case where the present invention is applied to the C processor and the coprocessor has been described, the present invention is not limited thereto, and can be widely applied to a CISC type processor, a logic LSI, and the like.

[0097]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a barrel shifter is used for barrel shift of input data and mask data generation, respectively.
In addition, by making the shift amounts of both barrel shifters the same as each other and configuring an arithmetic device capable of operating a bit field, an arithmetic device for operating a bit field such as extraction of an arbitrary region of data or replacement of an arbitrary region of data can be realized. This has the effect of contributing to higher functionality and higher calculation speed.

By laying out the transistor rows of the two sets of barrel shifters in pairs one by one and folding them in accordance with the width of the storage cell for one bit of the register file, a bit field operation operation is performed. This has the effect that the chip occupation area of the arithmetic device can be reduced.

In parallel with the data shift of the input data by the first barrel shifter, sign extension is performed by a sign extension circuit, each processing result is selected and arithmetic shift is performed, thereby reducing an operation speed for extracting an arbitrary area of data. There is an effect that the speed can be increased.

By employing a logic for obtaining a decoding result using mask bits, a circuit for converting an input into a signal of a complementary level is not required, and the circuit scale or chip occupation area of the decoder can be reduced.

When n is a positive integer, by including n shift circuits capable of shifting data by 2 ⁱ (i = 0, 1, 2,..., N−1) bits,
N of the input data in response to the n-bit shift control data
= 2n bits, so that a decoder for decoding n-bit shift control data is not required, thereby improving the operation speed of the barrel shift circuit and improving the performance of the LSI chip. The area occupied by the barrel shift circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a chip plan view of an embodiment of a processor to which the present invention is applied.

FIG. 2 is a block diagram illustrating an example of an integer operation unit.

FIG. 3 is an explanatory diagram of instruction steps in which an operation of replacing an arbitrary area of data with an arbitrary area of another data is performed using the bit-field manipulation operation device of the present embodiment and a case where the operation is not performed; is there.

FIG. 4 is a block diagram showing an example of a graphic processing system using a processor.

FIG. 5 is a block diagram of one embodiment of a bit field manipulation operation device.

FIG. 6 is an explanatory diagram illustrating an example of a mask data generation circuit.

FIG. 7 is an explanatory diagram of sign extension processing in two cases performed by an extract instruction.

FIG. 8 is an explanatory diagram of parallel processing of barrel shift of input data and 0th bit sign extension of input data in an extract instruction.

FIG. 9 is a diagram showing FIG. 8 when executing an extract instruction;
It is explanatory drawing which shows the process following [of].

FIG. 10 is an explanatory diagram of a case in which a 0th bit code extension process and a barrel shift process for the input data shown in FIG. 8 are dependently or serially performed;

FIG. 11 is a circuit diagram illustrating an example of first and second barrel shifters.

FIG. 12 is an explanatory diagram showing a circuit configuration of a first barrel shifter extracted from both barrel shifters shown in FIG. 11;

FIG. 13 is an explanatory diagram showing a circuit configuration of a second barrel shifter extracted from both barrel shifters shown in FIG. 11;

FIG. 14 is a view for explaining an enlargement of a horizontal dimension when it is assumed that a height dimension of a region is reduced when separately laying out the circuits shown in FIGS. 12 and 13;

FIG. 15 is a block diagram showing an embodiment of a decoder for extracting the position of a code bit for sign extension with respect to data output from a mask execution circuit.

FIG. 16 is an explanatory diagram of a basic operation of an extract instruction.

FIG. 17 is a diagram illustrating a basic operation of a deposit instruction.

FIG. 18 is an explanatory diagram of a mask data generation circuit using a subtractor.

FIG. 19 is a diagram showing a format of an extract instruction and a deposit instruction.

FIG. 20 is a block diagram showing one embodiment of the extension circuit of FIG. 5;

FIG. 21 is a block diagram showing another embodiment of the barrel shift circuit.

FIG. 22 is a circuit diagram showing a configuration example of a left shift circuit included in the barrel shift circuit of FIG. 21;

FIG. 23 is a circuit diagram showing a configuration example of a right shift circuit included in the barrel shift circuit of FIG. 21;

FIG. 24 is a diagram for explaining left shift of input data.

FIG. 25 is a diagram for explaining right shift of input data;

FIG. 26 is a block diagram showing the configuration of the barrel shift circuit of FIG. 21 when the shift target data is 4 bits.

FIG. 27 is an explanatory diagram of combining left shift output and right shift output.

FIG. 28 is a block diagram illustrating a configuration of a coprocessor including a barrel shift circuit according to an embodiment;

FIG. 29 is a block diagram showing a configuration of an execution unit included in the coprocessor.

FIG. 30 is a circuit diagram of a conventional barrel shifter circuit.

[Explanation of symbols]

MCU Processor EU Integer operation unit SMU Bit field operation operation device REGF Register file BSFT1 First barrel shifter BSFT2 Second barrel shifter SDEC Shift decoder MASKG Mask data generation circuit MBG Mask bit generation circuit MASKD1 First mask data MASKD2 Second mask data EXT1 Extension circuit 0th bit sign extension circuit MASKE mask execution circuit LGC logic gate circuit EOR exclusive OR circuit m1-in0 Lower input signal line of second barrel shifter m2-in0 Upper input signal line of second barrel shifter m-out0 Second barrel shifter Output signal line d1-in0 Lower-side input signal line of first barrel shifter d2-in0 Upper-side input signal line of first barrel shifter d-out0 First barrel Shifter output signal line shift0 Shift amount control line of first barrel shifter and second barrel shifter 1 Coprocessor 2 Bus interface 3 Execution unit 4 Micro ROM 5 Controller 7 Micro instruction decoder 9 RAM 10 RAM 11 Arithmetic logic operation device 12 Shift operation device 13 Temporary register 20 Left shift circuit group 21 Right shift circuit group 23 1-bit right shift circuit group LSFN-1 2 ^n-1 bit left shift circuit LSFN-2 2 ^n-2 bit left shift circuit LSF0 20 ⁰ bit left shift circuit RSFN- 1 2 ^n-1 bit right shift circuit ^RSFN-2 2 ^n-2 bit right shift circuit RSF0 2 ⁰ bit right shift circuit

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-58-40665 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 5/01 G06F 7/00 H01L 27 / Ten

Claims (10)

(57) [Claims] A data supply unit for supplying predetermined data including a plurality of mask bits; a control unit for supplying a shift control signal indicating a shift amount to be shifted; and a control unit coupled to the control unit. A first barrel shifter that shifts bits of input data and outputs the shifted input data including a plurality of input bits, and is coupled to the control unit, and shifts bits of control data according to the shift amount; Outputting mask data including a plurality of control bits, and each of the plurality of control bits is
A second barrel shifter corresponding to each of the plurality of input bits and indicating whether the corresponding input bit is a bit to be masked, the first barrel shifter, the second barrel shifter and the second barrel shifter. Supply means coupled to data supply means for selectively supplying the mask bits instead of input bits indicated as bits to be masked by the mask data from the second barrel shifter, each of which outputs an input signal; And a plurality of control data supply circuits each having an output terminal for outputting a control signal, and a plurality of control data supply circuits each having an output terminal for outputting a control signal. The first barrel shifter includes a plurality of output terminals for outputting the shifted input data, and a plurality of the input data. A plurality of input terminals coupled to each of the output terminals of the supply circuit; and a first matrix, wherein the first matrix includes a plurality of first insulated gate field effect transistors arranged in a matrix. Each of the plurality of columns in the first matrix has at least one of the plurality of output terminals and at least one of the plurality of input terminals,
And at least one first insulated gate field effect transistor coupled between the at least one output terminal and the at least one input terminal, wherein each of a plurality of rows in the first matrix is A plurality of first insulated gate field effect transistors, the gates of which are coupled to a shift control line in common, and one of the shift control signals is supplied via the coupled shift control line. The barrel shifter includes a plurality of output terminals for outputting the mask data, a plurality of input terminals coupled to respective output terminals of the plurality of control data supply circuits, and a second matrix, wherein the second matrix includes: A plurality of second insulated gate field effect transistors arranged in a matrix, wherein each of a plurality of columns in the second matrix comprises:
At least one of the plurality of output terminals, at least one of the plurality of input terminals, and at least one second insulation coupled between the at least one output terminal and the at least one input terminal. Each of the plurality of rows in the second matrix includes a gate type field effect transistor, and each of the plurality of rows is coupled to the shift control line in common, and the shift control line is coupled via the coupled shift control line. A plurality of second signals supplied with one of the signals
A row of first insulated gate field effect transistors of the first barrel shifter and a row of second insulated gate field effect transistors of the second barrel shifter are alternately arranged in parallel. A bit-field manipulation operation device, characterized in that: 2. The bit field operation operation according to claim 1, wherein said control means includes a decoder for supplying a decode signal to said first barrel shifter and said second barrel shifter as said shift control signal. apparatus. 3. One of the columns of the first matrix is arranged in a first area adjacent to a second area in which one of the columns of the second matrix is arranged. One is disposed in a third region adjacent to the first region and the second region,
2. The bit field operation and operation device according to claim 1, wherein the size of the third region in the direction of (b) is substantially equal to the size of the first and second regions in the first direction. 4. The control circuit includes a decoder having a plurality of output terminals coupled to shift control lines of the first and second matrices, wherein the decoder outputs the shift control signal as the shift control signal. 4. A bit field operation and operation device according to claim 3, wherein a decoding signal is supplied to the bit field operation device. 5. A microprocessor formed on a semiconductor substrate and executing a bit field operation in response to a bit field instruction, control means for forming a control signal in response to the instruction, an internal bus, A plurality of registers coupled to an internal bus; and a bit field operation / operation device coupled to the internal bus and the control means for executing a bit field operation in accordance with the bit field instruction. Data supply means coupled to the internal bus for supplying predetermined data having a plurality of mask bits according to the bit field instruction; and a decode signal indicating a shift amount to be shifted in response to the bit field instruction Means for instructing the shift amount for supplying A selecting means for selectively inputting data from the internal bus in response to a predetermined signal among the control signals; and a shift amount indicating means coupled to the selecting means and the shift amount indicating means. A first barrel shifter for shifting output data from the selection means according to the shift amount specified by the means and outputting shifted data including a plurality of input bits; and forming mask control data according to the bit field instruction. Mask control data forming means, coupled to the mask control data forming means and the shift amount indicating means, for shifting the mask control data according to the shift amount specified by the shift amount indicating means, and A second barrel shifter for outputting the shifted mask control data, Supply means coupled to the shifter, the second barrel shifter and the data supply means for supplying the mask bits instead of the input bits to be masked by mask control bits from the second barrel shifter; Wherein each of the plurality of mask control bits corresponds to each of the plurality of input bits and indicates whether or not the corresponding input bit is a bit to be masked. Includes a plurality of control data supply circuits each having an output terminal, wherein the first barrel shifter is coupled to a plurality of output terminals for outputting the shifted input data and an output terminal of the plurality of selection circuits. A plurality of input terminals, and a first matrix, wherein the first matrix includes a plurality of first insulating gates arranged in a matrix. Wherein each row of the first matrix includes at least one of the output terminals, at least one of the input terminals, the at least one output terminal, and the at least one input terminal. A first insulated gate field effect transistor coupled between the first matrix and each of the first matrixes, wherein each column of the first matrix has a shift control line coupled to its gate and is connected via the shift control line. A plurality of first insulated gate field effect transistors to which one of the decode signals is commonly supplied, the second barrel shifter includes a plurality of output terminals for outputting the shifted mask control data, and the plurality of control data. A plurality of input terminals coupled to an output terminal of the supply circuit, and a second matrix, wherein the second matrix comprises:
A plurality of second insulated gate field effect transistors arranged in a matrix, wherein each row of the second matrix comprises:
At least one of the output terminals, at least one of the plurality of input terminals, and at least one second insulated gate type coupled between the at least one output terminal and the at least one input terminal; Each of the columns of the second matrix, including a field effect transistor, includes a plurality of second insulating layers, the gates of which are connected to the shift control lines, to which the one decode signal is supplied via the shift control lines. A microprocessor including a gate type field effect transistor. 6. One of the rows of the first matrix is arranged in a first area adjacent to a second area in which one of the rows of the second matrix is arranged. In addition, one of the plurality of control data supply circuits includes the first area and the second area.
A third area adjacent to the area, wherein a size of the third area in a first direction is substantially equal to a size of the first and second areas in the first direction. Item 7. The microprocessor according to Item 5. 7. The bit field instruction includes a first field for indicating one of the registers and a second field for indicating a register or a third field in the bit field instruction. The contents specified by one field are supplied to the selection means, and the contents specified by the second field are supplied to the decoder to form the decode signal. The microprocessor according to claim 5, wherein 8. A mask data supply circuit for supplying predetermined data including a plurality of mask bits, a decoder for outputting a decode signal indicating a shift amount to be shifted, and an input according to a shift amount indicated by the decode signal. A first barrel shifter that shifts bits of data and outputs the shifted input data including a plurality of input bits; and shifts bits of control data according to a shift amount indicated by the decode signal. A second barrel shifter for outputting shifted control data including bits, coupled to the first barrel shifter, the second barrel shifter, and the mask data supply circuit, and masked by a control bit from the second barrel shifter Mask bits instead of the input bits shown as A plurality of input data supply circuits each having an output node for outputting a bit of the input data; and a plurality of control data each having an output node for outputting a bit of the control data. A bit field manipulation operation device formed on a semiconductor substrate, comprising: a supply circuit; and a plurality of signal lines coupled to the decoder and supplied with the decode signal from the decoder, wherein the first barrel shifter comprises: A plurality of rows in which insulated gate field effect transistors are arranged, each row including an input terminal coupled to an output node of the input circuit, an output terminal coupled to the selector, the input terminal and the output terminal Between the first insulated gate field effect transistor coupled to the input terminal in a row different from the output terminal A second insulated gate field effect transistor coupled to the control data circuit, wherein the second barrel shifter includes a plurality of rows in which the insulated gate field effect transistors are arranged, each row being connected to an output node of the control data circuit. A coupled input terminal, an output terminal coupled to the selector, a third insulated gate field effect transistor coupled between the input terminal and the output terminal, and an input terminal in a different row than the output terminal A fourth insulated gate field effect transistor coupled between the first and second insulated gate field effect transistors; a gate of the second insulated gate field effect transistor; a gate of the second insulated gate field effect transistor; Coupled to the gate of the third insulated gate field effect transistor and the gate of the fourth insulated gate field effect transistor Each row of the first barrel shifter and each row of the second barrel shifter are alternately arranged in parallel in a circuit configuration area width required by the input data circuit or the control data circuit. Characteristic bit-field operation arithmetic unit. 9. A gate of a first insulated gate field effect transistor in a plurality of rows and a gate of a third insulated gate field effect transistor in a plurality of rows are commonly coupled to one of the signal lines. The gate of a second insulated gate transistor in a row and a gate of a fourth insulated gate transistor in a plurality of rows are commonly connected to one of the signal lines. 8. The bit-field operation / operation device according to item 8. 10. The system according to claim 1, wherein each of the plurality of input data supply circuits includes a unit register and a unit selector, and each of the plurality of control data supply circuits includes a unit register and a unit selector. 8. The bit-field operation / operation device according to item 8.