JP3241642B2 - Binary-decimal conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary-decimal conversion circuit, and more particularly to a binary-decimal conversion circuit for improving a conversion processing speed in an information processing apparatus.

[0002]

2. Description of the Related Art In a conventional binary-decimal conversion circuit,
Conversion is repeated for each bit by the same number of times as the number of bits of the binary data to be converted, thereby converting the binary data to decimal data. For example, as disclosed in Japanese Patent Application Laid-Open No. Sho 59-168543, conversion is performed by generating binary data for each conversion cycle by using a decimal adder for binary data to be converted using a decimal adder for each bit. Is going.

FIG. 7 is a block diagram showing the configuration of this conventional technique. Referring to FIG. 7, the binary-decimal conversion circuit includes a binary data selector 11, a binary data register 12, a decimal adder 18, and a decimal data register 17. The binary data D0 to be converted and the data D3 obtained by shifting the binary data register 12 to the left by one bit are input to the binary data selector 11,
The output D1 of the binary data selector 11 is input to the binary data register 12, and the output D5 of the decimal data register 17 is output.
Is input to both inputs of the decimal adder 18 and the most significant bit D2 of the binary data register 12 is input to the decimal adder 18
And the output D4 of the decimal adder 18
Is input to the decimal data register 17.

In the above configuration, first, the binary data D0 to be converted is loaded into the binary data register 12 via the binary data selector 11,
The hex data register 17 is reset.

Next, the current most significant bit D2 of the binary data register 12 and the data D of the decimal data register 17
By adding 5 to the decimal adder 18, a double of the data D 5 of the decimal data register 17 and the current most significant bit D 2 of the binary data register 12 are added.

The output D4 of the decimal adder 18 is
At the same time as the data D stored in the binary data register 17,
3 is stored in the binary data register 12 via the binary data selector 11. By repeating this operation for the number of bits of the binary data, binary-decimal conversion is performed.

[0007]

A first problem in the above-mentioned prior art is that an addition operation is required as many times as the number of bits of binary data to be converted. As a result, the conversion processing time increases.

[0008] The second problem is that the circuit scale becomes large because a decimal adder is used.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a binary-decimal conversion circuit in which the conversion processing speed is improved and the circuit scale is taken into consideration.

[0010]

SUMMARY OF THE INVENTION A first binary 10 according to the present invention.
The binary conversion circuit is a binary-to-decimal conversion circuit that inputs i-bit binary data to be converted and converts the binary data into decimal data. A leading "1" detecting circuit for detecting the number of "0" bits until a bit appears, a shift circuit for performing a bit shift of binary data to the most significant side by a value detected by the leading "1" detecting circuit, A decimal double number generating circuit for generating a double of decimal data, a decimal quadruple number generating circuit for generating a quadruple of decimal data, and a decimal octal multiple generating circuit for generating an octal number of decimal data ,... Decimal "2" which generates a multiple of "2 (i-1) power" of decimal data
"(I-1) th power" multiple generation circuit, and the aforementioned decimal double generation circuit, decimal quadruple generation circuit, decimal octuple generation circuit, ..., "2 (i-1) th power" 2x, 4x, 8x, etc. of decimal data generated by the multiple generation circuit
.. a decimal data selector for selecting one of multiples of "2 to the power of (i-1)" based on a detection value of the leading "1" detection circuit.
Base conversion circuit.

The second binary-decimal conversion circuit of the present invention is a binary-decimal conversion circuit that inputs i-bit binary data to be converted and converts the binary data into decimal data. A) a binary data register for holding the i-bit binary data to be converted and the temporary binary data being converted;
(B) a leading "1" detection circuit for detecting the number of "0" bits from the most significant bit of the binary data output from the binary data register until the first "1" bit appears; c) a shift circuit that outputs data obtained by bit-shifting the output of the binary data register to the most significant side by the number of detection values of the reading “1” detection circuit;
(D) selecting one of the binary data to be converted and the data after the second bit after removing the most significant bit from the output data of the shift circuit, and selecting the data as storage data of the binary data register. (E) temporary decimal data during conversion processing and 1 of final conversion result
Zero-level data is stored, and the least significant bit of the output of the decimal data selector is replaced with the most significant bit of data shifted to the most significant side by the shift circuit by the value detected by the leading "1" detection circuit. A decimal data register for outputting data; (f) a decimal double number generating circuit for generating a double of the decimal data from an output of the decimal data register; A decimal quadruple number generating circuit for generating a quadruple number, a decimal octal number generating circuit for generating an octal number of decimal data from the output of the decimal data register,
A decimal "2 (i-1)" multiple generation circuit for generating a "2 (i-1)" multiple of the decimal data from the output of the decimal data register; Binary multiple generation circuit, decimal quadruple generation circuit, decimal octal multiple generation circuit,..., Doubles and quadruples of decimal data generated by the “(2−1) power” multiple generation circuit , 8 multiples,
... Select one of multiples of "2 to the (i-1) th power" by the detection value of the leading "1" detection circuit.
And a binary data selector.

A third binary-decimal conversion circuit according to the present invention is a binary-decimal conversion circuit for inputting i-bit binary data to be converted and converting the binary data into decimal data. A leading "1" detection circuit for detecting the number of "0" bits from the most significant bit of the data to the first appearance of a "1" bit, and binary data corresponding to the value detected by the leading "1" detection circuit. A shift circuit for performing a bit shift to the most significant side, and a first decimal 2 for generating a double number of decimal data
A multiple generation circuit, a second decimal double generation circuit for generating a quadruple of decimal data by inputting an output of the first decimal double generation circuit, and a second decimal binary
A third decimal double generation circuit that generates an eight-fold number of decimal data by inputting an output of the multiple generation circuit;
.. By inputting the output of the (i-2) th decimal double generation circuit that generates the "2 (i-2) power" multiple of the decimal data, the decimal data "2 (i)" is input. -1) a (i-1) th decimal double generation circuit for generating a power "multiple;
The first decimal double number generation circuit, the second decimal double number generation circuit, the third decimal double number generation circuit,..., The (i-1) th decimal double number generation circuit Generate 10
A decimal data selector for selecting any one of a double, a quadruple, an eight,..., A “2 (i−1) power” multiple of the decimal data based on a detection value of the leading “1” detection circuit; It is characterized by having.

The fourth binary-decimal conversion circuit of the present invention is a binary-decimal conversion circuit that inputs i-bit binary data to be converted and converts the binary data into decimal data. A) a binary data register for holding the i-bit binary data to be converted and the temporary binary data being converted;
(B) a leading "1" detection circuit for detecting the number of "0" bits from the most significant bit of the binary data output from the binary data register until the first "1" bit appears; c) a shift circuit that outputs data obtained by bit-shifting the output of the binary data register to the most significant side by the number of detection values of the reading “1” detection circuit;
(D) selecting one of the binary data to be converted and the data after the second bit after removing the most significant bit from the output data of the shift circuit, and selecting the data as storage data of the binary data register. (E) temporary decimal data during conversion processing and 1 of final conversion result
Zero-level data is stored, and the least significant bit of the output of the decimal data selector is replaced with the most significant bit of data shifted to the most significant side by the shift circuit by the value detected by the leading "1" detection circuit. A decimal data register for outputting data; (f) a first decimal double generation circuit for generating a double of decimal data from an output of the decimal data register; and a first decimal double generation circuit. A second decimal double generation circuit for generating a quadruple of the decimal data by inputting an output of the circuit; and a second decimal double generation circuit for inputting the output of the second decimal double generation circuit.
A third decimal doubling generation circuit for generating an octal multiple of decimal data,... A (i-2) th decimal generating a "2 (i-2) power" multiple of the decimal data By inputting the output of the double number generation circuit, the decimal data "2 (i-
(1) a (i-1) -th decimal double generation circuit for generating a multiple, and (g) the first decimal double generation circuit, a second decimal double generation circuit, and a third. Decimal doubling generation circuit,..., 2 times, 4 times, 8 times, etc. of decimal data generated by the (i-1) th decimal doubling number generation circuit
... Select one of multiples of "2 to the (i-1) th power" by the detection value of the leading "1" detection circuit.
And a binary data selector.

A fifth binary-decimal conversion circuit according to the present invention is a binary-decimal conversion circuit for inputting i-bit binary data to be converted and converting the binary data into decimal data. A leading "1" detection circuit for detecting the number of "0" bits from the most significant bit to the first "1" bit in the specific number n bits smaller than the i bits of the data; A shift circuit that performs a bit shift from the minimum 0 bits to the maximum n bits to the most significant bit according to the detection value of the leading “1” detection circuit, and a multiple of two, four, eight,. (N + 1)
(N + 1) decimal doubling generators each generating a “multiplier” multiple, and doubling, quadrupling, and doubling the decimal data generated by the (n + 1) decimal doubling generators.
And a decimal data selector for selecting any one of octal multiples,..., "2 to the power of (n + 1)", based on the detection value of the leading "1" detection circuit.

A sixth binary-decimal conversion circuit according to the present invention is a binary-decimal conversion circuit for inputting i-bit binary data to be converted and converting the binary data into decimal data. A) a binary data register for holding the i-bit binary data to be converted and the temporary binary data being converted;
(B) In a specific number n bits consecutive from the most significant bit smaller than the i bit of the binary data output from the binary data register, bits of “0” until a bit of “1” first appears. (C) a shift circuit that outputs data obtained by bit-shifting the output of the binary data register to the most significant side by the number of detection values of the reading “1” detection circuit; , (D) selecting either the binary data to be converted or the data after the second bit after removing the most significant bit from the output data of the shift circuit, and sets the selected data as the data stored in the binary data register. A binary data selector,
(E) The temporary decimal data during the conversion process and the decimal data of the final conversion result are stored, and the least significant bit of the output of the decimal data selector is changed by the value detected by the leading "1" detection circuit. A decimal data register for outputting data replaced with the most significant bit of the data shifted to the most significant side by the shift circuit, and (f) connecting each of them in series to convert the output of the decimal data register to decimal 2 Multiple, decimal 4 multiple, decimal 8 multiple,
..., (n + 1) decimal double generation circuits for generating and outputting the decimal "2 (n + 1) power" multiples, and (g) generation by the (n + 1) decimal double generation circuits 2 times, 4 times, 8 times, ..., "2
And a decimal data selector for selecting any one of the multiples of (n + 1) th power based on the detection value of the leading “1” detection circuit.

[0016]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention. Referring to FIG. 1, the binary-decimal conversion circuit of the present invention includes a binary data selector 11.
A binary data register 12, a reading "1" detection circuit 13, a shift circuit 14, eight decimal double generation circuits 15 (1) to 15 (8), a decimal data selector 16, And a decimal data register 17. Note that all eight decimal double generation circuits have the same circuit configuration.

Next, the connection between the constituent circuits will be described.

The binary data 000 to be converted and the data 401 excluding the most significant bit of the output of the shift circuit 14 are input to the binary data selector 11. The output 100 of the binary data selector 11 is the binary data register 12
Is input to The output 7 of the 7 most significant bits of the binary data register 12 is input to the reading “1” detection circuit 13. The output data 300 of the reading “1” detection circuit 13 is input to the shift circuit 14 as a shift amount and is also input to the decimal data selector 16 as a select control signal. Output 2 of binary data register
01 is input to the shift circuit 14 as shift data. Most significant 1-bit data 4 of the output of shift circuit 14
00 is input to the decimal data register 17 as replacement data.

The output 5 of the decimal data register 17
00 is input to the decimal double number generation circuit 15 (1). The output of the decimal double generation circuit 15 (1) is input to the decimal double generation circuit 15 (2).
15 (2) → 15 (3) → 15 (4)... → 15 (8), the output of each decimal double generation circuit 15 is input to the next decimal double generation circuit 15. . Further, respective outputs 601 to 608 of the decimal double number generation circuits 15 (1) to 15 (8) are input to the decimal data selector 16 as select data. And 10
The output data 700 of the decimal data selector 16 is input to the decimal data register 17.

FIG. 2 is a circuit diagram of the decimal double generation circuit 15 shown in FIG.
It is a block diagram of. Each of the decimal doubling generation circuits 15 (1) to 15 (8) shown in FIG. 1 has the configuration shown in FIG.

Each decimal doubling circuit generates j digits (j is a positive integer) of decimal data; d0 (0), d0 (1), d0 (2), d0 (3),. (0), di-1
(1), di-1 (2), di-1 (3), di (0), di (1), di (2), di (3),
di + 1 (0), di + 1 (1), di + 1 (2), di + 1 (3) ... dj-1 (0),
From dj-1 (1), dj-1 (2), dj-1 (3), decimal double data; D-1 (3), D0 (0), D0 (1), D0 (2), D0 (3) ・ ・ ・ Di-1 (0),
Di-1 (1), Di-1 (2), Di-1 (3), Di (0), Di (1), Di (2), D
i (3), Di + 1 (0), Di + 1 (1), Di + 1 (2), Di + 1 (3) ... Dj-
A double number generation circuit 151 is provided for each digit so as to generate 1 (0), Dj-1 (1), Dj-1 (2), and Dj-1 (3). The double number generation circuit 151 (0) corresponds to the most significant digit, and 151 (j-1) corresponds to the least significant digit. Note that these double number generation circuits 151 all have the same configuration.

FIG. 3 is a diagram showing a double number generating circuit 1 for each digit shown in FIG.
FIG. 51 is an example of a detailed circuit diagram of reference numeral 51.

FIG. 4 is a conversion table of the decimal double number generating circuit at the time of one digit conversion. As shown in FIG. 4, one digit of the decimal data is from “0” to “9”, and its double number is from “0” to “18”. And decimal 2
The least significant bit of the conversion digit of the multiple generation result is always "0".

FIG. 5 is a conversion table of a decimal double generation circuit for multi-digit conversion. In the generation of a decimal double of a multi-digit decimal number, one carry from the lower digit occurs, but as described with reference to FIG. 4, the least significant bit of each digit is 2 bits.
Since the value is multiplied to “0”, one bit of carry from the lower digit can be directly input.

Therefore, any one digit di (0), di (1), di (2), di (3) of a j-digit decimal number is converted to a decimal double number Di-1 (3), Di (0). ), Di (1), Di (2), Di (3) (i is a positive integer between 0 and j-1), Di-1 (3) = di (0) + di (1) ) * (di (2) + di (3)) Di (0) = di (0) * di (3) + di (1) * di (2) '* di (3)' Di (1) = di (0) * di (3) '+ di (1)' * di (2) + di (2) * di
(3) Di (2) = di (0) '* di (1)' * di (3) + di (1) * di (2) * di
(3) It can be generated by the logic of '+ di (0) * di (3)'.

Here, "*" indicates a logical product, "+" indicates a logical sum, and "'" indicates an inversion (complement).

Therefore, by connecting the double number generation circuits 151 shown in FIG. 3 for each digit in parallel as shown in FIG. Binary doubles can be generated.

Next, the operation of the binary-decimal conversion circuit of the present invention will be described in detail with reference to FIGS. FIG. 6 is a state transition table of conversion in the binary-decimal conversion circuit.

First, the binary data 000 to be converted is converted via the binary data selector 11 into the binary data register 12.
And the decimal data register 17 is reset.

Next, the leading "1" detecting circuit 13
Is the number of bits 3 until the first "1" appears in the most significant 7-bit data 200 of the binary data register 12.
00 is detected. Then, the shift circuit 14 shifts the output 201 of the binary data register 12 to the left by the number of bits.

Further, the leading "1" detecting circuit 13
Inputs the number of bits 300 to the decimal data selector 16 as a select control signal.

The double-decimal number generating circuit 15 calculates 15 (1)
15 to (8) are connected as shown in FIG.
The output 500 of the 0-ary data register 17 is input to the decimal double generation circuit 15 (1). Therefore, 10
15 from the output 500 of the binary data register 17
The output 601 of (1) is a double number and the output 602 of 15 (2)
Is a multiple, 15 (3) output 603 is an 8 multiple, 15
The output 604 of (4) is a multiple of 16 and the output 60 of 15 (5)
5 is 32 multiples, 15 (6) output 606 is 64 multiples, 1
The output 607 of 5 (7) is a multiple of 128, and the output 608 of 15 (8) is a multiple of 256, so that the output 607 is doubled every time it passes through one decimal double generation circuit 15.

The decimal data selector 16 selects one of the outputs 601 to 608 according to the number of bits 300 input as a select control signal from the leading "1" detection circuit 13. For example, as shown in FIG. 6, when the number of bits 300 is 0, the number is 601, which is a double number, when the number of bits 300 is 1, 602, which is a quadruple number, and when the number of bits 300 is 2, 603,
In the case of 7, 608 which is a multiple of 256 is selected.

The data 700 selected as described above is
Decimal data selector 16 to decimal data register 1
7 is input.

The decimal data register 17 stores the least significant one bit of the data 700 selected by the decimal data selector 16 into the most significant one bit 4 inputted from the shift circuit 14.
Replaced with 00 and stored.

The data 401 excluding the most significant bit of the output of the shift circuit 14 is converted to the binary data selector 11.
Through the binary data register 12.

The above operation is performed by converting the binary data 000 to be converted.
Is repeated until all the bits of the binary data register 12 have disappeared from the binary data register 12, thereby converting the binary data 000 to be converted into the decimal data 500. As shown in FIG. 6, the binary data 000 to be converted is “1100000000000100”.
In the case of 10 ", 1 cycle is obtained by repeating the conversion for 6 cycles.
Zero-level data "49170" is obtained.

While the operation of the present invention has been described mainly with reference to FIG. 1, the transition of the output value of each constituent circuit shown in FIG. 6 will be described along with the operation.

FIG. 6 is a state transition table of the conversion in the binary-decimal conversion circuit.
9 is a state transition table showing output values of each component circuit in each operation cycle in an operation in a case where the data is converted to decimal data assuming “000000010010”.

First, the binary data to be converted "11000"
0000000010010 "is loaded into the binary data register 12 via the binary data selector 11, and the decimal data register 17 is reset to" 00000 ". This state is cycle 0 shown in FIG.

First, in the first conversion cycle, since the most significant bit of the binary data register 12 is "1", the value of the output 300 of the reading "1" detection circuit 13 becomes "0". The output 400 of the shift circuit 14 has the value “1100000000000” of the output of the binary data register 12.
10010 "becomes the most significant 1 bit" 1 "left-shifted using the value" 0 "of the output 300 of the leading" 1 "detection circuit 13 as the shift amount.
01 is an output value “1100” of the binary data register 12.
000000010010 ”to the leading“ 1 ”
The data "1000" of the second most significant bit after the left-shifted value with the value "0" of the output 300 of the detection circuit 13 shifted to the left as a shift amount.
000000100100 ". The shift circuit 1
The value of 401 of the output of 4 "10000000000001001"
00 "is stored in the binary data register 12 via the binary data selector 11. The decimal data selector 16
Is the output 300 of the reading "1" detection circuit 13.
Of the output 601 of the decimal double generation circuit 15 (1) which is a multiple of the value "00000" of the output 500 of the decimal data register 17 by the value "0" of the decimal data register 17, is selected. The value “00001” obtained by replacing one bit with the value “1” of the output 400 of the shift circuit 14 is 1
It is stored in the 0-ary data register 17.

Next, in the second conversion cycle, since the most significant bit of the binary data register 12 is "1", the value of the output 300 of the reading "1" detection circuit 13 becomes "0". The output 400 of the shift circuit 14 is a value “100000000001” of the output of the binary data register 12.
00100 "becomes the most significant 1 bit" 1 "left-shifted using the value" 0 "of the output 300 of the leading" 1 "detection circuit 13 as the shift amount.
01 is the value of the output of the binary data register 12 "1000"
000000100100 ”to the leading“ 1 ”
The data "0000" of the second most significant bit after the left-hand shift, using the value "0" of the output 300 of the detection circuit 13 as the shift amount.
000001001000 ". The shift circuit 1
The value of 401 of the output of 4 "00000000000010010"
00 "is stored in the binary data register 12 via the binary data selector 11. The decimal data selector 16
Is the output 300 of the reading "1" detection circuit 13.
The value "00002" of the output 601 of the decimal double generation circuit 15 (1) which is a multiple of the value "00001" of the output 500 of the decimal data register 17 is selected by the value "0" of the The value “00003” obtained by replacing one bit with the value “1” of the output 400 of the shift circuit 14 is 1
It is stored in the 0-ary data register 17.

Next, in the third conversion cycle, the most significant 7 bits of the binary data register 12 are set to "000000".
Since it is 0, the value of the output 300 of the reading “1” detection circuit 13 is “7.” The output 400 of the shift circuit 14 is the value “000” of the output of the binary data register 12.
0000001001000 ”becomes the most significant 1 bit“ 0 ”left-shifted with the value“ 7 ”of the output 300 of the leading“ 1 ”detection circuit 13 as the shift amount.The output 401 of the shift circuit 14 is the binary data register 12
The output value “0000000001001000” is shifted to the left by using the value “7” of the output 300 of the leading “1” detection circuit 13 as the shift amount, and becomes the data “011001000000000000” of the second most significant bit. The value 401 of the output of the shift circuit 14 “010”
01000000000000 "is the binary data selector 1
1 is stored in the binary data register 12. 1
Based on the value “7” of the output 300 of the reading “1” detection circuit 13, the zero-decimal data selector 16 calculates the value of “00003” of the output 500 of the decimal data register 17 by two.
The value “00768” of the output 608 of the decimal double generation circuit 15 (8), which is a multiple of 56, is selected, and the least significant bit is replaced with the value “0768” of the output 400 of the shift circuit 14 to obtain the value “00776”. Is stored in the decimal data register 17.

Next, in the fourth conversion cycle, since the three most significant bits of the binary data register 12 are "01", the value of the output 300 of the reading "1" detection circuit 13 becomes "1". The output 400 of the shift circuit 14 is 2
Value of the output of the binary data register 12 "0100100000"
00000000 ”to the leading“ 1 ”detection circuit 1
The value of the output 300 of “3” becomes “1” of the most significant one bit left-shifted using the value “1” as the shift amount. The output 401 of the shift circuit 14 has the value “10” of the output of the binary data register 12.
01000000000000 "is the data" 0 "of the second most significant bit after the left-hand-shifted value" 1 "of the output 300 of the leading" 1 "detection circuit 13 as the shift amount.
The value of the output 401 of the shift circuit 14 is “0010000000000”.
00000 ”is stored in the binary data register 12 via the binary data selector 11. The decimal data selector 16 determines the decimal data by the value“ 1 ”of the output 300 of the reading“ 1 ”detection circuit 13. Register 17
Of the output 602 of the decimal double generation circuit 15 (2), which is a quadruple of the value of the output 500 of "0768""0307"
2 ", and the least significant bit is shifted by the shift circuit 1
The value “0307” replaced with the value “1” of the output 400 of No. 4
3 "is stored in the decimal data register 17.

Next, in the fifth conversion cycle, since the three most significant bits of the binary data register 12 are "001", the output 300 of the leading "1" detection circuit 13 is output.
Is "2". The output 400 of the shift circuit 14 is
The value of the output of the binary data register 12 "00100000"
00000000 "becomes the most significant 1-bit" 1 "left-shifted with the value" 2 "of the output 300 of the leading" 1 "detection circuit 13 as the shift amount.The output 401 of the shift circuit 14 is the binary data register 12 Output value “0”
010000000000000000 ", the data" 0 "from the second most significant bit after the left shift of the value" 2 "of the output 300 of the leading" 1 "detection circuit 13 as the shift amount.
The value of the output 401 of the shift circuit 14 is “00000000000000”.
00000 ”is stored in the binary data register 12 via the binary data selector 11. The decimal data selector 16 determines the decimal data by the value“ 2 ”of the output 300 of the reading“ 1 ”detection circuit 13. Register 17
Value of the output 603 of the decimal double generation circuit 15 (3), which is an eight multiple of the value "03073" of the output 500 of "2458"
4 ", and the least significant bit is shifted by the shift circuit 1
The value “2458” replaced with the value “1” of the output 400 of No. 4
5 "is stored in the decimal data register 17.

Next, in the sixth conversion cycle, since the effective bit of the binary data to be converted stored in the binary data register 12 is 1 bit, the output 300 of the reading "1" detection circuit 13 is: It becomes “0”. The output 400 of the shift circuit 14 is the binary data register 12
The output value “00000000000000000” is shifted leftward with the value “0” of the output 300 of the leading “1” detection circuit 13 as the shift amount, and becomes the most significant 1-bit “0”. The output 401 of the shift circuit 14 has the value “0000000000000” of the output of the binary data register 12.
"00000000" from the second most significant bit after left-shifting "0000" to the left using the value "0" of the output 300 of the leading "1" detection circuit 13 as the shift amount.
00000 ". The output 40 of the shift circuit 14
The value “000000000000000000” of 1 is stored in the binary data register 12 via the binary data selector 11. The decimal data selector 16 determines the value “2” of the output 500 of the decimal data register 17 based on the value “0” of the output 300 of the reading “1” detection circuit 13.
Decimal double generation circuit 15 which is a double of 4585 ″
The value “49170” obtained by selecting the value “49170” of the output 601 of (1) and replacing the least significant bit with the value “0” of the output 400 of the shift circuit 14 is stored in the decimal data register 17. .

In the above description, eight 10
Although the explanation has been made by using the binary number generating circuit 15,
The number can be an arbitrary number such as 12 or 12, and the conversion processing speed can be changed according to the number.

In the above description, eight 10
The binary double number generation circuits 15 are connected in series, and are doubled every time they pass through one decimal double number generation circuit 15. Instead of providing the same eight decimal double number generation circuits, 10 Binary multiple generation circuit, decimal quadruple generation circuit, 1
It is also possible to provide a octal-multiple-number generating circuit, a decimal 256-multiple-number generating circuit, and input the output of the decimal data register 17 to each generating circuit.

As described above, according to the present invention, the operation of converting the binary data "1100000000010010" into the decimal data "49170" can be performed without using an adder by using a cycle number smaller than the bit number of the binary data to be converted. Can be realized.

[0050]

As described above, the first advantage of the present invention is that the use of a plurality of decimal doubling circuits allows the continuous conversion of binary "0" bits of binary data to be converted. In this case, the conversion processing speed can be improved.

The second effect is that 1 is used instead of the decimal adder.
The use of the 0-ary double generation circuit allows the binary-decimal conversion circuit to be configured with a small amount of hardware, and also allows the conversion processing speed to be adjusted by changing the number of the decimal double generation circuits. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram of a decimal double generation circuit 15 of FIG. 1;

FIG. 3 is an example of a detailed circuit diagram of a double number generation circuit 151 for each digit in FIG. 2;

FIG. 4 is a conversion table of a decimal double generation circuit at the time of one-digit conversion.

FIG. 5 is a conversion table of a decimal double generation circuit at the time of multi-digit conversion.

FIG. 6 is a state transition table of conversion in a binary-decimal conversion circuit.

FIG. 7 is a block diagram showing a configuration of a conventional technique.

[Explanation of symbols]

 11 Binary data selector 12 Binary data register 13 Reading "1" detection circuit 14 Shift circuit 15 Decimal double multiple generation circuit 16 Decimal data selector 17 Decimal data register

Claims (6)

(57) [Claims] 1. A binary-decimal conversion circuit for inputting i-bit binary data to be converted and converting the binary data into decimal data, wherein the most significant bit of the binary data is "1" first. A leading "1" detecting circuit for detecting the number of "0" bits until a bit appears; a shifting circuit for performing a bit shift of binary data to the most significant side by a value detected by the leading "1" detecting circuit; A decimal double number generating circuit for generating a double of decimal data, a decimal quadruple number generating circuit for generating a quadruple of decimal data, and a decimal octal multiple generating circuit for generating an octal number of decimal data , ..., decimal data "2 (i-1)"
A decimal “2 (i−1)” multiple generation circuit that generates a “multiplier” multiple; and the decimal double multiple generation circuit, the decimal quadruple generation circuit, and 1
Occurrence octal multiple generation circuit,...
Double of decimal data generated by multiple generation circuit, 4
And a decimal data selector for selecting any one of a multiple, an eight multiple,..., A “2 (i−1) power” multiple based on a detection value of the leading “1” detection circuit. Binary-decimal conversion circuit. 2. A binary-decimal conversion circuit for inputting i-bit binary data to be converted and converting it into decimal data, comprising: (a) i-bit binary data to be converted; A binary data register for holding temporary binary data during the conversion process; and (b) a binary data register output from the binary data register until the first "1" bit appears from the most significant bit of the binary data. A leading "1" detecting circuit for detecting the number of "0" bits, and (c) data obtained by bit-shifting the output of the binary data register to the most significant side by the number of detection values of the leading "1" detecting circuit. And (d) the binary data to be converted,
Selecting any one of the data after the second bit, excluding the most significant bit, from the output data of the shift circuit;
A binary data selector for storing data in a decimal data register; and (e) storing temporary decimal data during conversion processing and decimal data of a final conversion result, and the least significant bit of the output of the decimal data selector. A decimal data register that outputs data obtained by replacing the most significant bit of data shifted to the most significant side by the shift circuit by the value detected by the leading “1” detection circuit; and (f) the decimal data register. , A decimal double generation circuit for generating a double of decimal data from the output of the decimal data register, a decimal quadruple generation circuit for generating a quadruple of the decimal data from the output of the decimal data register, and the decimal data register A octal-multiple-number generating circuit for generating an octal number of decimal data from an output of the decimal data register; Of 2 (i-1) th power "multiple decimal to produce a" 2 (i-1) th power "and multiple generating circuit, (g)
The decimal double generation circuit, the decimal quadruple generation circuit, 1
Occurrence octal multiple generation circuit,...
Double of decimal data generated by multiple generation circuit, 4
And a decimal data selector for selecting any one of a multiple, an eight multiple,..., A “2 (i−1) power” multiple based on a detection value of the leading “1” detection circuit. Binary-decimal conversion circuit. 3. A binary-to-decimal conversion circuit for inputting i-bit binary data to be converted and converting the binary data into decimal data, wherein the most significant bit of the binary data is first "1". A leading "1" detecting circuit for detecting the number of "0" bits until a bit appears; a shifting circuit for performing a bit shift of binary data to the most significant side by a value detected by the leading "1" detecting circuit; A first decimal double generation circuit for generating a double of decimal data, and a second generation of a quadruple of the decimal data by inputting an output of the first decimal double generation circuit.
, A third decimal double generation circuit for generating an octal multiple of decimal data by inputting the output of the second decimal double generation circuit,...
By inputting the output of the (i-2) th decimal double generation circuit that generates the "2 (i-2) power" multiple of the decimal data, the decimal data "2 (i-1)" is input. (I-1) th decimal double generation circuit for generating a "multiplier" multiple, the first decimal double generation circuit, the second decimal double generation circuit, and the third decimal double generation circuit Circuit,..., 10 generated by the (i−1) th decimal double generation circuit
A decimal data selector for selecting any one of a double, a quadruple, an eight,..., A “2 (i−1) power” multiple of the decimal data based on a detection value of the leading “1” detection circuit; And a binary-decimal conversion circuit. 4. A binary-decimal conversion circuit for inputting i-bit binary data to be converted and converting the binary data into decimal data, comprising: (a) the i-bit binary data to be converted; A binary data register for holding temporary binary data during the conversion process; and (b) a binary data register output from the binary data register until the first "1" bit appears from the most significant bit of the binary data. A leading "1" detecting circuit for detecting the number of "0" bits, and (c) data obtained by bit-shifting the output of the binary data register to the most significant side by the number of detection values of the leading "1" detecting circuit. And (d) the binary data to be converted,
Selecting any one of the data after the second bit, excluding the most significant bit, from the output data of the shift circuit;
A binary data selector for storing data in a decimal data register; and (e) storing temporary decimal data during conversion processing and decimal data of a final conversion result, and the least significant bit of the output of the decimal data selector. A decimal data register that outputs data obtained by replacing the most significant bit of data shifted to the most significant side by the shift circuit by the value detected by the leading “1” detection circuit; and (f) the decimal data register. A first decimal double number generating circuit for generating a double number of decimal data from the output of
The input of the output of the decimal double generation circuit of
A second decimal double number generating circuit for generating a quadruple number of the decimal data, and a third decimal number generating an octal number of the decimal data by inputting the output of the second decimal double number generating circuit. Binary double number generation circuit,... Of decimal data "2
The (i-2) th power of a (2−1) th power of the decimal data is generated by inputting the output of the (i-2) th decimal double generation circuit that generates the (i-2) th power. (I-1)
(G) the first decimal 2
Multiple generation circuit, second decimal double generation circuit, third 1
0-ary double generation circuit,..., A double of the decimal data generated by the (i-1) th decimal double generation circuit,
And a decimal data selector for selecting any one of quadruple, octal,..., And “2 (i−1) power” by the detection value of the leading “1” detection circuit. To decimal conversion circuit. 5. A binary-decimal conversion circuit for inputting i-bit binary data to be converted and converting the binary data into decimal data, wherein a specific number n bits smaller than the i-bit of the binary data Reading "1" for detecting the number of "0" bits from the most significant bit until the first "1" bit appears
A detection circuit; a shift circuit for shifting the binary data from the minimum 0 bits to the maximum n bits to the most significant bit according to the detection value of the leading "1" detection circuit; Multiple, ..., "2
(N + 1) -numbered double generation circuits each generating a (n + 1) -th power of multiples, and double, quadruple, and quadruple numbers of the decimal data generated by the (n + 1) decimal double-number generation circuits 8 multiples, ...
And a decimal data selector for selecting one of the multiples of "2 to the power of (n + 1)" based on the detection value of the leading "1" detection circuit. 6. A binary-decimal conversion circuit for inputting i-bit binary data to be converted and converting it into decimal data, comprising: (a) the i-bit binary data to be converted; A binary data register for holding temporary binary data during conversion processing; and (b) a specific number n bits continuous from the most significant bit smaller than the i bit of the binary data output from the binary data register , A leading "1" detecting circuit for detecting the number of "0" bits until the first "1" bit appears, and (c) the binary number corresponding to the number of detection values of the leading "1" detecting circuit. A shift circuit that outputs data obtained by bit-shifting the output of the data register to the most significant side; (d) the binary data to be converted, and the second and subsequent bits obtained by removing the most significant bit from the output data of the shift circuit Select one of the data from
A binary data selector for storing data in the binary data register; and (e) storing temporary decimal data during conversion processing and decimal data of a final conversion result, and A decimal data register for outputting data obtained by replacing one bit with the most significant bit of data shifted to the most significant side by the shift circuit by the value detected by the leading “1” detection circuit;
(F) By connecting each of them in series, the output of the decimal data register is converted to a decimal double number, a decimal quadruple number, a decimal octal number,..., Decimal "2 (n + 1)
(N + 1) decimal doubling generators for generating and outputting a power multiplier; and (g) doubling, quadrupling, and the like of the decimal data generated by the (n + 1) decimal doubling generators.
A decimal data selector for selecting any one of octal multiples,..., "2 to the power of (n + 1)", based on a detection value of the leading "1" detection circuit. Conversion circuit.