JP3226788B2 - Power converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter for converting direct current to alternating current.

[0002]

2. Description of the Related Art FIG. 16 is a diagram showing a main circuit configuration of an NPC inverter, in which switching elements 100U, 101U, 100V, 101
V, 100W, 101W, 100X, 101X, 100Y, 101
Y, 100Z, 101Z, and diodes 102U, 103U, 102V, 103V,
102W, 103W, 102X, 103X, 102Y, 103Y, 1
02Z, 103Z and wheeling diode 104U, 104
V, 104W, 104X, 104Y, 104Z,
Current detectors 105U and 105 for detecting V and W phase output currents
V, 105W.

The power supply V _dc on the DC side is divided into V _dc / 2,
The midpoint potential is set to zero potential. FIG. 17 is a block diagram of a control device of the NPC inverter. The control device of FIG.
Current detector 105U, 105V, three phase AC signal I _U detected by the 105W, I _V, I _W to the two-phase AC signals I _a, the 3-phase two-phase conversion circuit 20 for converting the I _b, the frequency f ₁ in the phase signal generation circuit 21 for generating a phase signal theta ₁ which rotates, two-phase alternating current signal I _a from the 3-phase two-phase conversion circuit 20 based on the phase signal theta ₁ from the phase signal generating circuit 21, stationary coordinate system converts the I _b rotating coordinate system of the current signal I _d, the I _q - the rotating coordinate system conversion circuit 22, the stationary coordinate system - current signal from the rotating coordinate system conversion circuit 22 I _d, and I _q Current command value I _d
^*, I _q ^* and the voltage command signal based on V _d ^*, V _q ^* and the current control circuit 23 for calculating a voltage command signal V _d from the current control circuit 23 ^*, V _q ^* the amplitude command signal V _r ^* and the rotating coordinate system is converted into a phase angle theta ₃ - a polar coordinate system conversion circuit 24, the rotating coordinate system - amplitude command signal V _r ^* and the voltage command signal based on the phase angle theta ₃ from polar coordinate system conversion circuit 24 V _U ^* , V _V
^* , Static coordinate system conversion circuit 25 for calculating V _W ^*
A triangular wave generating circuit 26 for generating triangular waves V _TR1 and V _TR2 having a constant frequency; and a polar coordinate system to stationary coordinate system conversion circuit.
Voltage designating signal V _U ^* from ^{_{25, V V *, V W}} * and the gate signals G _U1 as compared to switching elements of the inverter and a triangular wave V _TR1, V _TR2 from the triangular wave generation circuit 26, G _X1, G
_{U2, G X2, G V1,} G Y1, G V2, G Y2, G W1, G z1,
And a gate pulse generation circuit 27 for generating G _W2 and G _z2 .

Next, each component of the control device shown in FIG. 17 will be described in detail. The three-phase to two-phase conversion circuit 20 is a current detector
Three-phase AC signals I _U , I _U detected at 12u, 12v, 12w
_V and I _W are converted into two-phase AC signals I _a and I _b of orthogonal ab coordinates by the following calculation. However, the a-axis is the U-phase direction, and the b-axis is an axis delayed by 90 ° from the a-axis.

[0005]

(Equation 1) The phase signal generation circuit 21 obtains the phase signal θ ₁ rotating at the frequency f ₁ by the following calculation.

[0006]

The stationary coordinate system / rotational coordinate system conversion circuit 22 converts the two-phase AC signals I _a and I _b from the three-phase / two-phase conversion circuit 20 from the phase signal generation circuit 21 to θ ₁ = ∫2πf ₁ dt. current signal I _d of the rotating coordinate system performs the following operation based on the phase signal theta _1, is converted into I _q.

[0007]

(Equation 3) The current control circuit 23 includes a stationary coordinate system-rotating coordinate system conversion circuit 22.
Current signals I _d , I _{q from the first} and second current command values I _d ^* , I _q
^The following calculations are performed based on the ^* and the voltage command signals V _d ^* , V
_{Find q} ^* .

[0008]

(Equation 4) Rotating coordinate system - polar coordinate system conversion circuit 24, ^* the voltage command signal V _d from the current control circuit 23, the amplitude command signal V _r ^* and the phase angle theta ₃ of the polar coordinate system perform the following operations on the basis of V _q ^* Convert.

[0009]

(Equation 5)

The polar coordinate system-stationary coordinate system conversion circuit 25 receives the amplitude command signal _Vr ^* from the rotation coordinate system-polar coordinate system conversion circuit 24 ^.
The following calculation is performed on the basis of and the phase angle θ ₃ to obtain voltage command signals _VU ^* , _VV ^* , _VW ^* .

[0011]

(Equation 6) Triangular wave generating circuit 26 periodically generates the triangular wave V _TR of T ₁ by the following operations.

[0012]

(Equation 7)

The gate pulse generation circuit 27 is provided with voltage command signals V _U ^* , V _V ^* , from the polar coordinate system-stationary coordinate system conversion circuit 25.
V _W ^* and the triangular waves V _TR1 and V _TR2 from the triangular wave generating circuit 26
And the gate signals G _U1 , G
_X1 , _GU2 , _GX2 , _GV1 , _GY1 , _GV2 , _GY2 , _GW1 ,
G _z1 , G _W2 and G _z2 are generated.

For example, the U phase is as shown in FIG. V _U ^* G _U1 = ON when _{≧ V TR1, G X1 = OFF} V U * <G U1 = OFF, G X1 = ON V U * G U2 = ON when ≧ V _TR2 when the V _TR1, G _X2 = When OFF V _U ^* <V _{TR2 GU 2} = OFF, G _X2 = ON The same applies to the V-phase and W-phase.

[0015]

An NPC inverter is shown in FIG.
As shown in FIG. 18, there are three voltage states of positive voltage, zero voltage, and negative voltage. The NPC inverter has a period in which the neutral point of the DC power supply is connected to the load via a diode and a switching element. During the period, current flows to the neutral point of the DC power supply.

FIG. 19 is an operation waveform diagram of the NPC inverter, where V _U is the output phase voltage, I _U is the output current, I _c1 is the current flowing to the neutral point of the DC capacitor, and V _dc1 is the current of the positive side DC capacitor. Voltage, V _dc2 is the voltage of the negative DC capacitor,
V _dc is a DC voltage.

As can be seen from FIG. 19, although the DC voltage V _dc is constant, the voltages V _dc1 and V _dc2 of the positive and negative DC capacitors are three times lower than the output frequency due to the neutral point current.
It fluctuates at twice the frequency.

Since the magnitude of the fluctuation of the capacitor voltage depends on the capacitance of the capacitor, conventionally, a large-capacity capacitor must be used in order to suppress the fluctuation of the capacitor voltage, and the apparatus has been increased in size.

In the case where the GTO is used as the switching element, there is a restriction that once the GTO is turned on, it must be kept on for a certain period of time due to the characteristics of the GTO. In other words, it is necessary to keep a necessary minimum ON period (ON pulse width), and it is not possible to output a pulse narrower than that.

For example, in FIG. 18, when the voltage command signal is large and approaches the upper and lower vertices of the triangular wave, the on-pulse width becomes smaller than the minimum on-pulse width. In the case of the GTO, the minimum on-pulse width may reach about 200 μs. In order to avoid this, the upper limit of the modulation factor is about 0.8 when the frequency of the triangular wave is set to 500 Hz.

Assuming that the upper limit of the modulation factor is about 0.8, the peak value of the output line voltage of the power converter is (3 ^1/2/2 ) × γ ×
V _dc (where γ: degree of modulation, V _dc : DC voltage). That is, the upper limit of the peak value of the output line voltage is about 0.69 times the DC voltage. In other words, in order to obtain the required peak value of the output line voltage, a DC voltage as high as about 1.45 times the peak value is required.

In order to cope with a high DC voltage, the withstand voltage of the switching element is limited, so that it is necessary to connect a plurality of switching elements in series, and the number of used switching elements is directly reflected in the price. There is a problem that the conversion device becomes expensive. Accordingly, it is an object of the present invention to provide a control device for a power converter in which a change in neutral point potential is small and a line voltage can be obtained efficiently.

[0023]

[0024]

In the power converter according to the first aspect of the present invention, the output phase of the power converter is calculated based on the integrated value of the difference between the voltage command signal and the output phase voltage of the immediately preceding power converter. By obtaining and controlling the voltage, the output phase voltage can be made multi-level, the neutral point fluctuation can be reduced, and the modulation degree can be made approximately one.

In the power converter according to a second aspect of the present invention, the 60 ° period before and after the maximum of one phase of the first voltage command signal is fixed to the maximum value of the positive and negative, and the other two phases are fixed. By obtaining and controlling the output phase voltage of the power converter based on the integral value of the difference between the second voltage command signal converted so that the line voltage becomes a sine wave and the output phase voltage of the power converter immediately before, , The output phase voltage can be multi-level, the neutral point fluctuation can be reduced, the modulation factor can be made almost 1, and the voltage command is fixed to 1 /
No switching is performed during the period 3, power loss and heat generation can be reduced, and the peak value of the output line voltage can be set to γVdc.

In the power converter according to a third aspect of the present invention, the second voltage command signal obtained by correcting the first voltage command signal with a bias component that changes at a frequency three times the frequency of the power converter is used. By obtaining and controlling the phase voltage of the power converter based on the integrated value of the difference from the output phase voltage of the power converter, the output phase voltage can be multi-level and the neutral point fluctuation can be reduced. Further, the degree of modulation can be set to approximately 1, and the peak value of the output line voltage can be set to γVdc.

In the power converter according to the fourth aspect of the present invention, the first and second power converters are three-phase bridge inverters, so that the output phase voltage can be set to three levels. Gender point fluctuation can be reduced.

In the power converter according to claim 5 of the present invention, the first and second power converters are NPC inverters, so that the output phase voltage can be set to five levels, and the neutral point Fluctuations can be reduced. In the power converter according to claim 6 of the present invention, the current flowing through the reactor can be obtained from the voltage.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a main circuit configuration of a first embodiment of the present invention, in which a switching element 120u,
120v, 120w, 120x, 120y, 120z and diodes 121u, 121v,
A first three-phase bridge inverter 110 composed of 121w, 121x, 121y, and 121z, and a switching element 122u,
122v, 122w, 122x, 122y, 122z and the diodes 123u, 123v,
A second three-phase bridge inverter 111 composed of 123w, 123x, 123y, and 123z, and a coupling reactor 124 for connecting the respective phases of the first and second three-phase bridge inverters 124
u, 124v, 124w and a DC capacitor connected to the DC side of the first and second three-phase bridge inverters 110, 111
The DC reactor 125 includes a DC power supply _Vdc for supplying power to the DC capacitor 125, and a load is connected to a neutral point of the coupling reactor.

FIG. 2 is a block diagram of a control device of the circuit shown in FIG. The control device shown in FIG.
Three-phase AC signal I detected at 105u, 105v, 105w
_U , I _V , I _W are converted into two-phase AC signals I _a , I _b 3
Phase and two-phase conversion circuit 20, a phase signal generating circuit 21 for generating a phase signal theta ₁ which rotates at a frequency f _1, the three-phase to two-phase phase signal theta ₁ from the phase signal generating circuit 21 based on two-phase AC signals I _a from the conversion circuit 20, the stationary coordinate system converts the I _b rotating coordinate system of the current signal I _d, the I _q - the rotating coordinate system conversion circuit 22, the stationary coordinate system - rotating coordinate system transformation Circuit 22
Current signals I _d , I _q and current command values I _d ^* , I _q ^*
A current control circuit 23 that calculates voltage command signals V _d ^* and V _q ^{* based} on the above, and a voltage command signal V
_d ^*, V _q ^* the rotating coordinate system is converted to an amplitude command signal V _r ^* and the phase angle theta ₃ - a polar coordinate system conversion circuit 24, the rotating coordinate system - amplitude command signal V _r from the polar coordinate system conversion circuit 24 ^* a voltage command signal V _U ^* on the basis of the phase angle theta ^3, V _V ^*, the polar coordinate system calculates a V _W ^* - a stationary coordinate system conversion circuit 25, the polar coordinate system - voltage command from stationary coordinate system conversion circuit 25 Signal V _{U
^{*, V V *, V W}} * and feedback the inverter output voltage _{E U ', E V',} E W ' inverter output voltage based on the integrated value of the difference between E _U, E _V, the error to obtain the E _W Integral following PWM control circuit 30 and coupling reactor 124
Integrators 47u, 47 for integrating reactor voltages (cross currents) I _UC , I _VC , I _wc by integrating voltages across u, 124v, 124w.
v, 47w, comparators 31u, 31v, 31w for comparing reactor currents I _UC , I _VC , I _WC from integrators 47u, 47v, 47w with predetermined positive and negative values, type PWM inverter output voltage E _U from the control circuit 30, E
_V , E _W and the outputs J _U1 , J _{U of the} comparators 31 u, 31 v, 31 w
Gate signals G _U1 , G _V1 , G _W1 , G _X1 , G _Y1 , G _Z1 , G _U2 , G _U of the switching element of the power converter based on _{V 1} , J _W1.
And a gate pulse generating circuit 32 for generating _V2 , _GW2 , _GX2 , _GY2 , and _GZ2 . Here, the same components as those in the related art are denoted by the same reference numerals, and description thereof is omitted.

First, the error integral tracking type PWM control circuit 30 will be described with reference to FIG. Here, only the U phase is described, but the V phase and the W phase have the same configuration.
The error integration tracking type PWM control circuit 30 includes a comparator 35 for comparing the voltage command signal from the polar coordinate system-stationary coordinate system conversion circuit 25 with zero, and a voltage command signal from the polar coordinate system-stationary coordinate system conversion circuit 25. An integrating circuit 36 for integrating the difference between the feedback and the inverter output voltage, a comparator 37 for comparing the output from the integrating circuit 36 with a positive predetermined value, and an output from the integrating circuit 36 and a negative predetermined value. And an output voltage setting circuit 39 for obtaining an inverter output voltage based on the sum of the output of the comparator 37 and the output of the comparator 38 and the output of the comparator 35.
Consists of The comparator 35 compares the voltage command value _VU ^* from the polar coordinate system-stationary coordinate system conversion circuit 25 with zero, and outputs _V1U .

[0032]

(Equation 8) Integrating circuit 36, the polar coordinate system - by integrating the difference between the voltage command signal V _U ^* and the feedback to inverter output voltage E _U 'from the stationary coordinate system conversion circuit 25 obtains the integral amount S _U.

[0033]

S _u = ∫ (V _U ^* −E _U ′) dt The comparator 37 compares the integration amount S _U from the integration circuit 36 with a predetermined positive value A, and if S _U > A, +1. And S _U ≦ A
If so, 0 is output.

The comparator 38 calculates the integration amount S _U from the integration circuit 36.
Is compared with a predetermined negative value -A. If S _U <-A, -1 is output, and if S _U ≥-A, 0 is output. The output voltage setting circuit 39 calculates the sum N _U of the output of the comparator 37 and the output of the comparator 38.
_{Is calculated} based on the following equation.

When N _U = + 1, V _2U = 0, when N _U = 0, V _2U outputs the previously output value, and when N _U = -1, V _2U = −V _dc / 2, and the output voltage setting circuit 39, adds the V _2U determined to V _1U the previous from the comparator 35 is output as the inverter output voltage E _U. The integrator 47u integrates the voltage E _UC across the coupling reactor 124u to obtain a reactor current (cross current) I _UC .

[0036]

(Equation 10) Comparator 31u compares reactor current (cross current) I _UC flowing through coupling reactor 124u with predetermined positive and negative values ± B, which is the allowable value of reactor cross current, and outputs output J _U1 .

When I _UC > + B, J _U1 = 0 When I _UC <−B, J _U1 = 1−B ≦ I _UC ≦ + B, J _U1 is the previously output value. gate signal G _U1, G _U2 shown in FIG. 4 based on the output J _U1 from the comparator 31u inverter output voltage E _U from the error integrator tracking type PWM control circuit 30,
G _X1 and G _X2 are output.

FIG. 5 is a diagram showing the operation waveforms described above. In the error integral tracking type PWM circuit 30, the inverter output voltage is obtained based on the integral value of the difference between the voltage command signal and the fed-back inverter output voltage. Therefore, when the voltage command signal is large, the inverter output voltage becomes + V _dc / 2. Since the difference from the voltage command signal sometimes becomes small, the time required for the integrated value to reach the negative allowable value becomes longer, and the switching frequency decreases.

Therefore, as compared with the conventional triangular wave comparison PWM control, even if the voltage command signal is large, it is less likely to be restricted by the minimum on-pulse width. However, if the voltage command signal is very large, the pulse width t narrower than the minimum on-pulse width t _LMT
1 may be output. In such a case, the narrow pulse width t _{1 as} indicated is not output, and the minimum on-pulse width t 1
It is conceivable to output a fixed pulse to _LMT ,
Then, the voltage command signal is equivalently distorted, and as a result, the output voltage waveform is distorted.

Therefore, in such a case, t _LMT −t
_In the period of ₁ , the integration of the difference is continued beyond the allowable value and t
_{When it reaches LMT} , the inverter output voltage is changed. This operation will be described with reference to FIG.

The integral value S _U of the difference between the voltage command signal V _U ^* and the fed-back inverter output voltage E _U ′ is
At time t ₁ , it reaches the positive allowable value A. However, since the minimum on-pulse width t _LMT is not ensured, the integration is continued without changing the inverter output voltage.

At time t _LMT , the minimum on-pulse width t _LMT is ensured, so that the inverter output voltage E
_U outputs + V _dc / 2. Next to the integrated value S _U of the difference reaches the negative tolerance -A inverter output voltage E _U outputs a + V _dc / 2.

As described above, the inverter output voltage is not switched even if the allowable value is _exceeded , the integration is continued until the minimum on-pulse width t _LMT is secured, and the inverter output voltage is switched when the minimum on-pulse width is secured. ,
Since the minimum on-pulse width can be ensured and the time required to reach the next allowable value becomes longer by the amount exceeding the allowable value, the waveform is not distorted even if the pulse width is set to t _LMT .

As described above, in the power converter according to the first embodiment of the present invention, the output phase voltage is ± V _dc / 2,0
By performing switching so as to limit the reactor current flowing through the coupling reactor, the neutral point current does not flow and the neutral point potential does not fluctuate.

In addition, the limitation on the minimum on-pulse width of the switching element can be avoided, the degree of modulation of the power converter can be set to approximately 1.0, and the output voltage of the power converter can be increased.

Further, when the voltage command is large, the modulation frequency is lowered, and the number of times of switching can be reduced, so that power loss and heat generation due to switching can be reduced.

Next, a second embodiment of the present invention will be described. FIG. 7 shows a control device of the power converter according to the second embodiment, which is different from the first embodiment in that a voltage command conversion circuit 41 is added and the positive / negative maximum of one of three phases is obtained. The other two phases are fixed so that a sinusoidal line voltage can be obtained even if one phase is fixed.

In the control device shown in FIG. 6, the current detector 1
05u, 105v, 105w detected three-phase AC signal I _U ,
I _V, 3-phase for converting the I _W biphasic AC signal I _a, the I _b -
Two-phase conversion circuit 20, the phase signal theta ₁ which rotates at a frequency f ₁
And the two-phase AC signals I _a and I _b from the three-phase to two-phase conversion circuit 20 based on the phase signal θ ₁ from the phase signal generation circuit 21 based on the rotation coordinate system. current signal I _d, the stationary coordinate system is converted into I _q - the rotating coordinate system conversion circuit 22, the stationary coordinate system - current signal I _d from the rotating coordinate system conversion circuit 22, I _q and the current command value I _d ^*, I _q ^* and the voltage command signal based on V _d ^*, a current control circuit 23 for calculating a V _q ^*, the voltage command signal V _d from the current control circuit 23
^* , V _q ^* to the amplitude command signal V _r ^* and the phase angle θ ₃ , a rotation coordinate system-polar coordinate system conversion circuit 24, and the amplitude command signal V _r ^* from the rotation coordinate system-polar coordinate system conversion circuit 24 voltage command signal based on the phase angle ^{_{θ 3 V U *, V V}} *, the polar coordinate system calculates a V _W ^* - a stationary coordinate system conversion circuit 25, the polar coordinate system - the voltage command signal from the stationary coordinate system conversion circuit 25 V _U ^* ,
Voltage command signals V _U2 ^* , V _V2 ^* , converted so that the line voltage of the power converter becomes positive by the other two phases even if one of V _V ^* and V _W ^* is fixed. a voltage command conversion circuit 41 to output a V _W2 ^*, the voltage command signal V _U2 ^* from the voltage command conversion circuit ^{_{41, V V2 *, V W2}} * and feedback the inverter output voltage _{E U ', E V',} E inverter output voltage based on the integrated value of the difference between _{W 'E U, E V,} E W
, And comparators 31u, 31v, 31w for comparing reactor currents I _UC , I _VC , I _WC flowing through coupling reactors 124u, 124v, 124w with predetermined positive and negative values. When the inverter output voltage E _U from the error integrator tracking type PWM control circuit 30, E _V, E _W and the comparator 31u, 31v, 31w of the output J _U1, J _V1, J _W1 and the power converter based on Gate signals G _U1 , G _V1 , G _W1 , G _X1 , G _Y1 , G _Z1 , G _U2 , G _V2 , G
It comprises a pulse generation circuit 32 for generating _W2 , _GX2 , _GY2 , _GZ2 . Here, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

FIG. 8 is a waveform diagram showing the operation of the voltage command conversion circuit 41. 8 (a) is the polar coordinate system - voltage command signal V _U from stationary coordinate system conversion circuit 25 ^*, V _V ^*, a V _W ^*.

As shown in FIG. 8B, the voltage command conversion circuit 41 converts the voltage command signals _VU ^* , _VV ^* , _VW ^* to + V _dc / 2 during the 60 ° period before and after they take positive peak values. It is fixed, and is fixed to _-Vdc / 2 during the 60-degree period before and after the negative peak value is obtained.

In the other two phases which are not fixed, the line voltage of the power converter is a sine wave, and the voltage command signals V _U ^* , V _V ^* ,
V _W voltage command signal V _U2 ^* to obtain 2/3 ^1/2 times the line voltage obtained at ^*, V _V2 ^*, is converted to V _W2 ^*. For example, U
When the phase is fixed at + V _dc / 2, the following conversion is performed.

[0052]

[Equation 11]

When the V-phase and the W-phase are fixed, the same conversion is performed as shown in FIG. 8C.
The voltage command signals V _U2 ^* , V thus converted
_By controlling using _V2 ^* and _VW2 ^* , in the power converter according to the second embodiment, the output phase voltage is ± _Vdc /
The switching can be performed so as to limit the reactor current flowing through the coupling reactor, so that the neutral point current does not flow and the neutral point potential does not fluctuate.

Further, it is possible to avoid the limitation of the minimum on-pulse width of the switching element, to make the modulation degree of the power converter almost 1.0, and to set the peak value of the output line voltage of the power converter to γV _dc (where γ is the degree of modulation), the output voltage of the power converter can be increased.

Further, when the voltage command is large, the modulation frequency is lowered, and the number of times of switching can be reduced, so that power loss and heat generation accompanying switching can be reduced.

Further, since the voltage command signal is fixed to positive or negative for one third of the entire period, no switching is performed during this period, and power loss and heat generation accompanying the switching can be reduced. .

Next, a third embodiment of the present invention will be described. FIG. 9 shows a control device for a power converter according to the third embodiment. The difference from the first embodiment is that a bias operation circuit is used instead of the polar coordinate system-stationary coordinate system conversion circuit 25.
45 and a polar coordinate system-stationary coordinate system conversion circuit 46.

In the control device shown in FIG. 9, the current detector 1
05u, 105v, 105w detected three-phase AC signal I _U ,
I _V, 3-phase for converting the I _W biphasic AC signal I _a, the I _b -
Two-phase conversion circuit 20, the phase signal theta ₁ which rotates at a frequency f ₁
And the two-phase AC signals I _a and I _b from the three-phase to two-phase conversion circuit 20 based on the phase signal θ ₁ from the phase signal generation circuit 21 based on the rotation coordinate system. current signal I _d, the stationary coordinate system is converted into I _q - the rotating coordinate system conversion circuit 22, the stationary coordinate system - current signal I _d from the rotating coordinate system conversion circuit 22, I _q and the current command value I _d ^*, I _q ^* and the voltage command signal based on V _d ^*, a current control circuit 23 for calculating a V _q ^*, the voltage command signal V _d from the current control circuit 23
^* , V _q ^* to the amplitude command signal V _r ^* and the phase angle θ ₃ , a rotation coordinate system-polar coordinate system conversion circuit 24, and a phase angle θ ₃ from the rotation coordinate system-polar coordinate system conversion circuit 24. A bias operation circuit 45 for _{obtaining a} bias component V _bias ; an amplitude command signal V _r ^* , a phase angle θ ₃ from the rotational coordinate system-polar coordinate system conversion circuit 24; and a bias component V from the bias operation circuit 45.
voltage command signal based on the ^{_{bias V U2 *, V V2 *}} , polar coordinate system calculates the V _W2 ^* - a stationary coordinate system conversion circuit 46, the polar coordinate system - voltage command signal V _U2 from stationary coordinate system conversion circuit 46 ^* ,
V _V2 ^*, V _W2 ^* and feedback the inverter output voltage E _U ', E _V', error integrator follow to obtain E _W 'inverter output voltage based on the integrated value of the difference between E _U, E _V, the E _W Type PWM control circuit 30 and coupling reactor 124u, 1
Integrators 47u, 47v, and 47w that obtain reactor currents I _UC , I _VC , and I _WC by integrating voltages between both ends of the 24 v and 124 w;
The comparators 31u, 31v, 31w for comparing the reactor currents I _UC , I _VC , I _WC from the integrators 47u, 47v, 47w with predetermined positive and negative values, and the error integration tracking type PWM control circuit 30 inverter output voltage from the E _U, E _V, E _W
And outputs J _U1 , J _V1 and J _{V of} the comparators 31u, 31v and 31w.
_{On the} basis of _W1 , the gate signals G _U1 , G _V1 , G _W1 , G _X1 , G _Y1 , G _Z1 , G _U2 , G _V2 , G of the switching elements of the power converter.
It comprises a pulse generation circuit 32 for generating _W2 , _GX2 , _GY2 , _GZ2 . Here, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

FIG. 10 is a waveform diagram showing the operation of the bias operation circuit 45 and the polar coordinate-stationary coordinate system conversion circuit 46. The bias calculation circuit 45 receives the phase angle θ ₃ from the rotation coordinate system-polar coordinate system conversion circuit 24 as input, and obtains a bias component V _bias by the following calculation.

[0060]

(Equation 12)

In this manner, the bias component V having a 60 ° cycle
_Bias is found. Polar coordinate system - stationary coordinate system conversion circuit 46, the rotating coordinate system - amplitude command signal V _r from the polar coordinate system conversion circuit 24
^{With *} , the phase angle θ _3, and the bias component V _bias from the bias calculation circuit 45 as inputs, voltage command signals V _U2 ^* , V _V2 ^* , V _W2 ^* are obtained by the following calculation.

[0062]

(Equation 13) The integrator 47u obtains a voltage E _UC between both ends of the supply reactor 124u.

[0063]

[Equation 14] Similarly, the integrators 47v and 47w provide a reactor current (cross current).
_Find I _VC and I _WC . By controlling using the voltage command signals V _U2 ^* , V _V2 ^* , V _W2 ^* converted in this way, in the power converter according to the second embodiment, the output phase voltage is ± V _dc / The switching can be performed so as to limit the reactor current flowing through the coupling reactor, so that the neutral point current does not flow and the neutral point potential does not fluctuate.

Further, the limitation on the minimum on-pulse width of the switching element can be avoided, the modulation degree of the power converter can be set to approximately 1.0, and the peak value of the output line voltage of the power converter is set to γV _dc (where γ is the degree of modulation), the output voltage of the power converter can be increased.

Further, when the voltage command is large, the modulation frequency is lowered, and the number of times of switching can be reduced, so that power loss and heat generation accompanying switching can be reduced.

Next, a fourth embodiment of the present invention will be described. FIG. 11 shows a main circuit configuration of a fourth embodiment of the present invention, in which switching elements 151u, 152u, 151v,
152v, 151w, 152w, 151x, 152x, 151y, 1
52y, 151z, 152z and diodes 153u, 154u, 153v, 154v,
153w, 154w, 153x, 154x, 153y, 154y, 1
53z, 154z and wheeling diodes 155u, 155
v, 155w, 155x, 155y, 155z, and a switching element 161u, 1
62u, 161v, 162v, 161w, 162w, 161x, 162
x, 161y, 162y, 161z, 162z and diodes 163u, 164u, 163 connected in anti-parallel to the switching elements.
v, 164v, 163w, 164w, 163x, 164x, 163
y, 164y, 163z, 164z, a second NPC inverter 160 comprising wheeling diodes 165u, 165v, 165w, 165x, 165y, 165z, and a connection for connecting the respective phases of the first and second NPC inverters. Reactor
124u, 124v, 124w, and DC capacitors 125P, 125P connected to the DC side of the first and second NPC inverters.
N, and a DC power supply for supplying power to the DC capacitors 125P and 125N. A load is connected to the neutral point of the coupling reactor.

FIG. 12 is a block diagram of a control device of the circuit shown in FIG. In the control device shown in FIG. 12, the three-phase AC signal I detected by the current detectors 105u, 105v, and 105w is used.
_U , I _V , I _W are converted into two-phase AC signals I _a , I _b 3
Phase and two-phase conversion circuit 20, a phase signal generating circuit 21 for generating a phase signal theta ₁ which rotates at a frequency f _1, the three-phase to two-phase phase signal theta ₁ from the phase signal generating circuit 21 based on two-phase AC signals I _a from the conversion circuit 20, the stationary coordinate system converts the I _b current signal I _d of the rotary inverter, the I _q - the rotating coordinate system conversion circuit 22, the stationary coordinate system - rotating coordinate system conversion circuit current signal I _d from 22, I _q and the current command value I _d ^*, I
_q ^* and the voltage based on the command signal V _d ^*, a current control circuit 23 for calculating a V _q ^*, the voltage command signal V _d ^* from the current control circuit 23, a V _q ^* and amplitude command signal V _r ^* A rotation coordinate system-polar coordinate system conversion circuit 24 for converting the phase angle θ ₃ into an angle, and an amplitude command signal V _r ^* from the rotation coordinate system-polar coordinate system conversion circuit 24
Voltage command signal based on the phase angle theta ₃ and ^{_{V U *, V V *,}} V W
^* To calculate the polar coordinate system-stationary coordinate system conversion circuit 25 and the voltage command signal V from the polar coordinate system-stationary coordinate system conversion circuit 25
^{_{U *, V V *, V}} W * and feedback the inverter output voltage E _U ', E _V', obtaining E _W 'inverter output voltage based on the integrated value of the difference between E _U, E _V, the E _W The error integral tracking type PWM control circuit 50 and the coupling reactor 124
u, 124v, 124w, reactor current I _UC ,
Comparator 31 for comparing I _VC and I _WC with predetermined positive and negative values
u, 31v, 31w and the error integral tracking type PWM control circuit
Inverter output voltage E _U from 50, E _V, E _W and the comparator 31u, 31v, output of _{31w J U1, J V1, J} W1 and the gate signal of the switching elements of the power converter based on G _U1,
G _V1 , G _W1 , G _X1 , G _Y1 , G _Z1 , G _U2 , G _V2 , G _W2 , G
_And a gate pulse generating circuit 52 for generating _X2 , _GY2 , and _GZ2 . Here, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

The error integral tracking type PWM control circuit 50 will be described with reference to FIG. Here, only the U phase is shown, but the V phase and the W phase have the same configuration. The error integration tracking type PWM control circuit 50 includes a comparator 52 for comparing the voltage command signal from the polar coordinate system-stationary coordinate system conversion circuit 25 with zero.
And an integration circuit 36 for integrating the difference between the voltage command signal from the polar coordinate system-stationary coordinate system conversion circuit 25 and the inverter output voltage fed back, and a comparison for comparing the output from the integration circuit 36 with a predetermined positive value. A comparator 37 for comparing the output from the integrating circuit 36 with a predetermined negative value; and an inverter based on the sum of the output of the comparator 37 and the output of the comparator 38 and the output of the comparator 52. And an output voltage setting circuit 53 for obtaining an output voltage. The comparator 52 compares the voltage command value _VU ^* from the polar coordinate system-stationary coordinate system conversion circuit 25 with 0 and ± _Vdc / 4 and outputs _V1U .

[0069]

(Equation 15)

The integrating circuit 36 integrates the difference between the voltage command signal V _U ^* from the polar coordinate system-stationary coordinate system converting circuit 25 and the fed-back inverter output voltage EU 'to integrate the difference S.
_Ask for _U.

[0071]

S _U = １６ (V _U ^* −E _U ′) dt The comparator 37 compares the integration amount S _U from the integration circuit 36 with a predetermined positive value A. If S _U > A, +1 And S _U ≦ A
If so, 0 is output.

The comparator 38 calculates the integral S _U from the integrating circuit 36.
Is compared with a predetermined negative value -A. If S _U <-A, -1 is output, and if S _U ≥-A, 0 is output. First, the output voltage setting circuit 53 obtains V _2u based on the sum N _U of the output of the comparator 37 and the output of the comparator 38 as follows.

When N _U = + 1, V _2U = 0 When N _U = 0, V _2U is the previously output value when N _U = −1, V _2U = −V _dc / 4, and V _1U from the comparator 35 by adding the V _2U previously obtained and output as the inverter output voltage E _U.

The comparator 31u is connected to the coupling reactor 124u.
And outputs the reactor current I _UC are compared with the predetermined value ± B an allowable value of the lateral flow is positive and negative reactor output J _U1 flowing.

When I _UC > + B, J _U1 = 0 When I _UC <−B, J _U1 = 1 When −B ≦ I _UC ≤ + B, J _U1 is the previously output value. Based on the inverter output voltage from the PWM control circuit 50 and the output J _U1 from the comparator 31u, the gate signals G _U1 , G _U2 , G _X1 , G shown in FIG.
_X2 , _GU3 , _GU4 , _GX3 , and _GX4 are output.

In the fourth embodiment of the present invention, the output phase voltages can be set in five stages of ± V _dc / 2, ± V _dc / 4, 0, and the harmonics can be reduced. Further, it is possible to avoid the restriction on the minimum on-pulse width of the switching element, to make the degree of modulation of the power converter approximately 1.0, and to increase the output voltage of the power converter.

Further, when the voltage command is large, the modulation frequency is lowered, and the number of times of switching can be reduced, so that power loss and heat generation due to switching can be reduced.

Although not shown here, the voltage command conversion circuit and the bias operation circuit of the second and third embodiments may be applied to the fourth embodiment. Next, a fifth embodiment will be described.

FIG. 15 is a schematic diagram of a variable speed pumped storage power generation system. The variable speed pumped storage power generation system has a main transformer 15
1 is connected to the primary winding via a winding type induction generator 152
And first and second power converters 153 and 154 for supplying an exciting current to a secondary winding of the wound induction generator, and first and second power converters.
Reactors 155u, 155v, 155w for coupling the power converters 153 and 154, a DC capacitor 156 provided on the DC side of the first and second power converters, and a DC for supplying power to the DC capacitor 156. A power supply 157, a first phase detector 158 for detecting the phase on the primary side of the wound induction generator 152, and a second phase detector 159 for detecting the phase on the secondary side of the wound induction generator 152; , Winding type induction generator 152
Current detectors 160u, 160v, which detect the current on the secondary side of
160w, the difference between the output of the first phase detector 158 and the output of the second phase detector 159, and the current detectors 160u, 160v, 160
and a control circuit for controlling the first and second power converters based on the output of w.

By applying any of the first to fourth embodiments to the power converter constituting this variable speed pumped storage power generation system, a similar effect can be obtained in the present system. .

[0081]

[0082]

In the power converter according to the first aspect of the present invention, the output phase voltage of the power converter is obtained and controlled based on the integrated value of the difference between the voltage command signal and the output phase voltage of the immediately preceding power converter. By doing so, the output phase voltage can be made multi-level, the neutral point fluctuation can be reduced, and the modulation degree can be made approximately one.

In the power converter according to claim 2 of the present invention, the 60 ° period before and after the maximum of one phase of the first voltage command signal is fixed to the maximum value of the positive and negative, and the other two phases are fixed. By obtaining and controlling the output phase voltage of the power converter based on the integrated value of the difference between the second voltage command signal converted so that the line voltage becomes a sine wave and the output phase voltage of the power converter immediately before, , The output phase voltage can be multi-level, the neutral point fluctuation can be reduced, the modulation factor can be made almost 1, and the voltage command is fixed to 1 /
No switching is performed during the period 3, power loss and heat generation can be reduced, and the peak value of the output line voltage can be set to γVdc.

In the power converter according to a third aspect of the present invention, the second voltage command signal obtained by correcting the first voltage command signal with a bias component that changes at a frequency three times the frequency of the power converter is used. By obtaining and controlling the phase voltage of the power converter based on the integrated value of the difference from the output phase voltage of the power converter, the output phase voltage can be multi-level and the neutral point fluctuation can be reduced. Further, the degree of modulation can be set to approximately 1, and the peak value of the output line voltage can be set to γVdc.

In the power converter according to the fourth aspect of the present invention, the first and second power converters are three-phase bridge inverters, so that the output phase voltage can be set to three levels. Gender point fluctuation can be reduced.

In the power converter according to the fifth aspect of the present invention, the first and second power converters are NPC inverters, so that the output phase voltage can be set to five levels, and the neutral point Fluctuations can be reduced. In the power converter according to claim 6 of the present invention, the current flowing through the reactor can be obtained from the voltage.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a control device according to the first embodiment of the present invention.

FIG. 3 shows an error integration tracking type P according to the first embodiment of the present invention.
FIG. 3 is a block diagram of a WM control circuit.

FIG. 4 is a diagram illustrating a gate signal according to the first embodiment of the present invention.

FIG. 5 is an operation waveform diagram of gate signal generation according to the first embodiment of the present invention.

FIG. 6 is an operation waveform diagram for ensuring a minimum on-pulse width according to the first embodiment of the present invention.

FIG. 7 is a block diagram of a control device according to a second embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of the voltage command conversion circuit.

FIG. 9 is a block diagram of a control device according to a third embodiment of the present invention.

FIG. 10 is an explanatory diagram of the operation of the bias correction circuit.

FIG. 11 is a configuration diagram of a main circuit according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram of a control device according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram of an error integration tracking type PWM control circuit according to a fourth embodiment of the present invention.

FIG. 14 is a diagram illustrating a gate signal according to the fourth embodiment of the present invention.

FIG. 15 is a schematic diagram of a variable-speed pumped-storage power generation system.

FIG. 16 is a main circuit configuration diagram of an NPC inverter.

FIG. 17 is a block diagram of a control device of the NPC inverter.

FIG. 18 is a waveform chart of a triangular wave comparison.

FIG. 19 is an operation waveform diagram of the NPC inverter.

[Explanation of symbols]

 30, 50 ... error integration following PWM control circuit 31u, 31v, 31w ... comparator 32, 51 ... gate pulse generation circuit 41 ... voltage command conversion circuit 45 ... bias operation circuit 47u, 47v, 47w ... integrator 110, 111 ... Three-phase bridge inverter 124u, 124v, 124w ... coupled reactor 150, 160 ... NPC inverter

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 7/48 H02M 7/5387

Claims (6)

(57) [Claims] 1. A first power converter for converting DC to AC, a second power converter for converting DC to AC, and a first power converter provided on a DC side of the first and second power converters. A voltage source that supplies DC power to the first and second power converters, a reactor that connects the respective phases of the first and second power converters, and a load whose neutral point is connected to the reactor, Reactor current detecting means for detecting a flowing current, load current detecting means for detecting a load current, and the load current and the current command value;
A voltage command for calculating a voltage command signal based on the phase signal
Calculating means, the voltage command signal and the immediately preceding power converter
The output of the power converter based on the integrated value of the difference from the output phase voltage
An error integral tracking type PWM control means for obtaining a phase voltage;
Ratio of the current flowing through the reactor to a predetermined value
Comparison means for comparing the error integral following type PWM control means
Based on the output phase voltage from the stage and the output from the comparing means
Generating gate signals for the first and second power converters
Electric power characterized by comprising gate pulse generating means
Conversion device. 2. A first power converter for converting DC to AC.
And a second power converter for converting direct current to alternating current;
First and second power supplies provided on the DC side of the second power converter.
A voltage source for supplying DC power to the force converter;
Connect each phase of the power converter and connect the load to the neutral point
Reactor and the current flowing through the reactor
Reactor current detection means to output and load current detection
Load current detection means, the load current and the current command value,
A voltage for calculating a first voltage command signal based on the phase signal;
Pressure command calculating means, and a first command from the voltage command calculating means.
60 ° before and after the maximum of one phase positive and negative of the voltage command signal
The period is fixed to the maximum value of positive and negative, and the line voltage is sinusoidal for the other two phases.
For obtaining the second voltage command signal converted into a wave
Voltage command conversion means, and the second voltage command signal
Power conversion based on the integral of the difference from the output phase voltage of the power converter.
Integral Tracking PWM Control for Determining Output Phase Voltage of Converter
Means, a current flowing through the reactor and a preset
Comparing means for comparing with a predetermined value;
The output phase voltage from the PWM control means and the output
Gate signals of the first and second power converters based on the output
And gate pulse generating means for generating
Power converter. 3. A first power converter for converting DC to AC.
When the second power converter that converts direct current into alternating current, first and
First and second power supplies provided on the DC side of the second power converter.
A voltage source for supplying DC power to the force converter;
Connect each phase of the power converter and connect the load to the neutral point
Reactor and the current flowing through the reactor
Reactor current detection means to output and load current detection
Load current detection means, the load current and the current command value,
A voltage for calculating a first voltage command signal based on the phase signal;
Pressure command calculating means, and a first command from the voltage command calculating means.
At three times the frequency of the voltage command signal and the frequency of the power converter
A second voltage command signal based on the changing bias component;
Bias correction means, and a second voltage command signal.
Based on the integrated value of the difference from the output phase voltage of the previous power converter
Error integral tracking type PW for obtaining output phase voltage of power converter
M control means, current flowing in the reactor and preset
Comparing means for comparing with a predetermined value, and the error integration
Output phase voltage from tracking type PWM control means and said comparing means
Of the first and second power converters based on the output from the
Gate signal generating means for generating a gate signal.
A power converter characterized by the above-mentioned. 4. according to any one of claims 1 to 3
Power converter, the first and second power converters
Is a three-phase bridge inverter, characterized by power
Conversion device. 5. A according to any one of claims 1 to 3
Power converter, the first and second power converters
Is a neutral point clamp type inverter
Power converter. 6. claimed in any one of claims 1 to 5
In the power converter of the above, the reactor current detecting means
Is a voltage for detecting a voltage applied to both ends of the reactor.
Detecting means and integrating the output from the voltage detecting means and
Integrating means for calculating the current flowing through the actuator.
A power converter characterized by the above-mentioned.