JP3210420B2 - Multiplication circuit over integers - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit for integers, and more particularly to a circuit for multiplying a large number of digits using a multiplier of a small number of digits. The present invention provides an RSA cryptosystem that requires multiplication of a large number of digits (Shinichi Ikeno, Kenji Koyama:
“Modern Cryptography”, IEICE, 1986, Chapter 6)
It can be used for many integer operations including encryption techniques such as.

[0002]

2. Description of the Related Art In designing a gate array or a substrate, a multiplier on an integer having a small number of digits can be easily configured because a cell library, TTL, and the like are provided. However, when trying to realize a multiplication circuit with a large number of digits, there is no cell library or the like, so that the user has to design it by himself. However, when designing a multiplier with a large number of digits by itself, if the circuit configuration of the multiplier with a small number of digits is directly expanded, the circuit configuration becomes extremely complicated and difficult to realize.

Further, an input value is divided for each predetermined bit and
When trying to multiply by several clocks, the input value must be a polynomial
Considering the Galois field (Hiro Miyagawa, Yoshihiro Iwadare, Hideki Imai:
"Coding Theory", Shokodo, 1973, Chapter 4)
In a calculation system without glue, multiplication is performed by a circuit as shown in FIG.
Is known to be performed. * B in FIG._i Is B _i 
M bits * m bits using (i = 0,..., N-1) as a multiplier
A multiplier on the Galois field of EX, EX is an EXOR of m bits,
r is an m-bit register.

However, in multiplication on integers, when a division operation as shown in FIG. 2 is performed, a carry occurs for each digit obtained by the division operation, so that it is difficult to realize an efficient multiplier.

[0005]

SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned disadvantages, and performs multiplication of large integers by taking into account carry.
The circuit scale is small using a multiplier with a small number of digits.
It is an object of the present invention to provide an integer multiplication circuit having a simple configuration .

[0006]

In order to solve this problem, a multiplication circuit on integers according to the present invention provides an n-bit integer A and (h × x) when h, m, and n are positive integers. m) a multiplication circuit on an integer for multiplying a bit by an integer B;
H 1-bit × m-bit multipliers for multiplying each 1-bit of the integer A inputted from the upper digit in n clocks for each bit by different m-bits of the integer B respectively in parallel; , H m-bit full adders with 2-bit carry, each one output from the multiplier and m + 1 from the lower end of the previous clock output of the m-bit full adder with 2-bit carry of one lower digit. bit
Adds the value obtained by shifting the above partial eye one bit higher, and fed back value obtained by shifting the lower m bits of the output at the time of his own previous clock in one bit <br/> upper, h pieces of 2 Bitsutokiyari M-bit full adder with m-bit full adder and each of the m-bit full adder with 2-bit carry
One of storing the output of the m + 2 bits, and feedback the lower m bits to the full adder at the next clock, or lower
And it outputs the Luo m + 1 bits or more portions to the 2 Bitsutokiyari with m-bit full adder of the upper, h pieces of m + 2
A multiplying result A and B are sequentially output from the uppermost digit from the m + 2 bit register of the uppermost digit .

When h, m, and n are positive integers,
An integer multiplication circuit for multiplying an n-bit integer A by an (h × m) -bit integer B, comprising a 1-bit × m-bit multiplier, an m-bit full adder with a 2-bit carry, and an m + 2 bit register H are provided corresponding to a predetermined m bits of the integer B, and the integer A is divided into n clocks for each bit and input in parallel from the upper digit to the multiplier A. Each one bit is multiplied by a predetermined m bit of an integer B and output to the m-bit full adder. In the m-bit full adder, the output of each of the multipliers and the previous clock from the register of the lower digit are read. M + 1 from the lower end of the m-bit full adder of the lower digit of the hour
The value obtained by shifting the bit or more portions to one bit higher,
Lower m of the result of addition in the m-bit full adder at the previous clock from the register in the same arithmetic element
Adding the fed back value shifted to one bit higher the bit, the register, the m-bit full adder of m + 2 bits of the output holding time, fed back to the lower m bits in said m-bit full adder in the same calculation element that is, to provide the lower (m + 1) th bit or more portions to the m-bit full adder of the upper digit, and sequentially output from the high-order digit of the m + 2 from bit registers multiplication result a · B in the calculation element of the most significant It is characterized by.

The m-bit full adder with 2-bit carry is realized by a plurality of 2-input full adders or half adders.

[0009]

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In this embodiment, a multiplier of an integer A of n bits and an integer B of hm bits is assumed.
It is described as n. This limitation does not cause loss of generality. That is, it is assumed that an integer A of n bits and an integer B of nm bits are used, and the calculation of AB = C is executed. Here, multiplication a · b of two integers a and b of m bits
= C can be easily realized by a known configuration such as a cell library or TTL.

If the integer A is divided by 1 bit and the integer B is divided by n every m bits, it can be expressed as follows.

[0012] _{A = A n-1 · 2} n-1 + A n-2 · 2 n-2 + ... + A 1 · 2 + A 0 B = B n-1 · X n-1 + B n-2 · X n-2 + ... + B ₁ · X + B ₀ Here, X = 2 ^m, and the bit sequence obtained by dividing A and B into n from the upper digit is A _i , B _i (i = n−1,
..., 0). In this case, since the integers A and B can be regarded as polynomials, AB can be expressed as follows.

[0013]

A · B = A _n−1 · B · 2 ⁿ⁻¹ + A _n−2 · B · 2 ⁿ⁻² +... + A ₁ · B · 2 + A ₀ · B Here, generality is lost. Therefore, consider the case of n = 4.

A · B = A ₃ · (B ₃ · X ³ + B ₂ · X ² + B ₁ · X + B ₀ ) · 2 ³ + A ₂ · (B ₃ · X ³ + B ₂ · X ² + B ₁ · X + B ₀ ) ² + A ₁ · (B ₃ · X ³ + B ₂ · X ² + B ₁ · X + B ₀ ) · 2 + A ₀ · (B ₃ · X ³ + B ₂ · X ² + B ₁ · X + B ₀ ) It consists of a multiplier with a circuit like FIG. 1 shows that A _i (i = n−1,..., 0) is one bit unit and B _i is m
This is a multiplication circuit in a bit unit. Figure 1 1 × multiplier 4 m bits and _{(× B 0 ~ × B 3} ) is provided with with 2 Bitsutokiyari m-bit full adder 4 _{(+ 0 ~ + 3),} m +
It is composed of _four 2-bit registers ( _{R0 to} R4). In FIG. 1, the initial state of each register is all "0".
And

When A ₃ is input at the first clock,
The coefficient A ₃ · B _i (i = 3,..., 0) of each term of the equation is output from each multiplier and stored in each register through each full adder.

When A ₂ is input at the next clock,
The coefficients A ₂ · B _i (i = 3,..., 0) of each term of the equation are output from each multiplier. Since the expression is one digit greater than the expression in binary, the value stored in the register is shifted up one bit and added to the output from each multiplier representing the coefficients of the expression. Accordance connexion, the lower m bits of the register is fed back input to the adder while being shifted one bit higher, of each register m + 1 bit th or more is 1 bit
After being shifted to the higher order, it is input to the adder on the right. Accordingly, the adder performs addition of m bits shifted by 1 bit. If there is a carry, m + 2 bits are output and stored in the register again.

[0017] When A ₁ is entered in the next clock also,
Operation similar to that when A ₂ is input is made. Sand
Chi, m + 1 bit th carry bit of each register is input to the second bit from the lower right of the adder as the carry, the m + 2 bit-th carry bit of each register
Enter the third bit from the lower end of the adder on the right as a carry.
Ru is a force. That is, since the (m + 1) th bit of each register indicates the same bit position as the least significant bit of the register on the right, the adder does not have the least significant carry bit.
Treats as Kiyaribitsuto the second bit from the lower, each record
The m + 2th bit of the register is 2
Since it represents the same bit position as the bit,
It is necessary cormorant treated as Kiyaribitsuto of the third bit from the lower. Accordingly, the adder outputs m + 2 bits and stores it in the register again. As a result, the addition of the coefficients of the terms up to the above equation has been performed.

[0018] When the next last input A ₀ in clock is input, it is performed addition of coefficients of the terms of Yotsute to Formula similar operation, so that the multiplication of A · B were made. Thereafter, the clock is continuously input, and the multiplication results A and B may be output from the upper digit from the upper bit of the register of the highest digit, or the contents of each register may be read and the final multiplication results A and B may be output.
May be created. Thus, when the value of A is divided and input, the calculation of AB is efficiently performed.

In this example, the integer A is divided by one bit,
Although described as n = 4, without loss of generality, the integer A is assumed to be the number of nm bits divided into m bits, and is extended to multiplication of any integer in which n and h are different. In this case, an m-bit × m-bit multiplier is used.

It is also apparent that the full adder having a carrier in FIG. 1 can be realized by a combination of a plurality of two-input full adders and half adders. Also, it is clear that a similar multiplier can be constructed by omitting the rightmost register in FIG. 1 or adding a full adder and a register.

Further, as shown in FIG. 1, the same operation element (element) consisting of a multiplier (× B _j ), a full adder (+ _j ), and a register (R _j ) is constructed by repeating VLS.
There is also an advantage that a large-scale circuit such as I can be easily configured. Furthermore, using a memory having a plurality of regions R _j, by proceeding sequentially or parallel operation corresponding to the operation elements by software, it is apparent that the same operation results are obtained. The present invention may be applied to a system including a plurality of devices or to an apparatus including a single device. It is needless to say that the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

I to the present invention lever, a large integer multiplication,
Using a multiplier with a small number of digits while considering carry,
Provides an integer multiplication circuit with a small circuit size and simple configuration
It can be.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a multiplication circuit on an integer according to an embodiment.

FIG. 2 is a diagram showing a known polynomial multiplication circuit on a Galois field.

[Explanation of symbols]

R ... m + 2 bit register, + ... 2 m bit full adder with 2-bit carry, xB _i ... B _i (i = 0, ..., n
Multiplier on a 1-bit × m-bit integer with a multiplier of −1), and a 1-bit * m-bit Galois field with a multiplier of * B _i ... B _i (i = 0,..., N−1) Multiplier, EX ... m bit EXOR, r ... m bit register

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 7/52 310 G06F 7/60 WPI (DIALOG)

Claims (3)

(57) [Claims] 1. When h, m, and n are positive integers, n
An integer multiplying circuit for multiplying an integer A of bits and an integer B of (h × m) bits. The multiplication circuit is divided into n clocks for each bit, and each one bit of the integer A input from the upper digit is divided into n clocks. On the other hand, there are h number of 1-bit × m-bit multipliers for multiplying different m-bits of the integer B in parallel, and h number of m-bit full adders with 2-bit carry, each of which is the multiplier. one output of the one lower digit of 2 Bitsutokiyari with m-bit full previous lower from m + 1 bits or more portions of the output at the clock of the adder 1
A value shifted in bit higher, adds the fed back value obtained by shifting the lower m bits of the output at the time of his own previous clock in one bit higher, and h pieces of 2 Bitsutokiyari with m-bit full adder, each, the 2 Bitsutokiyari with m bits to store the output of one of m + 2 bits of the full adder, and feedback the lower m bits to the full adder at the next clock, the lower
Output of the m + 1-th bit or more from the m-bit full adder with 2-bit carry to the upper m bits,
And a register of +2 bits, the multiplication result A · from the m + 2 bits of the registers most significant
A multiplication circuit for integers, wherein B is sequentially output from an upper digit. 2. When h, m, and n are positive integers, n
A multiplication circuit on an integer for multiplying an integer A of bits and an integer B of (h × m) bits, comprising a 1-bit × m-bit multiplier and m with 2-bit carry
An arithmetic element having a bit full adder and a register of m + 2 bits is assigned an
The integer A is divided into n clocks for each bit and inputted in parallel from the upper digit in parallel from the upper digit, and each one bit of the integer A is multiplied by a predetermined m bit of the integer B to obtain the m. Output to a bit full adder, wherein in the m bit full adder, the output of each of the multipliers is:
A value shifted last the lower digit the m-bit full backward from m + 1-th bit than <br/> on parts of the adders during clock in one bit higher from the register of lower digit, said in the same calculation element The lower m bits of the addition result in the m-bit full adder at the time of the previous clock from the register are set to 1
Adding the fed back value shifted to bit higher, said register, said m holds bit full adder of m + 2 bits of the output at the same time, and fed back to the lower m bits in said m-bit full adder in the same calculation element, the lower To the (m + 1) th bit or more from the m + 2 bit register in the most significant digit of the arithmetic element, and the multiplication results A and B are sequentially output from the most significant digit. Multiply circuit over integers. 3. The m-bit full adder with two-bit carry is realized by a plurality of two-input full adders or half adders.
Multiplication circuit on integers as described.