JP3180898B2 - Boost circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit mounted on a portable electronic device or the like, and particularly to a booster circuit for supplying high-voltage power to a display device or the like.

[0002]

2. Description of the Related Art Portable electronic devices and the like are generally driven by a battery. However, in consideration of portability, the volume and weight of the battery cannot be increased, and the voltage cannot be increased. On the other hand, there are circuits and elements that require relatively high voltage power even in portable electronic devices.

[0003] Particularly, in a display device or the like, a PDP (Plasma D) is used.
isplay Panel: plasma display panel ) or LC
Many elements requiring a high voltage, such as D (Liquid Crystal Display), are used in many cases, and a small, lightweight, and efficient booster circuit is indispensable.

FIG. 5 is a connection diagram showing the principle of a booster circuit conventionally used, which is a double booster circuit that outputs an output voltage _{VOUT obtained} by boosting an input voltage _VREF approximately twice. In FIG. 5, the output terminal is connected to a capacitor Cb for storing a charge having a boosted potential. On the other hand, the capacitor Ca is a boosting capacitor that stores the charge and distributes the charge to the above-described capacitor Cb.

[0005] SW1 and SW2 connected to each end of the capacitor Ca are switches that simultaneously switch to a contact a or a contact b. First, when SW1 and SW2 each select the contact a, the charge of Q = Ca · VREF is stored in the capacitor Ca.

Next, when both SW1 and SW2 are switched to the contact b side, the positive electrode side (upper side in FIG. 5) of the capacitor Ca is connected to the capacitor Cb. For this reason, the electric charge Q stored in the capacitor Ca is distributed, and a part Q ′ of the electric charge Q is charged in the capacitor Cb.

[0007] By repeating such an operation, the capacitor Cb is charged with electric charge, and rises to a potential at which the electric charge is not distributed from the capacitor Ca, that is, a voltage twice the input voltage VREF.

FIG. 6 is a connection diagram showing an example of a double boosting circuit using the boosting principle as shown in FIG. This figure 6
Replaces SW1 and SW2 shown in FIG. 5 with N-channel MOS (Meta1-Oxide-Semiconductor), respectively.
switch) M7, M8 or P-channel M
An example in which OS switches M9 and M10 are replaced is shown.

The ON resistance of these MOS switches is configured to be as small as possible, and the transistor width of an element used for the MOS switch is generally relatively large. This is because a current flows through the switch when the boosting capacitor Ca is charged and discharged, but the voltage drop and the power loss caused by the MOS switch resistance are suppressed.

For example, this voltage drop or power loss is
Assuming that the average output driving the load by the boosted output voltage is I and the internal resistance of the switch is R, the voltage drop V is proportional to RI and the power loss P is proportional to RI2. That is, in order to suppress the voltage drop and the power loss without lowering the current driving capability, it is necessary to reduce the resistance R of the MOS switch.

However, in this case, even when the load RL is not connected (when current is not driven), the booster circuit operates in the same state as at the time of maximum current drive. For this reason, in the case where a circuit such as a power supply unit, a memory, a CPU, and the like is mixed in one substrate or one IC as in a portable electronic device or the like, noise generation or standby may occur. Problems such as large current consumption occurred.

[0012]

On the other hand, there has been proposed a booster circuit which suppresses current consumption by selecting a current capability and a frequency according to the situation of a peripheral device. For example, Japanese Unexamined Patent Publication No. 5-64429 discloses an example of such a circuit, and FIG. 7 is a connection diagram showing an example of such a booster circuit. In the example shown in FIG. 7, two operating frequencies f1 and f2 are selected according to the boosted potential, and the current driving capability is divided into two stages.

The current consumption I consumed by the entire booster circuit is Il, the current flowing through the load is Il, the current consumed by charging / discharging the parasitic capacitance of the source-drain of the MOS switch is Ip, MO
The current Id for driving the gate of the S switch and the through current It at the time of switch switching are expressed as follows. I = Il + Ip + Id + It (1)

In the above equation (1), the current Il flowing to the load of the first term is an item which is not related to the circuit. Further, the through current It at the time of switch switching of the fourth term can be set to 0 if the timing of switching two switches is implemented in an off / off state.
Think about terms.

In each of the second and third terms, the parasitic capacitance of the source-drain of the switch is Cp, the gate capacitance is Cg, and the frequency of the signal for turning on / off the switch is f. And

Here, the charging and discharging of the parasitic capacitance Cp is between the ground potential GND and the input voltage VREF, or between the input voltage VREF and the output voltage VOUT (that is, twice the input voltage VREF).
Charge / discharge of Qp = Cp · VREF is performed as the parasitic charge Qp.

On the other hand, the charge and discharge of the gate capacitance Cg of the switch are performed by the ground voltage GND and the output voltage VOUT (ie, the input voltage VR).
(Twice the EF). As a result, charge and discharge of the charge of Qg = Cg · 2 · VREF is performed as the gate charge Qg.

Therefore, the current consumption I of the booster circuit is expressed as follows. I = α · f (Cp + 2. Cg) (α is a proportional constant) (2) Therefore, if the frequency is switched as in this known example, the entire current consumption decreases in proportion to the frequency.

However, in the above-described conventional example, the current consumption for driving the gate capacitance Cp of the MOS switch is not considered. That is, since the apparent current consumption is merely reduced by changing the frequency, the current consumption during the operation of the entire booster circuit does not decrease.

Further, since the current drive capability is switched by connecting the MOS switches in series, the total number of switches increases, and the circuit scale increases. Furthermore, since a specific frequency is switched and used, there is a problem that versatility is poor.

The present invention has been made under such a background, and has as its object to provide a booster circuit which consumes less current during operation, has a smaller circuit scale, and is more versatile.

[0022]

The gist of the present invention is as follows: a capacitor for boosting an input voltage; first switching means for charging the capacitor; and a capacitor for discharging the charge from the capacitor. 2 switching means, and a driving means for supplying a driving signal to the first and second switching means at a predetermined timing. Each of the first and second switching means is connected in parallel with each other. From the first to the n-th (n
Is an integer of 2 or more), and the number of switch elements connected in parallel is changed in accordance with the boosting capability. The gist of the invention described in claim 2 is that the first to n-th (n is 2)
Switching elements of an integer greater than one) is that Sons to the booster circuit according to claim 1, characterized in that each is composed of a charging side MOS switches and the discharge side MOS switch. Also, the gist of the invention described in claim 3, and a capacitor for boosting an input voltage, a first switching means for charging the charge on the capacitor, a second switching means for discharging electric charge from said capacitor, A driving unit for supplying a driving signal to the first and second switching units at a predetermined timing, wherein each of the first and second switching units is connected in parallel with each other to the first to n-th switching units. (N is an integer of 2 or more), and the first to n-th (n is an integer of 2 or more) switch elements
Each of the switch elements comprises a charging MOS switch and a discharging MOS switch, and includes comparing means for comparing the input voltage with the boosted voltage. The boosting efficiency of the boosted voltage determined by the comparing means is the first efficiency. If the value exceeds the first switching element, both the charge-side MOS switch and the discharge-side MOS switch are turned off except for the first switch element, and if the boost efficiency becomes equal to or less than the first efficiency value, the second MOS switch is turned off. When the switching element is in the operating state, and the boosting efficiency is lower than the second efficiency value, the third switching element is in the operating state, and the boosting efficiency is lower than the (n-1) th efficiency value. In such a case, the booster circuit is characterized in that the n-th switch element is brought into an operating state. Further, the gist of the invention according to claim 4 includes switch control means for controlling the drive signal supplied to a gate electrode of each of the charging MOS switches and a gate electrode of each of the discharging MOS switches, 4. The switch control unit according to claim 3 , wherein each of the first to n-th switch elements controls an operation state according to a boosting efficiency of the boosted voltage obtained by the comparing unit.
Above. The gist of the invention described in claim 5 is that a capacitor for boosting an input voltage, first switching means for charging one end of the capacitor, and a second switching means for discharging charge from the other end of the capacitor. Switching means, and driving means for supplying a driving signal to the first and second switching means at a predetermined timing, wherein each of the first and second switching means includes a charging MOS switch and a discharging MOS switch. And a booster circuit comprising a first switch element and a second switch element which are connected in parallel with each other. The gist of the invention according to claim 6 is that a capacitor for boosting an input voltage,
A first switching unit configured to include a first MOS switch and a second MOS switch connected in parallel with each other and configured to include a charging MOS switch and a discharging MOS switch; Discharge side MO
S switch and a first switch connected in parallel with each other.
A second switching unit configured to discharge electric charge from the capacitor, a driving unit configured to supply a driving signal to the first and second switching units at a predetermined timing, And a switch control means for controlling the drive signal supplied to the gate electrode of each of the charging-side MOS switches and the gate electrode of each of the discharging-side MOS switches. 90% boost efficiency of boost voltage required by means
Is exceeded, the switch control means sets the charging side MOS switch and the discharging side M which constitute the second switch element.
Both of the OS switches are turned off, and the boosting efficiency is 90
%, The second switch element is brought into an operating state when the voltage is equal to or less than%.

According to the invention, the capacitor for boosting the input voltage, the first switching means for charging the capacitor, the second switching means for discharging the charge from the capacitor, and the first
And a driving unit for supplying a driving signal to the second switching unit at a predetermined timing, wherein each of the first and second switching units is connected to a first to n-th switch connected in parallel with each other. It is composed of elements. Also, the first
To n-th switch elements are formed by a charging MOS switch and a discharging MOS switch, respectively. In this case, the input voltage is compared with the boosted voltage by the comparing means,
If the boosting efficiency of the boosted voltage required by the comparing means exceeds the first efficiency value, the charge-side MOS transistors except for the first switch element
Both the switch and the discharge side MOS switch are turned off,
When the boosting efficiency is equal to or less than the first efficiency value, the second switch element is set to the operating state. When the boosting efficiency is equal to or less than the second efficiency value, the third switch element is set to the operating state. ..., when the boosting efficiency becomes equal to or less than the (n-1) th efficiency value, the n-th switching element is set to the operating state. Also,
In accordance with the boosting efficiency of the boosted voltage required by the comparing means, the switch control means supplies the gate electrode of each of the charging MOS switches and the gate electrode of each of the discharging MOS switches of the first to n-th switching elements. Control the drive signal.
Alternatively, a drive signal is supplied to a capacitor for boosting the input voltage, first switching means for charging the capacitor with electric charge, second switching means for discharging electric charge from the capacitor, and the first and second switching means at a predetermined timing. In the booster circuit including the driving means, each of the first and second switching means includes a first MOS switch and a second discharge switch, each of which comprises a charging MOS switch and a discharging MOS switch.
Of switch elements. In this case, the comparing means compares the input voltage with the boosted voltage, and when the boosting efficiency of the boosted voltage required by the comparing means exceeds 90%, the switch control means determines whether or not the charging-side MOS switch constituting the second switch element is discharged. When both the side MOS switches are turned off and the boosting efficiency becomes 90% or less, the second switch element is brought into an operating state.

[0024]

DETAILED DESCRIPTION OF THE INVENTION First Embodiment Hereinafter, the present invention will be described. FIG. 1 is a connection diagram illustrating a configuration of the booster circuit according to the first embodiment of the present invention. In FIG. 1, P1 is an input terminal to which an input voltage VREF is supplied, and P2 is an output terminal to which an output voltage is output. The output terminal P1 outputs twice the voltage of the input terminal P2.

M1 to M8 are MOS switches for charging and discharging, respectively, MOS switches M1 and M2, MOS switches M3 and M4, MOS switches M5 and M6, and MO switches.
The S switches M7 and M8 are respectively connected in parallel.

When the MOS switches M1 and M2 and the MOS switches M7 and M8 are turned on, the capacitor Ca is charged, and the MOS switches M3 and M4 and the MOS switch M3 are turned on.
When the S switches M5 and M6 are turned on, the capacitor C
Discharge from a.

The timing generation circuit 2 controls on / off of the MOS switches M1 to M8 at a predetermined timing. The input voltage VREF and the output voltage VOUT are input to the comparison operation circuit 1 to monitor whether a desired boosted voltage is output.

The switch control circuit 3 has two gate elements,
It is composed of an OR gate G1 and an AND gate G2, and controls signals supplied from the timing generation circuit 2 to the gate electrodes of the MOS switches M1 to M8 based on the output of the comparison operation circuit 1.

One of the input terminals of the OR gate G1 has
The signal f1 applied to the gate electrodes of the MOS switches M4 and M6 for discharging the capacitor Ca is input, and the output signal of the comparison operation circuit 1 is input to the other input terminal.

The signal f2 applied to the date electrodes of the MOS switches M2 and M8 for charging the capacitor Ca is input to one of the input terminals of the AND gate G2. An output signal is input.

Here, the operation of the present embodiment when the boosting efficiency is set to 90% or more will be described. In this case, half of the output voltage VOUT and 9 of the input voltage VREF
/ 10 level, VOUT / 2> 9 · VREF / 1
0, the output level of the comparison operation circuit 1 is “H”.
(High) ".

For example, when no load is connected to the present embodiment, there is no need to output a current. Therefore, the boost voltage is also 2 · VREF, and the boost efficiency is almost a value close to 100%. Therefore, the output of the comparison operation circuit 1 becomes “H”.

At this time, the MOS switches M1, M3, M5
And M7 is an output signal f1 of the timing generation circuit 2,
It is off regardless of f2. That is, the timing generation circuit 2
MOS to drive OR gate G1 and AND gate G2
The number of gates of the switch is halved. Therefore, the parasitic capacitance Cp of the source and the drain of the MOS switch (see the above equation (2)) is halved, and the current consumption is also close to half.

Next, a case where a load is connected to the present embodiment will be described. As output current increases, MOS
When the output voltage VOUT decreases due to the loss of the resistance of the switch and the boosting efficiency becomes 90% or less, the output of the comparison operation circuit 1 becomes "L".

Accordingly, the output signals f1 and f2 of the timing generation circuit 2 are directly applied to the gate electrodes of the MOS switches M3 and M5 or the MOS switches M1 and M7 by the functions of the OR gate G1 and the AND gate G2. For this reason, the current driving capability is increased by lowering the resistance value of the entire MOS switch, thereby maintaining the current driving capability.

That is, in this embodiment, the MOS switch for charging and discharging the boosting capacitor is divided and controlled, and the gate load to be driven is changed according to the load. Therefore, it is possible to reduce the gate drive current, which accounts for a large proportion of the operating current of the booster circuit, according to the situation. Further, by providing the comparison operation circuit with hysteresis, the above-described switching can be performed more stably.

B. Second Embodiment FIG. 2 is a connection diagram showing a configuration of a booster circuit according to a second embodiment of the present invention. In the above-described first embodiment, an example has been described in which the MOS switch is divided into two in the double boosting circuit. The present invention employs n as shown in FIG.
It can also be applied to a double booster circuit,
It is also possible to divide.

In the n-fold booster circuit, as shown in FIG.
One boosting capacitor is required, and a switch SWa or SWb for selecting two potentials is connected to both ends of each capacitor, and a double boosting circuit is connected in series.

FIGS. 3 and 4 are connection diagrams showing a detailed configuration of the switches SWa and SWb.
Shows the configuration of the switch SWa, and FIG.
Is shown.

As shown in FIG. 3 and FIG.
a or SWb is a m-divided P-channel MO
It is composed of S transistors (MP1 to MPm) or N-channel MOS transistors (MN1 to MNm).

Each switch SWa or SWb is driven based on the output of the oscillation circuit 5. This drive timing is controlled by an m-bit A / D (Analog / Digital: analog-digital conversion circuit) 4 to which the output voltage VOUT of the booster circuit is supplied via a switch control circuit 6.

As described above, according to the present embodiment, the resistance value of the MOS switch for driving the booster circuit and the drive gate capacitance thereof are changed according to the boosting condition due to the load drive.
Current consumption and noise due to useless operation are suppressed.

[0043]

As described above, according to the present invention, the capacitor for boosting the input voltage, the first switching means for charging the capacitor, the second switching means for discharging the charge from the capacitor, and the first And a driving unit for supplying a driving signal to the second switching unit at a predetermined timing, wherein each of the first and second switching units is connected to a first to n-th switch connected in parallel with each other. It is composed of elements. Further, the first to n-th switch elements are each constituted by a charging MOS switch and a discharging MOS switch. In this case, the input voltage is compared with the boosted voltage by the comparing means, and when the boosting efficiency of the boosted voltage obtained by the comparing means exceeds the first efficiency value, the charge-side MOS switch and the discharging-side MOS switch are switched except for the first switch element. Both the MOS switches are turned off, and when the boosting efficiency becomes equal to or less than the first efficiency value, the second switch element is set in the operating state. When the boosting efficiency becomes equal to or less than the second efficiency value, The third switch element is set to the operating state, and when the boosting efficiency becomes equal to or less than the (n-1) th efficiency value, the n-th switch element is set to the operating state. Further, the switch control means supplies the gate electrode of each charge-side MOS switch and the gate electrode of each discharge-side MOS switch of each of the first to n-th switch elements in accordance with the boosting efficiency of the boosted voltage obtained by the comparison means. Since the drive signal to be controlled is controlled, an effect is obtained that a booster circuit with small current consumption during operation can be realized. Alternatively, a drive signal is supplied to a capacitor for boosting the input voltage, first switching means for charging the capacitor with electric charge, second switching means for discharging electric charge from the capacitor, and the first and second switching means at a predetermined timing. In the step-up circuit, the first and second switching means are each constituted by a first and a second switch element, which are composed of a charging MOS switch and a discharging MOS switch and are connected in parallel with each other. Constitute. In this case, the comparing means compares the input voltage with the boosted voltage, and when the boosting efficiency of the boosted voltage required by the comparing means exceeds 90%, the switch control means determines whether or not the charging-side MOS switch constituting the second switch element is discharged. When both of the side MOS switches are turned off and the boosting efficiency becomes 90% or less, the second switch element is brought into an operating state, so that a boosting circuit having a small circuit scale and high versatility can be realized. The effect is obtained.

That is, in the present invention, unlike the conventional circuit,
Without changing the frequency of the booster circuit, the drive capability of the booster circuit and the total gate capacitance of the MOS switches that operate according to the load are changed to reduce current consumption.

Further, since the present invention can be implemented by dividing the MOS switch, it can be implemented on the same scale as the conventional one.
Further, unlike the conventional case, it is not necessary to suppress the current consumption by changing the frequency, and it is possible to add several gates and a comparison circuit to the existing timing circuit, so that the versatility is high.

[Brief description of the drawings]

FIG. 1 is a connection diagram illustrating a configuration of a booster circuit according to a first embodiment of the present invention.

FIG. 2 is a connection diagram illustrating a configuration of a booster circuit according to a second embodiment of the present invention.

FIG. 3 is a connection diagram showing a detailed configuration of a switch SWa in the embodiment.

FIG. 4 is a connection diagram showing a detailed configuration of a switch SWb in the embodiment.

FIG. 5 is a connection diagram showing the principle of a booster circuit conventionally used.

FIG. 6 is a connection diagram showing an example of a double boosting circuit using the boosting principle as shown in FIG.

FIG. 7 is a connection diagram illustrating a configuration example of a booster circuit that suppresses current consumption by selecting current capability and frequency.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 comparison operation circuit (comparison means) 2 timing generation circuit (drive means) 3 switch control circuit (switch control means) 4 m-bit A / D (comparison means) 5 oscillation circuit (drive means) 6 switch control circuit (switch control means) ) Ca capacitor M1, M2, M7, M8 N-channel MOS switch (MOS switch) M3, M4, M5, M6 P-channel MOS switch (MOS switch) MN N-channel MOS switch (MOS switch) MP P-channel MOS switch (MOS switch) SWa switch (second switching means) SWb switch (first switching means)

Claims (6)

(57) [Claims] A first switch for charging the capacitor; a second switch for discharging the charge from the capacitor; a first switch and a second switch for discharging the charge from the capacitor. And a driving means for supplying a driving signal at a predetermined timing, wherein each of the first and second switching means includes a first to an n-th (n is an integer of 2 or more) connected in parallel with each other. A booster circuit comprising a switch element, wherein the number of switch elements connected in parallel is changed according to boosting capability. 2. The first to the n-th (n is an integer of 2 or more)
2. The booster circuit according to claim 1, wherein each of the switch elements comprises a charge-side MOS switch and a discharge-side MOS switch. 3. A capacitor for boosting an input voltage, first switching means for charging the capacitor with electric charge, second switching means for discharging electric charge from the capacitor, and first and second switching means. And a driving means for supplying a driving signal at a predetermined timing, wherein each of the first and second switching means includes a first to an n-th (n is an integer of 2 or more) connected in parallel with each other. The first to n-th (n is an integer equal to or greater than 2) switch elements each include a charge-side MOS switch and a discharge-side MOS switch, and are configured to compare the input voltage with a boosted voltage. Means for determining whether the boosting efficiency of the boosted voltage obtained by the comparing means exceeds a first efficiency value. Off, the second switch element is turned on when the boosting efficiency is lower than the first efficiency value, and the third switch element is turned on when the boosting efficiency is lower than the second efficiency value. A booster circuit comprising: a switch element in an operating state; and when the boosting efficiency becomes equal to or less than the (n-1) th efficiency value, the n-th switching element is in an operating state. 4. A switch control means for controlling the drive signal supplied to a gate electrode of each of the charge-side MOS switches and a gate electrode of each of the discharge-side MOS switches, wherein the switch control means comprises: The first means depends on the boosting efficiency of the boosted voltage required by the means.
4. The booster circuit according to claim 3 , wherein the operation state of each of the first to nth switch elements is controlled. 5. A capacitor for boosting an input voltage, first switching means for charging a charge at one end of the capacitor, second switching means for discharging a charge from the other end of the capacitor, A driving means for supplying a driving signal to the second switching means at a predetermined timing, wherein each of the first and second switching means is a charging MOS
A booster circuit comprising a first switch element and a second switch element, which are composed of a switch and a discharge-side MOS switch and are connected in parallel with each other. 6. A capacitor for boosting an input voltage, and first and second switch elements which are composed of a charging-side MOS switch and a discharging-side MOS switch and are connected in parallel with each other, and charge the capacitor. A first switching means, comprising a first MOS switch and a second MOS switch connected in parallel to each other and comprising a charge-side MOS switch and a discharge-side MOS switch, for discharging electric charge from the capacitor. Means, a driving means for supplying a driving signal to the first and second switching means at a predetermined timing, a comparing means for comparing the input voltage with a boosted voltage, a gate electrode of each of the charging-side MOS switches, Switch control means for controlling the drive signal supplied to the gate electrode of each discharge-side MOS switch. When the boosting efficiency of the boosted voltage exceeds 90%, the switch control means includes a charge-side MOS switch and a discharge-side MOS switch constituting the second switch element.
A booster circuit, wherein both of the switches are turned off, and when the boosting efficiency becomes 90% or less, the second switch element is brought into an operating state.