JP3164445B2 - Decimal operation instruction processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decimal operation instruction processor for performing a decimal operation instruction process in an arithmetic and logic operation circuit constituting a central processing unit.

[0002]

2. Description of the Related Art In a central processing unit (hereinafter referred to as CPU) having a decimal addition / subtraction instruction, for example, when calculating 32-bit data, the CPU performs the processing shown in Table 1. In each table, which will be described later, including Table 1, one numeral is composed of 4 bits. The display of "hex" means hexadecimal notation, and the display of "Dec" means decimal notation.

[0003]

[Table 1]

In the example shown in Table 1, the CPU is a CPU.
In the arithmetic and logic operation circuit (hereinafter referred to as ALU) provided in the table, first, the operation is performed in binary and displayed in hexadecimal.
35468A ”, and the above answer is
The answer of "35354690" is obtained by correcting to binary data. In the following description, the answer obtained by the above-described operation of the binary number is “answer 1”, and the answer corrected to the decimal data is “answer 2”.

The above-mentioned method of correcting decimal data is such that when the operation for obtaining "answer 1" is an addition operation, the value in the nibble of the data on which the addition operation has been performed is hexadecimal "10", that is, binary. When "1010" is exceeded, a method is obtained in which a solution can be obtained by adding "6" (= 0110) in hexadecimal to the nibble value. The nibble value is 1
When a byte is composed of 8 bits, it refers to half of the 4-bit data. When such a correction operation is realized by the CPU, the following two methods are conceivable.

A first method is to provide a dedicated constant adder for adding a correction value to be corrected to decimal data to the data of "answer 1". In the second method, as shown in Table 2, for example, the data of "answer 1" is re-input to the ALU in the CPU with the same data length, while the value corresponding to the data of "answer 1" is stored. In this method, the correction value supplied to the ALU and the re-input data are added by the ALU to calculate "Answer 2".

[0007]

[Table 2]

[0008]

In the first method, since the addition operation of the binary operation and the decimal correction is performed by a dedicated adder, the correction is completed within a maximum of one CPU operation cycle. There is an advantage that the instruction can be executed at a higher speed as compared with the above-mentioned second method which requires two operations. However, since a dedicated adder is provided, there is a problem that the hardware increases, and the circuit is more complicated than the second method in which the propagation delay time of data such as a carry generated during the addition operation is considered. There is also a problem that it is impossible to follow the increase in the operation cycle rate of the CPU unless consideration is given to it.

Also, in the second method, after "Answer 1" is obtained in the binary operation cycle, the constant used in the correction cycle is determined. In the case of the example shown in Table 2 below, Since it is necessary to consider the carry from the lowest nibble value to determine the correction value of the highest nibble value, a propagation delay occurs, and the calculation data size increases as in the case of the first method. Sometimes, it is impossible to keep up with the increase in the operation cycle rate of the CPU, that is, the operation cycle rate is increased and the CPU can operate at a high speed.
However, there is a problem that the operation of the decimal operation command takes a long time, the operation of the CPU is eventually stopped, and the operation speed of the entire CPU cannot be improved.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has been developed without changing the circuit configuration.
CP according to the operation speed of the adder provided in the ALU
It is an object of the present invention to provide a decimal operation instruction processing device capable of processing a decimal operation instruction according to the operation cycle rate of U.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a decimal operation instruction processing for converting the operation result data of a binary representation sent from an arithmetic and logic operation means into a decimal representation by the arithmetic and logic operation means. When performing, the operation result data that is fed back to the arithmetic and logic operation means,
Perform the above decimal operation command processing based on the constant data;
In the decimal operation instruction processing device, the arithmetic and logic operation means outputs the operation result data to be processed by the decimal operation instruction as 4 decimal places.
A plurality of blocks are respectively supplied in bit units, and each block includes 4-bit data in the operation result data supplied as feedback,
Adding means for adding constant data consisting of bits; correction determining means for determining whether or not to perform decimal operation instruction processing on the 4-bit data based on the 4-bit data supplied from the adding means; A constant generating means for generating the constant data based on the data on the necessity of the decimal operation instruction processing supplied from the correction determining means and sending the constant data to the adding means. The arithmetic processing is performed in one operation cycle of the central processing unit provided with the decimal operation instruction processing device so that the operation result data processed by the decimal operation instruction processing can be divided into a plurality of times and the decimal operation instruction processing can be performed. A control to send a control signal to each of the blocks so that the blocks within a possible range are in a calculation enabled state and the other blocks are in a non-calculation processing state. Characterized by comprising a stage.

[0012] With this configuration, the control means sends a control signal to a block that can be operated out of a plurality of blocks provided in the arithmetic and logic operation means, so that the operation result data processed by the decimal operation instruction is processed. Is divided into a plurality of 10
It works so that binary arithmetic instruction processing can be performed. For example, the operation result data is composed of 32 bits, and every 4 bits is 8 bits.
In the case of being divided into three blocks, in the first decimal operation instruction processing, the control means makes it possible to operate the first four blocks, first performs the decimal operation instruction processing in the above four blocks, and causes the second In the decimal operation instruction processing, the decimal operation instruction processing can be performed in the last four blocks. As described above, the operation result data to be processed by the decimal operation instruction can be divided into a plurality of times and the decimal operation instruction can be processed, so that even if the operation cycle rate of the central processing unit is increased, the operation speed is increased. Since the control means can calculate up to the block in which the decimal operation instruction processing can be executed at one cycle rate, the control means can execute the decimal operation instruction processing following the increase in the operation cycle rate. Act like so.

Further, the present invention provides the above-described arithmetic and logic operation when the arithmetic and logic operation means performs the decimal operation instruction processing for converting the arithmetic result data of the binary number expression into the decimal expression by the arithmetic and logic operation means. In the decimal operation instruction processing device for performing the decimal operation instruction processing based on the operation result data and the constant data fed back to the operation means, the arithmetic and logic operation means is configured to execute the decimal operation instruction processing. A plurality of blocks are provided to each of which result data is supplied in 4-bit units, and each block adds 4-bit data and 4-bit constant data in the operation result data supplied as feedback. An adder, and a 1-bit data for the 4-bit data based on the 4-bit data supplied from the adder. Correction determining means for determining the necessity of decimal operation command processing, and constant generating means for generating the constant data based on data on the necessity of decimal operation command processing supplied from the correction determining means and sending the data to the adding means When,
And the decimal operation instruction processing device is provided so that the operation result data divided into four bits and processed by the decimal operation instruction can be divided into a plurality of times to perform the decimal operation instruction processing. Control means for sending a control signal to each of the blocks so that the blocks within a range in which the arithmetic processing can be performed in one operation cycle of the central processing unit and the other blocks are in a non-operation processing state. The correction determining means, when the calculation result data is obtained by addition, when the 4-bit unit data supplied from the addition means is 10 or more in decimal, or
When the carry signal is supplied from the lower-side addition means, which is 9 in decimal, it is determined that the output data of the block is required to process a decimal operation instruction, and the operation result data is obtained by subtraction. When a carry signal is not generated in units of 4 bits, it is determined that decimal operation command processing is required for output data of the block, predetermined data is transmitted, and predetermined value determination and constant basic data generation means are provided. ,
When the above operation result data is obtained by the addition, the previous 10 in the decimal operation instruction processing performed by dividing into a plurality of times is performed.
Performs a logical sum operation of the carry signal in the hexadecimal operation command processing and the carry signal supplied from the lower-order addition means, and retains the data obtained by the logical sum operation. When the result data is obtained, the carry signal generated in the first calculation result data in the binary representation is held, and the held carry signal is sent to the outside and the predetermined value judgment and constant basic data generating means. Signal generating means.

With this configuration, the carry signal generating means is provided for each of the blocks, and generates a carry signal for each block. Further, when the operation result data is obtained by the addition, the OR operation of the carry signal generated in the previous decimal operation instruction processing and the carry signal supplied from the lower-order addition means is performed. The carry signal generating means operates so that the carry signal to be generated in the decimal operation instruction processing is generated without disappearing.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a decimal operation instruction processing apparatus according to the present invention will be described below with reference to FIG. The decimal operation instruction processing device shown in the present embodiment is of a type that performs the same operation as the operation in the above-described second method, that is, supplies again the transmission data from the ALU to the ALU, and generates the transmission data based on the transmission data. The constant is added to the transmission data to obtain 10
It is similar to the type that sends the hexadecimal operation result,
In the decimal operation instruction processing device of this embodiment, when the transmitted data of the ALU is 32 bits, for the constant added to the transmitted data of the ALU, for example, the first time corresponds to the lower 16 bits of the transmitted data. 10 with constants only
Decimal operation instruction processing is performed to obtain an answer. At the next second time, decimal operation instruction processing is performed using only the constant corresponding to the upper 16 bits of the transmission data, and finally the decimal operated answer is obtained. Is to be obtained. Note that the decimal operation instruction processing is not limited to being performed twice as described above, and as described later, the decimal operation instruction processing device in the present embodiment is capable of processing every 4 bits, that is, in units of nibbles. Therefore, the decimal operation instruction processing can be performed in nibble units. Further, the present decimal operation instruction processing device is not limited to the decimal operation instruction processing for the case where the "answer 1" is obtained by the addition operation, and also the decimal operation for the case where the "answer 1" is obtained by the subtraction operation. The operation instruction processing can also be executed.

FIG. 1 shows an example of the configuration of an ALU in which a total of eight blocks are provided for performing processing for each nibble, that is, for each 4-bit unit, and for performing a decimal operation instruction process on data of a total of 32 bits. I have. In the 32-bit data, the block that processes the first to fourth bits on the lower side is the first block, and the next fifth to eighth bits.
The block for processing up to the bit is the second block, and similarly to the eighth block, and it is assumed that the first to eighth blocks exist from the upper side to the lower side in FIG. In the present embodiment, a control signal (a constant basic data generation circuit, which will be described later) provided from each control block and transmitted from the control circuit to which block from the first block to which decimal operation command processing is to be performed at one time is determined. DAJ
Signal) to control which of the blocks generates the basic data generation circuit.

The configuration of the decimal operation instruction processing device shown in this embodiment is shown below with reference to FIG. Each of the blocks is supplied with predetermined 4-bit data out of 32-bit data connected to the A bus and transmitted from the A bus, and is supplied from a constant generator 1 described later to a signal line f.
, A 4-bit adder 2 to which a constant is supplied via an input terminal, a latch circuit 3 connected to the output side of the adder 2 for storing output data of the adder 2 via a signal line b, a latch circuit 3 and an adder Is connected to the output side of the adder 2 and determines whether or not execution of the decimal operation command processing is necessary based on the data supplied from the latch circuit 3 via the signal line g and the carry signal d sent from the adder 2. A flag latch and correction determiner 4 to determine;
A constant generator 1 connected to the output side of the flag latch and correction determiner 4 via a signal line c and connected to the B bus to generate a predetermined 4-bit constant is provided. still,
The output side of the latch circuit 3 is connected to the A bus, and the 4-bit data subjected to the decimal operation instruction processing in each block is sent from the latch circuit 3 to the A bus.

As will be described in detail later, the flag latch and the correction determiner 4 differ in data generated by addition and subtraction of data supplied from the A bus and the B bus. Also, as shown in FIG. 1, the first block is provided with a flag latch and correction determiner 4a, the second block is provided with a flag latch and correction determiner 4b, and the third block is provided with a flag latch and correction determiner 4c. , The fourth block includes a flag latch and a correction determiner 4b,
The fifth block includes a flag latch and correction determiner 4c, and the sixth block includes a flag latch and correction determiner 4c.
b, a seventh block is provided with a flag latch and correction determiner 4c, and an eighth block is provided with a flag latch and correction determiner 4b. These flag latches and correction determiners are collectively referred to as a flag latch and correction determiner 4. Write.

In each of the second, third,... Blocks, the adder 2 is supplied with a carry signal from the adder included in the higher-order block via a signal line d. The carry signal is also supplied from the flag latch and correction determiner 4 included in the upper block via the signal line e to the unit 4.

The overall configuration of the decimal operation instruction processing device of the present embodiment is as described above. The specific circuit configuration of the latch circuit 3 and the like will be described below. In this embodiment, the circuit configuration of the adder 2 is not particularly limited. The latch circuit 3 has a configuration corresponding to one bit, for example, as shown in FIG. 2. One bit of the output data of the adder 2 is supplied to the signal line b, and the output data is output to the signal line g. Is done.
The constant generator 1 has a circuit configuration as shown in FIG.
Three kinds of control signals indicated by in FIG. 3, that is, data of the first to third bits, which are output from the flag latch and correction determiner 4, are supplied. It is supplied to the adder 2.

The relationship between the data generated by the constant generator 1 and the output data of the flag latch and the correction determiner 4 is shown below. That is, when the first to third bit data of the output data of the flag latch and correction determiner 4 is “000” or “001”, the constant generator 1 outputs “000”.
0 "to the adder 2, and the first to third data
When the bit data is "011", the constant generator 1
Sends the data "0110" to the adder 2, and when the first to third bit data is "110", the constant generator 1 sends the 4-bit data supplied from the B bus to the adder 2. Send out.

The flag latch and correction determiner 4 has the configuration shown in FIG. The components 4a, 4b, 4c shown in FIG.
Corresponds to the components 4a, 4b, 4c shown in FIG. Although each of the flag latches and the correction determiner 4a have a slightly different circuit configuration in each block, etc.
a predetermined value determination circuit 41 for determining whether or not the 4-bit data supplied from the latch circuit 3 via the g is a predetermined value
a, 41b, 41c and output data from a predetermined value judgment circuit 41a and the like, and a constant basic data generation circuit 42a, which sends out data on which constants generated from the constant generator 1 are generated.
42b, 42c and carry signal generating circuits 43a, 43b, 43c for generating carry signals for each block such as the first block, in other words, for each nibble.

The predetermined value judging circuit 41a and the like perform the above-mentioned "answer 1"
Is obtained by the addition operation, the nibble value:
(i) When the operation result data supplied from the latch circuit 3 is 16
Whether it is "A" in binary, that is, "1010" or more in binary, (ii)
Whether the operation result data is "9" in hexadecimal, that is, "1001" in binary, and whether there is a carry from the lower block, and whether "Answer 1" is obtained by subtraction operation When the condition is satisfied, a signal is sent to the constant basic data generation circuit 42a or the like when one of the conditions of whether the calculation result data has generated a carry signal in nibble units is satisfied.

The predetermined value judging circuit 41a is composed of an OR circuit and a NAND circuit as shown in the figure. Of the 4-bit data sent out by the latch circuit 3 in the first block, the lower second and third bits are transmitted. The data of the bit (indicated by) in the figure is supplied to the OR circuit, and the data of the fourth bit (indicated by) in the figure is supplied to the NAND circuit.

The predetermined value judging circuit 41b comprises a three-input NOR circuit, a NAND circuit, and an AND circuit as shown in FIG.
Of the bit data, inverted data of the first and fourth bits on the lower side (indicated by bars in the drawing) are supplied to the NOR circuit, and inverted data of the second and third bits (see FIG. (Indicated by bars and bars) is NAN
It is supplied to the D circuit. The constant basic data generation circuit 4 of the flag latch and correction decision unit 4a in the first block
Data supplied from 2a via signal line e is 3 input NO
It is supplied to one terminal of the R circuit.

The predetermined value judging circuit 41c comprises a three-input NAND circuit, an OR circuit, and a two-input NAND circuit, as shown in the figure, and the lower side of the 4-bit data transmitted by the latch circuit 3 in the third block. The first and fourth bits of data (indicated by, in the figure) are N
The data is supplied to the AND circuit, and the data of the second and third bits (indicated by, in the figure) is supplied to the NAND circuit. Also, the signal line from the constant basic data generation circuit 42b of the flag latch and correction decision unit 4b in the second block.
Data supplied via e is supplied to one terminal of a three-input NAND circuit. The predetermined value determination circuit 41a and the like are not limited to the illustrated circuit configuration, but may be any configuration that performs the above-described functions.

The constant basic data generation circuit 42a and the like
ADD signal and inverted A for changing constant data generated when data to be subjected to binary arithmetic instruction processing is obtained by an addition operation and when it is obtained by a subtraction operation
One input terminal is connected to each of the ADD signal line for transmitting the DD signal and the inverted ADD signal line, and the other input terminal is connected to the output terminal of the predetermined value determination circuit 41a or the like.
D circuit or the like and an output side of the two-input AND circuit or the like are connected, and DAJ for distinguishing the addition operation or the subtraction operation is used.
And a circuit 420 configured by a NAND circuit or the like connected to the DAJ signal line and the inverted DAJ signal line for transmitting the signal and the inverted DAJ signal, and transmitting 3-bit constant basic data to the signal line c. Note that the correction determiner 4 shown in FIG.
Since the circuit 420 included in b and 4c is the same as the circuit 420 included in the correction determiner 4a, the description is omitted.

In the present embodiment, the flag latch and the correction determiner 4 basically differ in the judgment of correction between addition and subtraction. At the time of subtraction, the fact that no carry (nibble) occurs in the first operation cycle indicates the necessity of correction, which is the reverse of the case of addition. Therefore, in the control of the ALU, it is necessary to distinguish between addition and subtraction in the constant basic data generation circuit, and the distinction is made between the DAJ signal and the inverted DA signal.
This is done with the J signal.

The carry signal generation circuit 43a, which is a characteristic circuit of the decimal operation command processing device of this embodiment, includes
A flip-flop 430 for storing a carry signal by a latch control signal supplied to a clock terminal, and an AND operation of the flip-flop 430 to which the stored data is supplied from the data output terminal and the ADD signal is supplied And a two-input AND circuit 432 for performing
The output side of the OR 32 is connected to one side, and the other side is connected to the signal line d extending from the adder 2a in the upper block.
And a circuit 431.

In the flag latch and correction decision units 4a and 4c, the inverted output terminal of the flip-flop 430 is connected to predetermined value judgment circuits 41a and 41c and constant basic data generation circuits 42a and 42c. In 4b, the output terminal of the flip-flop 430 is connected to the predetermined value judgment circuit 41b and the constant basic data generation circuit 42b. Also, the flip-flop 43
The carry signal transmitted from 0 is transmitted as a carry signal in a block provided with the flip-flop 430.

The operation of the decimal operation instruction processing device having such a configuration will be described below. In addition, when displayed in hexadecimal, the added data of “23234545” is supplied via the A bus, while when displayed in hexadecimal, “232” is displayed.
74445 "is supplied via the B bus, and the result of these addition operations is processed by a decimal operation instruction (hereinafter, this example is referred to as Example 1). Also, A
At the time of the LU operation, each digit of the data is represented by 4 bits in a binary number, and is composed of a total of 32 bits.

The 4-bit binary data representing the least significant digit "5" in the added data is supplied to the adder 2a provided in the first block shown in FIG. 1, and the least significant digit "5" in the data to be added. Is supplied to the adder 2a via the constant generator 1 provided in the first block. As in the case of the least significant data, binary 4-bit data representing the second digit “4” in the lowermost digit of the added data is supplied to the adder 2b provided in the second block, and Binary 4-bit data representing the lower digit "4" is supplied to the adder 2b via the constant generator 1 provided in the second block. In the same manner, 4-bit binary data corresponding to the highest digit of addition and addition is supplied to the adder 2b of the eighth block.

In this way, the addition operation of the added data and the added data is performed, and the result data "464" is obtained.
A898A "is obtained, and a decimal operation instruction process is performed on the result data. When performing decimal operation instruction processing,
Adder 2 constituting decimal operation instruction processing device of this embodiment
Because of the relationship between the arithmetic capability of the CPU and the propagation speed of the carry signal, it is considered that the limit to the operation up to, for example, the fourth block shown in FIG. Then, a plurality of DAJ signals are provided, and in the decimal operation instruction processing device of the present embodiment, the first control signal DAJ (hereinafter referred to as the first DA signal) transmitted from the control circuit 5 is provided.
J signal), the first to fourth blocks are grouped as a group, and the fifth to eighth blocks are grouped as another group with a second control signal DAJ (hereinafter, referred to as a second DAJ signal).
It is assumed that a binary operation instruction processing operation is performed.

That is, in Example 1, the decimal operation instruction processing is performed twice. In the first decimal operation instruction processing, the constant “898A” generated in correspondence with “898A” and the lower constant “898A” of the result data “464A898A”
Hexadecimal operation instruction processing is performed, and at this time, "464A"
For "0000" (hexadecimal)
Hexadecimal operation instruction processing, in other words, the upper side "464A"
Does not perform decimal operation instruction processing. The decimal operation instruction processing is performed again on the data obtained in this manner. In the next second decimal operation instruction processing, a constant generated for the upper side “464A” corresponding to the “464A” At this time, the lower-order “898A” is “0000” (1
Decimal operation instruction processing is performed with the data of (hexadecimal number), in other words, the decimal operation instruction processing is not performed on the lower side “898A”. As described above, the decimal operation instruction processing is performed twice, and finally, the data processed by the decimal operation instruction is obtained.

As described above, first, the decimal operation instruction processing is performed for the first to fourth blocks, and then the fifth to eighth blocks are processed.
The control for performing the decimal operation command processing on the block is performed by the DA supplied from the control circuit 5 to the circuit 420 provided in the constant basic data generation circuit 42a and the like shown in FIG.
This is performed by controlling which circuit 420 sends valid data by the J signal. In the case of the first example, first, in the first decimal operation instruction processing, the constant basic data generation circuit 42a in the first to fourth blocks is used.
Valid data is transmitted from the circuit 420 provided in
To constant basic data generation circuit 4 in the eighth to eighth blocks
The first DAJ signal is supplied to the circuits 420 of the first to fourth blocks and the second DAJ signal is supplied to the circuits 420 of the fifth to eighth blocks so that data "0" is transmitted from the circuit 420 provided in 2a or the like. Supply signal. Next, in the second decimal operation instruction processing, the circuit 42 provided in the constant basic data generation circuit 42a and the like in the first to fourth blocks
Data of 0 to "0" is transmitted, and circuits 420 of the first to fourth blocks are provided so that valid data is transmitted from the circuit 420 provided in the constant basic data generation circuit 42a and the like in the fifth to eighth blocks. Supplies the second DAJ signal and supplies the first to the circuits 420 of the fifth to eighth blocks.
Provides DAJ signal.

In the first embodiment, the first and second DAJ signals are supplied in units of four blocks. However, the present invention is not limited to this. The first and second DAJ signals may be supplied individually for each block. All eight blocks may be regarded as one unit.

First, the result data "464A898A"
A case will be described in which decimal operation instruction processing is performed for "898A" on the lower side. The above result data "464A8
98A "is supplied to the adder 2a via the first block A bus shown in FIG. 1, and the second lowest data" 8 "is added via the second block A bus. Vessel 2
b, the lower third data "9" is supplied to the adder 2a via the third block A bus, and so on. Similarly, the highest data "4" is supplied to the eighth block A bus. The signal is supplied to the adder 2b via the adder. The operation of the decimal operation command processing for each data will be described below.

The lowest digit "A", that is, "1010" in binary, is supplied from the latch circuit 3 to the flag latch and correction determiner 4a provided in the first block shown in FIG. That is, the predetermined value determination circuit 41a included in the flag latch and correction determiner 4a stores the second data
, The data of the fourth bit, that is, “101” is supplied. When the data "101" is supplied, the predetermined value determination circuit 41a performs a logical operation according to the logic circuit configuration shown in FIG. 4, and as a result, outputs a signal indicating that decimal operation instruction processing is required in the next stage. It is sent to the constant basic data generation circuit 42a.

Since the decimal operation command processing based on the addition operation result is executed, the signal level of the first DAJ signal is high (= 1), and the constant basic data generation circuit 42
“a” performs a logical operation according to the illustrated logic circuit configuration, and as a result, sends 3-bit “011” data to the constant generator 1 via the signal line c. The constant generator 1 performs a logical operation by the logical circuit configuration shown in FIG. 3 based on the supplied 3-bit data, and as a result, “6” in hexadecimal, 2
The data of "0110" in base is transmitted to the adder 2a.

Therefore, the adder 2a outputs the data "898
The addition of the least significant data "A" of "A" and the data of "6" in hexadecimal is performed using 4-bit data expressed in binary. The 4-bit result data obtained as a result is sent to the latch circuit 3 and sent from the latch circuit 3 to A
Sent to the bus. At this time, by setting the signal level of the first DAJ signal to a low level, the value sent from the flag latch and correction determiner 4a to the signal line C becomes a fixed H level. Thereby, the constant generator 1 shown in FIG. 3 is supplied with B (0) to B (3), that is, the value of the bus. The carry signal generated by the operation of the 4-bit data in the adder 2a is a signal line d.
Is supplied to the OR circuit 431 constituting the carry signal generation circuit 43a included in the flag latch and correction determinator 4a, and is OR-operated with the output data of the AND circuit 432, and the result is supplied to the flip-flop 430.
Then, the carry signal C3 is transmitted from the flip-flop 430 as a carry signal in the first block, and is also transmitted to the AND circuit 432.

Next, a case will be described in which decimal operation command processing is performed on the second-place data "8" of the data "898A". The operation will be described in order, but the decimal operation command processing itself in each block proceeds simultaneously. The lower second digit “8”, that is, “1000” in binary, is supplied from the latch circuit 3 to the flag latch and correction determiner 4b provided in the second block shown in FIG. The predetermined value determination circuit 41b included in the flag latch and correction determiner 4b stores the data "1" as shown in FIG.
000 "is supplied. When the data “0111” is supplied, the predetermined value determination circuit 4
1b performs a logical operation according to the logical circuit configuration shown in FIG. 4, and as a result, sends a signal to the effect that the decimal operation instruction processing is unnecessary to the constant basic data generation circuit 42b at the next stage.

As described above, the signal level of the first DAJ signal is high (= 1), and the constant basic data generation circuit 4
2b performs a logical operation according to the illustrated logic circuit configuration, and as a result, sends 3-bit "010" data to the constant generator 1 via the signal line c. The constant generator 1 performs a logical operation according to the logical circuit configuration shown in FIG. 3 based on the supplied 3-bit data, and as a result, “0” in hexadecimal,
The data of "0000" in binary is transmitted to the adder 2b.

Therefore, the adder 2b outputs the data "898
A is a 4-bit binary number representing the addition of the lower second data “8”, the data “0” in hexadecimal and the carry data supplied from the adder 2a of the first block. Perform with data. The resulting 4-bit result data is sent to the latch circuit 3 and sent from the latch circuit 3 to the A bus. At this time, the signal level of the first DAJ signal is at the low level, and the value transmitted from the flag latch and correction determiner 4b is at the H level, as in the case of the first block described above.

In the operation in the second block, no carry signal is generated in the adder 2b, so that no carry signal is supplied to the OR circuit 431 constituting the carry signal generation circuit 43a. Therefore, no data of "1" is supplied to the flip-flop 430, and no carry signal is transmitted from the second block.

As described in the description of the first block, even if a carry signal is not supplied from the adder 2b, the carry signal from the adder 2b and the AND circuit 432 in the carry signal generation circuit 43a and the like. In the case of addition, for example, when data of “1” is transmitted from the AND circuit 432 as in the case where a carry occurs in the previous operation cycle, each block is added. May carry a carry signal.

Next, a case will be described in which decimal operation command processing is performed on the third-place data "9" of the data "898A". The lower third digit “9”, that is, “1001” in binary, is supplied from the latch circuit 3 to the flag latch and correction determiner 4c provided in the third block shown in FIG. The data "1001" is supplied to the predetermined value determination circuit 41c included in the flag latch and correction determiner 4c as shown in FIG. When the data “1001” is supplied and the carry signal is not supplied from the constant basic data generation circuit 42b provided in the second block, the predetermined value determination circuit 41c performs the logical operation according to the logic circuit configuration shown in FIG. As a result, a signal to the effect that the decimal operation command processing is unnecessary is sent to the constant basic data generation circuit 42c at the next stage. The following operation is the same as the operation in the above-described second block, and thus the description is omitted. As a result of the calculation in the third block, no carry signal is transmitted.

Next, a case will be described in which the decimal operation command processing is performed on the most significant data "8" of the data "898A". Since the flag latch and correction determiner provided in the fourth block are the same as the flag latch and correction determiner 4b provided in the second block as shown in FIG. 1, the decimal operation of the most significant data "8" is performed. The instruction processing is the same as that in the description of the operation in the above-described second block, and a description thereof will not be repeated. As a result of the operation in the fourth block, no carry signal is transmitted.

In the above operation, the result data "464A
This means that the decimal operation command processing has been performed on "898A" on the lower side of "898A", and the circuit 420 of the fifth to eighth blocks for processing "464A" on the upper side of the result data has been described above. As described above, since the second DAJ signal is supplied, data of "00X" (X is 1 or 0) is sent from the constant basic data generation circuit 42a to the constant generator 1, and the constant generator 1 adds the adder 2a. Are supplied with 4-bit data of "0000" in binary, so that the decimal operation instruction processing is not performed on the upper-side "464A", and the decimal operation instruction processing device does not execute the "464A". Is transmitted as it is. Therefore, the data obtained in the first decimal operation command processing is "464A8990". And this "464A
The second decimal operation instruction processing is performed based on the data of “8990”.

The least significant data "0" of the above data "464A8990" is supplied to the adder 2a via the A bus of the first block shown in FIG. 1, and the second most significant data "9" of the second block is shown in FIG. The data "9" of the third lowermost position is supplied to the adder 2a through the A bus of the third block via the A bus, and similarly, the uppermost data "4" is supplied. The signal is supplied to the adder 2b via the A bus in the eighth block. The operation of the decimal operation command processing for each data will be described below.

As described above, the data "464A8
Since the second DAJ signal is supplied to the circuits 420 of the first to fourth blocks for processing "8990" on the lower side of "990", the constant basic data generation circuit 42a and the like to the constant generator 1 Is “00X” (X is 1
Or 0), and the constant generator 1 is supplied with 4-bit binary "0000" data from the constant generator 1 to the adder 2a and the like. No processing is performed, and the above-mentioned "8990" data is transmitted as it is from the decimal operation instruction processing device.

As shown in FIG. 1, the flag latch and correction determiner 4c provided in the fifth block have the same configuration as the flag latch and correction determiner 4c provided in the third block described in the first decimal operation command processing. is there. The flag latch and correction determiner 4c provided in the fifth block are supplied with the lowest digit "A" of the data of the upper "464A" from the latch circuit 3, that is, the data of binary "1010". You. Since no carry signal is generated in the constant basic data generation circuit 42b in the fourth block, no carry signal is supplied. Therefore, data "1"
010 "is supplied, the predetermined value determination circuit 41c
The logic operation according to the logic circuit configuration shown in FIG. 4 is performed, and as a result, a signal to the effect that decimal operation instruction processing is required is sent to the constant basic data generation circuit 42a at the next stage.

The constant basic data generation circuit 42c performs a logical operation according to the logic circuit configuration shown in the figure. As a result, the 3-bit "011" data is transmitted to the constant generator 1 via the signal line c.
Send to The constant generator 1 performs a logical operation by the logical circuit configuration shown in FIG. 3 based on the supplied 3-bit data, and as a result, “6” in hexadecimal and “01” in binary.
10 "is sent to the adder 2a.

Therefore, the adder 2a outputs the data "464"
The addition of the least significant data "A" of "A" and the data of "6" in hexadecimal is performed using 4-bit data expressed in binary. The 4-bit result data obtained as a result is sent to the latch circuit 3 and sent from the latch circuit 3 to A
Sent to the bus. At this time, by setting the signal level of the first DAJ signal to the low level, the value transmitted from the flag latch and correction determiner 4a becomes the H level. The carry signal generated by the operation of the 4-bit data in the adder 2a is supplied via a signal line d to an OR circuit 431 constituting a carry signal generating circuit 43c included in the flag latch and correction determiner 4c. The output data of the AND circuit 432 is ORed with the output data, and the result is supplied to the flip-flop 430. Then, the flip-flop 430 is used as a carry signal in the fifth block.
Transmits a carry signal C19, and the above AN
It is sent to the D circuit 432.

Next, for the data "4", "6", and "4", which are the second to highest data of the data "464A", 10
When the decimal operation instruction processing is performed, the operation is the same as that of the second to fourth blocks described in the first decimal operation instruction processing, and the description thereof is omitted. Thus, the result data “464A89
Decimal operation instruction processing ends for "464A", which is the upper side of "8A". Therefore, the decimal number data obtained in the second decimal operation instruction processing is “46508990”.
And this data is the data ultimately needed.

As described above, 10 in this embodiment is used.
The decimal operation instruction processing device is of a type in which the result data obtained by addition or subtraction is input to the ALU again to perform the decimal operation instruction processing, and the decimal operation instruction processing can be performed in a plurality of times. Although the number of cycles required for the operation increases accordingly, the internal propagation delay time of the ALU is reduced as compared with a type in which a dedicated decimal operation instruction processing device is added to the ALU and the decimal operation instruction processing is performed in one cycle. be able to. That is, in the case where the decimal operation instruction processing is performed in one cycle of the CPU, even if the operation cycle rate of the CPU is increased, the decimal operation instruction processing is not performed due to the propagation delay of the carry signal in the decimal operation instruction processing.
It can not be completed within the cycle time, CP
The processing operation of U stops. The decimal operation command processing is a highly independent operation that is difficult to execute in parallel with other processing operations, and is an additional operation. Stopping operation is disadvantageous for the whole system. However, as in the decimal operation instruction processing device of the present embodiment, the decimal operation instruction processing is divided into a plurality of parts, and the processing to the point where the ALU can be processed in one cycle of the CPU is performed once. The operation cycle rate can be increased without considering the decimal operation instruction processing, and even at such an increased cycle rate, the decimal operation instruction processing device of the present embodiment can operate the CPU at a higher speed. It can be executed without stopping the processing, and there is no need to add hardware since it is not of the type that separately adds a decimal operation instruction processor.

Next, the reason for providing the signal generation circuit 43a and the like and the effect obtained by providing the signal generation circuit 43a will be described. For example, data "83232325" (hexadecimal) and data "8007"
1234 ”(hexadecimal) and the result data“ 032A ”
3559 "is processed as a decimal operation instruction (hereinafter, this example is referred to as Example 2). In addition, a carry signal “1” is generated in addition result data “032A3559” (hexadecimal number) in the addition operation with “83232325” and “80071234” in the binary operation. The carry signal generation circuit 4 in the decimal operation instruction processing device as described above
In the apparatus excluding 3a and the like, when the decimal operation command processing of the addition result data is executed, for example, in two steps as in the above embodiment, the operation process is as shown in Table 3 below.

[0057]

[Table 3]

In brief, the above-mentioned operation process is performed by first performing a decimal operation instruction process on "3559" on the lower side of the addition result data "032A3559". At this time, the constant data sent from the constant generator is "3559". "," 0000 "(1
(Hexadecimal number). Therefore, in the first decimal operation instruction processing, the above addition result data “032A3559” and “000”
00000 "and the resulting data is" 032A3559 ". That is, no carry signal is generated in the first decimal operation command processing.

Next, the addition result data "032A355
Decimal operation instruction processing is performed for “032A” on the upper side of “9”. In this case, the constant data sent from the constant generator is “6006” in the case of the above “032A” with reference to the above operation description. (Hexadecimal). Note that the data of the highest order “0” of the above “032A” is actually “0” in the result of the carry, so the constant corresponding to the data “0” is “6”. Therefore, in the second decimal operation instruction processing, the addition result data “032A
3559 "and" 600600000 ", and the resulting data is" 63303359 ". That is, no carry signal is generated in the second decimal operation instruction processing. As described above, it is necessary to determine whether "0" is "0" after carry. As described above, when the decimal operation instruction processing is simply divided into a plurality of times, a problem arises in that a carry signal that should be originally generated does not occur. In order to solve this problem, a problem occurs. Control is required to hold the carry signal and to generate an appropriate constant at an appropriate constant generation time as described above.

There is another problem that it is necessary to recognize in which cycle the carry signal is generated. For example, a case will be described in which an addition result data "99999999A" of data "23232325" (hexadecimal) and data "76767675" (hexadecimal) is processed by a decimal operation instruction (hereinafter, this example is referred to as Example 3). Note that "23232325" and "76767675" in the binary operation
And addition result data "9999999A" in the addition operation
In (hexadecimal), no carry signal is generated. In a device in which the carry signal generation circuit 43a and the like are removed from the decimal operation instruction processing device as described above, the decimal operation instruction processing of the addition result data is executed, for example, in two steps as in the above embodiment. , The calculation process is shown in Table 4 below.
It becomes as shown in.

[0061]

[Table 4]

In brief, the above calculation process is performed by first performing a decimal calculation instruction processing on the lower-order “999A” of the addition result data “9999999A”. At this time, the constant data sent from the constant generator is “999A”. "," 6666 "(1
(Hexadecimal number). Therefore, in the first decimal operation instruction processing, the addition result data “99999999A” and “000
06666 ", and the resulting data is" 999A0000 ". That is, no carry signal is generated in the first decimal operation command processing.

Next, the addition result data "999A000
Decimal operation instruction processing is performed for “999A” on the upper side of “0”, and the constant data sent from the constant generator at this time is “6666” in the case of the above “999A” by referring to the above-described operation description. (Hexadecimal). Therefore, in the second decimal operation instruction processing, the above addition result data “999A0000” and “666660000” are added, and the result data becomes “00000000”, and a carry signal is generated in the second decimal operation instruction processing. I do. In this case, assuming that a carry signal generated as a result of the binary operation is held as in Example 2 above,
In this example 3, there is no carry signal. As can be seen from examples 2 and 3, the control of holding the carry signal in the cycle at a predetermined time cannot be dealt with uniformly. There is a problem that the timing for holding the signal must be controlled.

The carry signal generation circuit 43a and the like are provided to solve such a problem. As described in the above description of the operation, the carry signal generation circuit 43a and the like are provided in each of the first to eighth blocks, and carry the carry signal in the previous decimal operation instruction process and the current decimal Since the OR operation is performed with the carry signal from the adder 2a or the like in the lower block in the operation instruction processing, once the carry signal is generated, the carry signal to be generated as in the above-described example 2 is generated. The problem of not doing so does not arise.

The carry signal generating circuit 4 is provided for each block.
Since 3a and the like are provided, a block is selected even if, for example, decimal operation instruction processing is performed on 32-bit data, for example, when required data is data up to the eighth bit. Thus, carry signals up to the 8th bit can be obtained.

As shown in FIG. 4, since the output side of the carry signal generation circuit 43a and the like is connected to the predetermined value judgment circuit 41a and the like and the constant basic data generation circuit 42a and the like, a carry occurs. In some cases, a correct constant required for decimal operation instruction processing can be generated from the constant generator 1.

The specific operation of the carry signal generation circuit 43a and the like will be described for the case of Example 2 above. Since the carry is not generated for the lower data “3559” of the addition result data “032A3559” in the binary operation, the description is omitted, and the upper data “032A” will be described. The decimal operation instruction processing for the lowest data "A" of the data "032A" is performed by the fifth block shown in FIG. The 4-bit binary data representing the data “A” is supplied to a predetermined value determination circuit 41c of the correction determiner 4c,
Since the carry signal is not supplied from the adder 2b in the fourth block, the carry signal generation circuit 43
The data of "0" is output from the flip-flop 430 of the predetermined value determination circuit 41c and the constant basic data generation circuit 42c.
Sent to Therefore, the 3-bit data transmitted from the constant basic data generation circuit 42c is "010", and the constant generator 1 of the fifth block transmits "6" (hexadecimal) data to the adder 2a.

Therefore, the adder 2a adds the data "A" and "6". Therefore, the carry signal is sent from the adder 2a in the fifth block to the OR circuit 431 in the carry signal generation circuit 43b in the next sixth block. Next, the data “2” in the second place of the data “032A”
Is performed by the sixth block shown in FIG. The 4-bit binary data representing the data "2" is supplied to the predetermined value determination circuit 41b of the correction determiner 4b, and the flip-flop 4 of the carry signal generation circuit 43b.
30 outputs data of "1" to the predetermined value determination circuit 41b and the constant basic data generation circuit 42b.
The signal is sent to the outside as a carry signal in the sixth block. Therefore, the 3-bit data sent from the constant basic data generation circuit 42b is "001", and the constant generator 1 of the sixth block sends "0" (hexadecimal) data to the adder 2a. Therefore, the adder 2b adds "2", "0", and the carry signal supplied from the adder 2a of the fifth block, and sends out the data "3".

Hereinafter, the decimal operation instruction processing is executed in the same manner. As a result, the constant added to the data “032A” is “0006”, the answer after the second decimal operation command processing is “0330”, and the carry signal is transmitted from the sixth block. A carry signal is generated in the second decimal operation command processing, and the answer after the first or second decimal operation command processing is "03303559" and the carry signal is "1".

By providing the carry signal generation circuit 43a and the like as described above, if a carry signal to be generated is not generated, or if the operation result data is divided into a plurality of times and the decimal operation instruction processing is performed, the operation data , It is possible to solve the problem that it is necessary to pay attention to the time when the carry signal is generated.

In the above-described embodiment, a case has been described in which the decimal operation instruction processing is performed on the addition operation result data. However, in the apparatus shown in FIGS. Processing can also be performed. When the decimal operation command processing is executed for the subtraction operation, the signal level of the DAJ signal shown in FIG.
And The correction determiner 4a and the like shown in FIG. 1 operate when the operation result data does not generate a carry signal.
To generate a constant "6". The carry signal generating circuit 43a provided in the correction determiner 4a holds the carry signal when the carry result is generated in the binary-calculated subtraction result data. The generated carry signal is ignored. In addition, in the case of the subtraction operation, the data supplied from the correction determiner 4a and the like to the constant generator 1 is obtained by inverting the data shown in FIG. These controls are performed by the CP including the decimal operation instruction processing device.
U included in the program logic array (hereinafter, PLA)
Described below).

[0072]

As described in detail above, according to the present invention, the arithmetic and logic operation means is provided with a plurality of blocks, and the control means is capable of operating a predetermined block, thereby processing a decimal operation instruction. The operation result data can be divided into a plurality of parts to perform decimal operation instruction processing. In this way, the decimal operation instruction processing can be performed by dividing the operation result data processed by the decimal operation instruction into a plurality of times, so that the operation cycle rate of the central processing unit can be increased and the decimal operation instruction processing can be performed. Can be performed.

In addition, a carry signal generating means is provided for each block. For example, when the operation result data is obtained by addition,
Since the OR operation of the carry signal generated in the previous decimal operation instruction processing and the carry signal supplied from the lower-order addition means is performed, the carry to be generated in the decimal operation instruction processing is performed. It is possible to solve the problem that the signal is lost in the middle of the calculation, and since the carry signal is generated from each block, it is not necessary to pay attention when the carry signal is generated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a decimal operation instruction processing device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a circuit configuration example of a latch circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram showing an example of a circuit configuration of a constant generator shown in FIG. 1;

FIG. 4 is a circuit diagram illustrating an example of a circuit configuration of a correction determiner illustrated in FIG. 1;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 constant generator, 2a, 2b adder, 3 latch circuit, 4a, 4b, 4c correction determiner, 41a, 41b, 41c predetermined value determination circuit, 42a, 42b, 42c constant basic data generation circuit 43a, 43b, 43c ... carry signal generation circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-175628 (JP, A) JP-A-1-280828 (JP, A) JP-A-1-258129 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G06F 7/50 G06F 7/00

Claims (3)

(57) [Claims] 1. The arithmetic and logic operation means transmits the arithmetic result data in binary notation sent from the arithmetic and logic operation means to the arithmetic and logic means.
When performing a decimal operation instruction process for converting to a decimal representation, a decimal operation instruction processing device for performing the decimal operation instruction process based on the operation result data fed back to the arithmetic and logic operation means and the constant data In the above, the arithmetic and logic means comprises a plurality of blocks to which the operation result data to be processed by the decimal operation instruction are respectively supplied in units of 4 bits, and each block is provided in the operation result data to be fed back and supplied. Adding means for adding 4-bit data and 4-bit constant data; and performing decimal operation instruction processing on the 4-bit data based on the 4-bit data supplied from the adding means. Correction determination means for determining whether or not the decimal operation command processing supplied from the correction determination means is necessary And a constant generating means for generating the constant data based on the data and sending the constant data to the adding means. The arithmetic result data divided into four bits and processed by the decimal operation instruction is divided into a plurality of times. In order to be able to process decimal operation instructions, the above-mentioned blocks within a range in which operation can be performed in one operation cycle of the central processing unit provided with the decimal operation instruction processing device are set to be in an operable state, and the other blocks are 10. A decimal operation command processing device, comprising: a control unit for sending a control signal for setting a non-operation processing state to each of the blocks. 2. The arithmetic and logic unit according to claim 1, wherein the arithmetic result data in binary notation sent from the arithmetic and logic unit is processed by the arithmetic and logic unit.
When performing a decimal operation instruction process for converting to a decimal representation, a decimal operation instruction processing device for performing the decimal operation instruction process based on the operation result data fed back to the arithmetic and logic operation means and the constant data In the above, the arithmetic and logic means comprises a plurality of blocks to which the operation result data to be processed by the decimal operation instruction are respectively supplied in units of 4 bits, and each block is provided in the operation result data to be fed back and supplied. Adding means for adding 4-bit data and 4-bit constant data; and performing decimal operation instruction processing on the 4-bit data based on the 4-bit data supplied from the adding means. Correction determination means for determining whether or not the decimal operation command processing supplied from the correction determination means is necessary And a constant generating means for generating the constant data based on the data and sending the constant data to the adding means. The arithmetic result data divided into four bits and processed by the decimal operation instruction is divided into a plurality of times. In order to be able to process decimal operation instructions, the above-mentioned blocks within a range in which operation can be performed in one operation cycle of the central processing unit provided with the decimal operation instruction processing device are set to be in an operable state, and the other blocks are A control signal for sending a control signal to the respective blocks to make the non-calculation processing state possible. When the calculation result data is obtained by addition, the correction determination means outputs 4 bits supplied from the addition means. When the unit data is 10 or more in decimal, or when the data is 9 in decimal and a carry signal is supplied from the lower-order addition means, the output of the corresponding block is performed. If it is determined that the decimal operation command processing is necessary for the data, and if the above operation result data is obtained by subtraction, the decimal operation is performed on the output data of the block when no carry signal is generated in 4-bit units. A predetermined value determining and constant basic data generating means for determining that instruction processing is necessary and transmitting predetermined data; and a decimal arithmetic instruction processing which is performed by dividing the arithmetic result data into a plurality of times when the arithmetic result data is obtained by addition. Last 10 in
Performs a logical sum operation of the carry signal in the hexadecimal operation command processing and the carry signal supplied from the lower-order addition means, and retains the data obtained by the logical sum operation. When the result data is obtained, the carry signal generated in the first operation result data in the binary representation is held, and the held carry signal is sent to the outside and the predetermined value determination and constant basic data generating means. And a signal generating means. 3. The constant generating means generates the constant data of 0 or 6 in a binary number based on the predetermined data supplied from the correction determining means and sends it to the adding means. A decimal operation instruction processing device according to any one of the above.