JP3161870B2 - Plasma display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly to a PDP which is a self- luminous display cell.
About plasma display <br/> Lee device comprising (Plasma Display Panal).

[0002]

2. Description of the Related Art Flat panel display devices frequently used in display devices such as portable personal computers are:
Although the power consumption is much lower than that of a CRT (Cathode Ray Tube) type display device, further power dissipation technology is required in order to achieve long-time battery operation.

FIG. 10 is a conceptual block diagram of a conventional flat panel display device. 1 is an external display control circuit such as a graphic display controller for generating a display signal and various control signals accompanying the display signal, and 2 is a high potential necessary for display (for example, a DC voltage of about 100 V in the case of a PDP). 3) a control circuit for controlling display timing in accordance with horizontal and vertical scanning periods of the screen;
Reference numeral 4 denotes a display panel in which a large number of self-luminous display cells are arranged in a matrix, 5 denotes a driver that generates various drive pulses for driving the display panel, 6 denotes a drive current detection circuit, and 7 denotes an APC signal generation circuit. The drive current detection circuit 6 and the APC signal generation circuit 7 are circuits specially provided for power saving measures.

That is, the drive current detection circuit 6 includes a resistor (not shown) inserted in series on the transmission path of the drive voltage Vs, and an active element (high potential Vs) for detecting the voltage across the resistor. High-voltage transistors that support
And the display panel 4 via the driver 5
(Hereinafter referred to as “driving current Is”) is taken out as a voltage across the resistance element. Also,
The APC signal generation circuit 7 outputs a predetermined control signal Sapc whose duty in the H-level period changes according to the magnitude of the above-mentioned voltage (= driving current Is).

FIG. 11 shows the magnitude of the driving current Is (in the figure, three stages of Is _(L) <Is _(M) <Is _{(H ))} for convenience.
predetermined logic level of apc (H level for convenience)
It is a figure showing correspondence of duty change of a period. The drive current Is is proportional to the display ratio of the display panel 4, that is, the ratio of light emitting cells to all display cells. Therefore, as the display ratio becomes higher (in other words, as the display becomes higher in brightness), the power consumption increases, which causes a problem. As shown in the lower part of FIG.
If the high frequency period of the driving waveform of the display panel 4 (for example, a sustain discharge waveform in the case of a PDP) is changed in accordance with the H level period of Sapc, the higher the display ratio, the lower the high frequency period (the lower frequency period). Can be increased), and the above-described power consumption problem can be solved.

[0006]

However, in such a conventional flat panel display device, a resistance element is inserted in series on the transmission path of the drive voltage Vs, and the voltage across the resistance element is detected. Because
(1) The power supply impedance of the drive voltage Vs is increased by the resistance element, and the power supply efficiency is deteriorated. (2) It is necessary to build a transistor with a high breakdown voltage, which makes it difficult to cope with an increase in circuit scale and integration. And so on. [Purpose] Accordingly, an object of the present invention is to provide a circuit technique which can be suppressed to a circuit scale without deteriorating power supply efficiency and is adapted to integration.

[0007]

According to the present invention, there is provided a plasma display apparatus for lighting a display cell of a display panel in synchronization with the frequency of a sustain discharge waveform. Integrates the number of signals
And, an integrating means for outputting the accumulated result, is characterized in that a frequency changing means for changing the frequency of the sustain discharge waveform, based on the integrating calculation results.

[0008]

According to the present invention, the frequency of the sustain discharge waveform is changed based on the pixel information directly related to the display ratio. Therefore,
A resistance element or a high-voltage transistor on the transmission path of the driving voltage Vs is not required, so that deterioration in power supply efficiency and an increase in the circuit scale are avoided, and it is easy to cope with integration.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 9 are views showing an embodiment of a plasma display device according to the present invention. In FIG. 1, 1 is an external display control circuit, 2 is an external drive power supply, 3 is a control circuit, 4 is a display panel, 5 is a driver, and these circuits 1 to 5 are the same as those at the beginning of the prior art. It is.

Reference numeral 10 denotes a pixel number integrating circuit, and 11 denotes an AP.
This is a C signal generation circuit, and these circuits 10 and 11 are unique to this embodiment. That is, the pixel number accumulating circuit 10 has a function as an accumulating means for accumulating the number of pixel signals of a predetermined level from image signals given in a predetermined period, and the APC signal generating circuit 11 It has a function as frequency changing means for changing the panel drive frequency based on the result.

Here, the predetermined period is an arbitrary period synchronized with the screen scanning of the display panel 4, and is preferably a period of one vertical scan or one horizontal scan. The above-mentioned pixel signal of a predetermined level is a pixel signal having a level capable of lighting (self-luminous) a selected display cell of the display panel 4. For example, a digital pixel signal of two gray levels of white / black is used. A predetermined logic level (H level or L level) corresponding to the white level
Level). Also, the above-mentioned panel driving frequency is
This is the frequency of various waveforms required to drive the display panel 4, for example, the frequency of a sustain discharge waveform in the case of a PDP.

The drive current Is is determined by the display rate of the display panel 4,
That is, the display ratio is proportional to the ratio of the light emitting cells in all the display cells, and the display ratio correlates well with the integrated number of pixel signals having a level capable of lighting the selected display cell of the display panel 4 (for example, the integrated number in one vertical period). I do. Accordingly, since the integrated number (hereinafter referred to as “integrated pixel number”) is a value that indirectly represents the magnitude of the drive current Is required for display, as shown in FIG. If the duty in the H level period of Sapc is changed, a means for directly detecting the drive current Is (such as a resistance element or a high-voltage transistor) can be omitted, and the power supply impedance of the drive voltage Vs is increased. Without this, a circuit configuration suitable for integration can be realized.

First Embodiment FIG. 3 shows an example of a specific configuration of a pixel number accumulating circuit and an APC signal generating circuit. Here, for simplicity of description, the total number of display cells of the display panel 4 is set to 256 or less. In FIG. 3, reference numeral 12 denotes a pixel signal DAT.
8-bit output for counting the bits of H level (level at which the selected display cell of the display panel 4 can be turned on) in A (that is, the integrated value from 0 ₍₁₀₎ to 256 ₍₁₀₎ is output)
And the binary counter 12
Is reset (the integrated value is set to 0 ₍₁₀₎₎ every vertical period in synchronization with the vertical synchronization signal Vsync that has passed through the delay circuit 13 having a very small delay time. From the most significant bit of the binary counter 12 to n bits (n corresponds to the number of frequency variable steps of the panel drive waveform. For example, as shown in FIG. 2, n = 2 for three steps and n = 4 for 16 practical steps. Is latched for one vertical scan by an n-bit latch 14, and the n-bit output of the latch 14 (that is, the integration of the H level pixel signal during one vertical scan period) Value; hereinafter, for convenience, code Ds
) Is given to one input (n-bit A input) of the comparator 15. The other input (n-bit B input) of the comparator 15 is provided with an n-bit output of an n-bit binary counter 16 that counts the clock signal CLKst of an arbitrary frequency (a periodic function that repeats monotonically increasing from 0 to 16 stages, ie, A digital triangular wave; hereinafter, denoted by a symbol Dt for convenience) is given, and the comparator 15 changes the output Q (which becomes Sapc) to H level when A input <B input (when Ds <Dt). To

According to such a configuration, as shown in the operation timing chart of FIG. 4, the number of H-level pixel signals DATA input during one cycle of Vsync is integrated, and the integrated value is the timing of Vsync. Latch at 14
After that, 0 is synchronized with the output of the delay circuit 13
Reset to ₍₁₀₎ . Here, the integrated value Ds taken into the latch 14 is the total number of pixel signals of H level (a level at which the selected display cell of the display panel 4 can be turned on) input during one vertical scanning period. , The number of all display cells of the display panel 4 (here, 256).
A locus indicated by a broken line in FIG. 4 is an integrated value locus when all the display cells are turned on, and the power consumption in this case is the largest.

Output (Ds) of latch 14 in FIG.
Represents three stages: when the number of lit cells is minimum (a), when the number of lit cells is medium (b), and when the number of lit cells is close to the maximum for all cells (c). In stage a, since the value of Ds is small, “D
The period of s <Dt ”is long, and the output of the comparator 16 (S
The H level period of apc) is maximized. On the other hand, in step b, since the value of Ds becomes moderately large, “Ds <Dt”
Is moderate, and in step c, the value of Ds approaches the maximum or maximum, and the period of “Ds <Dt” approaches the minimum or minimum.

Therefore, the 16 outputs (Sa) of the comparator
Since the H level period of pc) changes in inverse proportion to the number of pixel signals integrated in one vertical scanning period, if the frequency of the driving waveform of the display panel 4 is changed using this Sapc, the driving as in the conventional example will be performed. An appropriate drive current Is corresponding to the display ratio can be obtained without requiring direct detection means (such as a resistive element or a high-voltage transistor) of the current Is. As a result, the power supply impedance of the drive voltage Vs and the circuit It is possible to solve the problem of increase in scale and to provide a circuit configuration suitable for integration.

Second Embodiment FIG. 5 shows an example constituted by an analog circuit. That is, the resistor 20, the operational amplifier 21, the capacitor 22, and the analog switch 23 constitute a first integrator 24 for integrating the level of the pixel signal DATA, and the integration period of the first integrator 24 is a small delay time. V passed through the delay circuit 25 of
Analog switch 2 that turns on / off in response to sync
This corresponds to 3 off periods (one vertical scanning period). Therefore,
The integrated value of the pixel signal DATA in one vertical scanning period is output from the first integrator 24, and the integrated value is held in the sample & hold circuit 26 at a non-delayed Vsync timing. The output of the sample-and-hold circuit 26 (that is, the integrated value of the pixel signal DATA in one vertical scanning period; Ds) is supplied to one input of an analog comparator 27 using an operational amplifier, and the other input of the analog comparator 27 is connected to a resistor. 28, operational amplifier 2
9, a saw-tooth waveform voltage Dt (a voltage reset for each cycle of the clock signal CLKsw) from the second integrator 32 composed of the capacitor 30 and the analog switch 31 is applied, and the analog comparator 27 satisfies Ds <Dt. A signal (Sapc) which becomes H level at the time is output.

Therefore, even with such an analog configuration, a signal (Sapc) in which the H level duty changes in inverse proportion to the integrated value of the pixel signal in one vertical scanning period can be generated, and this signal (Sapc) is used. By doing
It is possible to obtain an appropriate drive current Is corresponding to the display ratio without requiring direct detection means (such as a resistance element or a high breakdown voltage transistor) of the drive current Is as in the conventional example. It is possible to solve the problem of increasing the impedance and the circuit scale and to provide a circuit configuration suitable for integration.

Third Embodiment In the above-described first and second embodiments, the disadvantage that the APC signal (Sapc) responds to a slight change in the luminance of a pixel in the still display screen, that is, the still display screen For example, when performing blinking or inverting blinking for highlighting, the integrated value of the pixel signal changes in response to the blinking or blinking, and the APC signal (Sapc) changes. There is a disadvantage that.

[0020] Therefore, in this embodiment, in order to solve such drawbacks, in short, with the pixel signal number and the new pixel signal number of a subsequently entered at a certain time, a certain value the difference If it exceeds the threshold, the driving power of the display panel is controlled based on the new number of pixel signals . Note that the same reference numerals are given to circuit elements common to the first embodiment, and description thereof is omitted.

In FIG. 6, an n-bit output from an 8-bit binary counter 12 is output from an n-bit subtraction circuit 3.
0 is input to the A input and an n-bit latch 31. Latch 31 latches the n-bit output of counter 12 when the H level appears at the output of AND gate 32, and applies the latched content to B input of subtraction circuit 30. Subtraction circuit 30
Calculates the difference ΔDx between the A input and the B input and calculates the difference ΔD
x is given to the B input of the comparator 33,
3 is the value of the A input (the set value ΔDa of the setting register 34;
A value exceeding a value corresponding to a periodic change in the number of pixels such as a blinking cursor or an inverted blink) is compared with a value of the B input (ΔDx). When “ΔDa <ΔDx”, an H level signal from the output Q is output. Take Sc out. The signal Sc is supplied to the AND gate 32.
, And Vsync is applied to the other input of the AND gate 32.

In such a configuration, in the initial state,
The output Q (Sc) of the comparator 33 is at L level,
Since the output of the AND gate 32 is also fixed at the L level, the output (integrated value) of the counter 12 is given only to the subtraction circuit 32, and the subtraction circuit 30 outputs ΔDx having the same value as the integrated value.
Is output. If the value of ΔDx exceeds ΔDa after a certain time, the output Q (Sc) of the comparator 33
Changes to the H level, the output of the AND gate 32 also changes to the H level, and the output of the counter 12 at that time is taken into the latch 31. Then, the subtraction circuit 30 calculates a difference value ΔDx between the content held in the latch 31 (hereinafter, “old integrated value”) and the output of the counter 12 (hereinafter, “new integrated value”), and the comparator 33 calculates the difference value. ΔDx is the set value Δ
The output Q (Sc) is kept fixed at the L level until it exceeds Da.

Therefore, while the output Q (Sc) is at the L level,
That is, as shown in FIG. 7, until the difference value ΔDx between the old integrated value and the new integrated value exceeds the set value ΔDa, the latch 3
The same integrated value (old integrated value) is continuously output from 1 and Sa
Since the H level duty of pc does not change, flickering of the luminance of the entire screen can be suppressed, and the display quality can be improved.

Fourth Embodiment This embodiment is an example applied to multi-tone display. FIG. 8 is a diagram showing the configuration. The first counter 40 counts the first bit DATA ₀ of the pixel signal, and the second counter 41 counts the second bit DATA ₁ of the pixel signal. The n-bit outputs of the two counters 40 and 41 are added by an adder circuit 42, and the added value (ie, the integrated value of the four-gradation display pixel signal) is taken into the latch 43 at the timing of Vsync. The output Ds is compared by the same comparator 15 as in the first embodiment.

In the present embodiment, the integration of the number of pixels is performed in accordance with the weighting of the gradation of a plurality of image data signals. FIG. 8 shows that the image data signal is DATA
_This is the case of 2 bits of ₀ and DATA ₁ , that is, 4 gradations. DATA ₀ and DATA ₁ are counters 40 and
After the integration at 41, the integration result is added at the addition circuit 42. Since the integration value of the counter 41 is the value corresponding to the second bit of the gradation, it is necessary to add double weighting. . In the present embodiment, the integrated value of the counter 40 corresponding to the first bit of the gray scale is shifted by one bit (by １ ／) and input to the adder circuit 42, so that the two bits of the gray scale are relatively changed. The value corresponding to the eye is weighted twice.

Although FIG. 8 shows an example of four-gradation display, when applied to multi-gradation display of three or more gradations, the number of counters is increased in accordance with the bit configuration of the pixel signal. At the same time, a plurality of adder circuits may be hierarchically connected so as to add weights. Fifth Embodiment FIG. 9 shows an example in which the configuration of the fourth embodiment is realized by an analog circuit, and is a modification of the first embodiment.

That is, the difference from the first embodiment is that the input resistance of the first integrator 50 is changed by the bits DATA ₀ ,
Each DATA _{1 is} provided with a resistor 51 for DATA _{0 and} a resistor 52 for DATA ₁ , and the value of each resistor is made to correspond to the bit weight (the value of the resistor 52 is の of the resistor 51). The other points are common to the first embodiment.

[0028]

According to the present invention, it is possible to provide
Integrating the image element signal number that, release maintained based on the multiplication result
Since the frequency of the radio wave is changed, the circuit scale can be suppressed without deteriorating the power supply efficiency, and a circuit technology suitable for integration can be provided.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of an embodiment.

FIG. 2 is a principle waveform diagram of an embodiment.

FIG. 3 is a specific configuration diagram (first embodiment) of the embodiment.

FIG. 4 is an operation waveform diagram of FIG.

FIG. 5 is a specific configuration diagram (second embodiment) of an embodiment.

FIG. 6 is a specific configuration diagram of an embodiment (third embodiment).

FIG. 7 is an operation waveform diagram of FIG.

FIG. 8 is a specific configuration diagram of an embodiment (fourth embodiment).

FIG. 9 is a specific configuration diagram (fifth embodiment) of the embodiment.

FIG. 10 is a principle configuration diagram of a conventional example.

FIG. 11 is a principle waveform diagram of a conventional example.

[Explanation of symbols]

 4: Display panel 10: Pixel number integrating circuit (integrating means) 11: APC signal generating circuit (frequency changing means)

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/28 G09G 3/20

Claims (5)

(57) [Claims] 1. A plasma display device for lighting a display cell of a display panel in synchronization with a frequency of a sustain discharge waveform, wherein the number of pixel signals applied during a predetermined period is integrated, and the integration result is obtained.
And integrating means for outputting a plasma display apparatus characterized by comprising a frequency changing means for changing the frequency of the sustain discharge waveform, based on the integrating calculation results. (2) The predetermined period may be any time synchronized with screen scanning.
And the integrating means outputs the integrated result.
2. The plug according to claim 1, wherein the
Zuma display device. (3) The integrating means corresponds to a vertical synchronization signal.
3. The method according to claim 2, wherein the integration result is output.
Plasma display device. 4. The method according to claim 1, wherein said frequency changing means includes a pixel at a certain point in time.
When compared with the new pixel signal number which is the number of signals and then input, it exceeds a certain value the difference, new pixels
2. The plasma display device according to claim 1, wherein the frequency of the sustain discharge waveform is changed based on the number of signals . (5) The pixel signal has a plurality of signals for multi-tone display.
And the number of pixel signals consisting of the plurality of bits
And changing the frequency of the sustain discharge waveform by integrating.
2. The plasma display device according to claim 1, wherein: