JP3122622B2 - Division device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital arithmetic unit which performs a division by inputting normalized divisor data and dividend data and generates a 2-bit partial quotient per cycle. It is.

[0002]

2. Description of the Related Art In recent years, with the development of semiconductor technology, more than several million transistors can be integrated in one chip, and a block having a very complicated arithmetic function can be integrated into one VLSI. It is common sense to incorporate many inside. Digital arithmetic devices have come to include fixed-point adders, subtractors, multipliers, dividers, logical operators, and floating-point adders, subtractors, multipliers, dividers, and the like. In addition, not only the degree of integration,
In terms of speed, the technology has been remarkably advanced, and the speed has been further increased. Among these digital arithmetic devices, the systems of the dividing devices built in the VLSI are roughly classified into two types. One is a convergence type division by iterative multiplication, and the other is a subtraction shift type division based on a subtractor. The former uses a multiplier, so if the multiplier is built-in, it can be realized with almost no increase in hardware cost, but has a drawback in terms of speeding up. Further, when a multiplier is not built in, a multiplier is required for division, which causes a problem in hardware cost. The latter, to some extent, by adding hardware,
It is possible to improve the speed, but simply cannot increase the speed. The subtraction-shift type divider is described in Computer Arithmetic Principles, Architectures, a.
nd Design ".

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed divider.

Another object of the present invention is to provide a division device that executes a division operation at high speed by reducing the delay time by simplifying the path of the critical path to a simpler path.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a division apparatus according to the present invention executes division by inputting normalized dividend data and divisor data, and performs a 2-bit partial quotient every cycle. A first data holding means for selectively holding data as the dividend data and the partial remainder data as input data, and a second data holding the data as input to the divisor data. Holding means; first subtraction means for subtracting the data output from the second data holding means from the data output from the first data holding means and outputting a result; and the first data holding means. Comparing means for inputting the upper N bits of data output from the means and the upper N bits of data output from the second data holding means and outputting a comparison result; First selection means for selectively shifting left by one bit and outputting the data output from the calculation means and the data output from the first data holding means according to the comparison result of the comparison means; Data generation for adding an arbitrary signal generated by using the result of the subtraction performed by the first subtraction means and the comparison result output from the comparison means as an input to the output from the first selection means, and outputting the signal. Means, second subtraction means for subtracting the data output from the second data holding means from the data output from the data generation means, and outputting the result, and output from the first subtraction means. Second selection means for selectively shifting left by 2 bits and outputting the data and data output from the first data holding means as a data input in accordance with a subtraction result of the first subtraction means; The data output from the second subtraction unit is shifted left by one bit and the data output from the second selection unit are used as data inputs and selectively input according to the result of the subtraction by the first or second subtraction unit. And a third selecting means for outputting as partial remainder data.

According to the present invention, the critical path for determining the speed is (subtraction processing in the first subtracting means) + (data passing in the first selecting means).
+ (Subtraction processing in the second selection means) + (selection of data in the third selection means) + (passage of data in the third selection means), thereby realizing a high-speed division device. Become.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a subtraction shift type divider according to a first embodiment will be described below with reference to FIG.

FIG. 1 shows a case where division is performed by using normalized divisor data and dividend data as inputs, and two divisions are performed every cycle.
1 shows a configuration of a subtraction shift type division device that generates a partial quotient of bits. The input data is normalized data having a data width of 8 bits. A [7: 0] is a dividend input, and B [7: 0] is a divisor input. Since both the dividend input and the divisor input are normalized, the most significant bit A
1 is always input to [7] and B [7].

In FIG. 1, reference numeral 10 denotes the dividend input A.
This is a first data holding unit that selectively holds data with [7: 0] and partial remainder data as inputs. At the time of data input, the dividend input A [7: 0] is selectively input, and at the time of division execution, the partial remainder data is selectively input and held. When 9-bit data is held as the bit width of the data to be held and the dividend input A [7: 0] is selectively input, the MSB (Most Sign) is used.
1-bit data “0” is added to the side of the (Effect Bit) to hold 9-bit data. Reference numeral 20 denotes a second data holding means for holding the divisor input B [7: 0], and holds 9-bit data by adding 1-bit data "0" to the MSB side. This data is retained even at the time of division execution. 30 is the first data holding means 10
This is a first subtraction means for subtracting the data output from the second data holding means 20 from the data output from, and outputting the result, and is constituted by a 9-bit subtractor. Here, the second data holding means 20 has an 8-bit configuration, and the first subtraction means 30 adds 1-bit data "0" to the MSB side of the data output from the second data holding means 20. Even if subtraction is performed, it is functionally equivalent. 51 receives the data output from the first subtraction means 30 and the data output from the first data holding means 10 as inputs and selectively shifts left by one bit in accordance with the subtraction result of the first subtraction means 30. This is a first selecting means for outputting. If the subtraction result of the first subtraction means is positive or 0, the data output from the first subtraction means 30 is selectively shifted left by one bit and output. If the subtraction result is negative, the first data is outputted. The data output from the data holding means 10 is selectively shifted left by one bit and output. Reference numeral 41 denotes second subtraction means for subtracting the data output from the second data holding means 20 from the data output from the first selection means 51 and outputting the result, and comprises a 9-bit subtractor. You. 61 receives the data output from the second subtraction means 41 and the data output from the first selection means 51 as inputs and selectively shifts left by one bit in accordance with the subtraction result of the second subtraction means 41. This is the second selection means for outputting the data.
If the subtraction result of the second subtraction means 41 is negative, the data output from the first data selection means 51 is selectively changed to 1
The data output from the second subtraction means 41 is selectively shifted left by one bit and output in other cases. 70 is a partial quotient holding circuit. It holds a partial quotient generated according to the result of the subtraction performed by the first subtraction means 30 and the result of the subtraction performed by the second subtraction means 41. If the subtraction result of each of the first subtraction means 30 and the second subtraction means 41 is positive or 0, 1 is held as a partial quotient, and if it is negative, 0 is held as a partial quotient. Based on the results of the two subtractors, a partial quotient of two bits is generated and held every cycle. The partial quotient holding circuit 70 can be easily constituted by a 2-bit input shift register or a register having an input data selection function.

The operation of the above-configured dividing device will be described below.

First, normalized dividend data is input to a dividend input A [7: 0], and normalized divisor data is input to a divisor input B [7: 0]. Since the dividend data and the divisor data are both normalized, data “1” is input to the most significant bits A [7] and B [7]. The input data is held in the first data holding means 10 and the second data holding means 20, respectively, and the execution of division is started. After a 2-bit partial quotient is generated for each cycle, the output from the second selecting means 61 is input to and held in the first data holding means 10 as partial remainder data. By repeating this cycle N times, 2
The quotient of N bits can be obtained.

Further, in order to explain the operation in detail, 1
Combination of partial quotients generated in a cycle "0"
The operation will be described for each of 0 "," 01 "," 10 ", and" 11 ". Since the divisor data held in the second data holding means 20 is not changed as it is input, the bit [7] is always used. Is 1, but with respect to the data held in the first data holding means 10, since the partial remainder is taken in,
Bit [7] is not limited to “1”. Further, data "1" may be input to bit [8].

1) An example of a case where the partial quotient is “00”, the minuend input in the first subtraction means 0001000000 The subtraction input in the first subtraction means 010000000 The subtraction result in the first subtraction means 11010000000 (−001100000) → negative 1 selection means output 00100000 The minuend input in the second subtraction means 00100000 The subtraction input in the second subtraction means 010000000 The subtraction result in the second subtraction means 11100000 (-00100000) → negative 2nd selection means output 010000000 2) Partial quotient Example in the case of “01”, the minuend input in the first subtraction means 00111000000 The subtraction input in the first subtraction means 010000000 The subtraction result in the first subtraction means 1111000000 ( 000100000) → negative output of first selecting means 011000000 minuend input in second subtracting means 0110000000 subtractive input in second subtracting means 010000000 subtraction result in second subtracting means 00100000 (+00100000) → positive second selecting means output 010000000 3) Example when partial quotient is "10", minuend input in the first subtraction means 010100000 Subtraction input in the first subtraction means 0100000000 Subtraction result in the first subtraction means 00000000 (+000100000) → positive First selection means Output 00100000 Subtracted input in second subtraction means 00100000 Subtracted input in second subtraction means 010000000 Subtraction result in second subtraction means 11 000000 (−00100000) → negative Output of the second selecting means 010000000 4) Example in the case of partial quotient “11”, minuend input in the first subtraction means 011100000 Subtraction input in the first subtraction means 010000000 1st subtraction means 001100000 (+001100000) → positive Output of the first selection means 0110000000 Subtracted input in the second subtraction means 0110000000 Subtractive input in the second subtraction means 010000000 Subtraction result in the second subtraction means 00100000 (+00100000) → positive Second As described above, a 2-bit partial quotient is obtained within one cycle according to the result of the subtraction in the first and second subtraction means 30 and 41. When each subtraction result becomes 0, it is the same as when the operation result is positive.

Here, in the above dividing device, the critical path for determining the speed is (subtraction processing in the first subtraction means 10) + (selection of data in the first selection means 51) + (first selection means) (Data passing at 51) + (subtraction processing at second subtracting means 41) + (selection of data at second selecting means 61) + (data passing at second selecting means 61).

Hereinafter, the configuration of a divider according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 shows a case where the normalized divisor data and the dividend data are input and division is performed.
1 shows a configuration of a subtraction shift type division device that generates a partial quotient of bits. The input data is normalized data having a data width of 8 bits. A [7: 0] is a dividend input, and B [7: 0] is a divisor input. Since both the dividend input and the divisor input are normalized, the most significant bit A
1 is always input to [7] and B [7].

In FIG. 2, reference numeral 10 denotes a dividend input A [7:
0] and partial remainder data as inputs, and is a first data holding unit that selectively holds data. When inputting data, the dividend input A [7: 0] is selectively input, and when performing division, the partial remainder data is selectively input and held.
When 9-bit data is held as the bit width of the data to be held and the dividend input A [7: 0] is selectively input, 1-bit data “0” is added to the MSB side to add 9-bit data. Holds the data.

Reference numeral 20 denotes a second data holding means for holding the divisor input B [7: 0], and holds 1-bit data "0" on the MSB side to hold 9-bit data. This data is retained even at the time of division execution.

Reference numeral 30 denotes first subtraction means for subtracting the data output from the second data holding means 20 from the data output from the first data holding means 10 and outputting the result. It is composed of vessels. Here, the second
The data holding means 20 of the first embodiment has an 8-bit configuration, and the first subtracting means 30 performs subtraction by adding 1-bit data "0" to the MSB side of the data output from the second data holding means 20. Are also functionally equivalent.

Numeral 80 denotes a comparing means for inputting the upper 3 bits of the data output from the first data holding means 10 and the upper 3 bits of the data output from the second data holding means 20, and outputting a comparison result. is there. Even if the second data holding means 20 has an 8-bit configuration, and 0 is added to the most significant bit and then the comparison of the upper three bits is executed, the function is equivalent.

Reference numeral 50 designates the data output from the first subtraction means 30 and the data output from the first data holding means 10 as inputs and selectively shifts left by one bit in accordance with the comparison result of the comparison means 80. This is a first selecting means for outputting. Only when the upper 3-bit data of the data output from the first data holding means 10 is larger than the upper 3-bit data of the data output from the second data holding means 20, the first subtraction means 30 The output data is selectively output, and otherwise, the data output from the first data holding unit 10 is selectively output.

Reference numeral 40 denotes second subtraction means for subtracting the data output from the second data holding means 20 from the data output from the first selection means 50 and outputting the result.

Numeral 90 designates, as inputs, the data output from the first subtraction means 30 and the data output from the first data holding means 10, and selectively outputs two bits according to the subtraction result of the first subtraction means 30. This is second selection means for shifting to the left and outputting. The subtraction result of the first subtraction means 30 is positive or 0
In the case of (1), the data output from the first subtraction means 30 is selectively shifted left by 2 bits and output, and in the case of a negative value, the data output from the first data holding means 10 is selectively shifted by 2 Bit left shift output.

Numeral 60 indicates whether the data output from the second subtraction means 40 is shifted left by one bit and output in accordance with the result of the subtraction by the second subtraction means 40, or the second selection means 9
This is third selection means for directly outputting the data output from 0. If the subtraction result of the second subtraction means 40 is negative, the data output from the second selection means 90 is selectively output; otherwise, the data output from the second subtraction means 40 Is selectively shifted left by one bit and output.

Reference numeral 70 denotes a partial quotient holding circuit. The partial quotient is held according to the result of the subtraction performed by the first subtraction means 30 and the result of the subtraction performed by the second subtraction means 40. If the subtraction result of each of the first subtraction means 30 and the second subtraction means 40 is positive or 0, 1 is held as a partial quotient,
If it is negative, 0 is retained as a partial quotient. Based on the results of the two subtractors, a partial quotient of two bits is generated and held every cycle. The partial quotient holding circuit 70 can be easily constituted by a 2-bit input shift register or a register having an input data selection function.

The operation of the dividing device configured as described above will be described.

First, normalized dividend data is input to a dividend input A [7: 0], and normalized divisor data is input to a divisor input B [7: 0]. Since the dividend data and the divisor data are both normalized, data “1” is input to the most significant bits A [7] and B [7]. The input data is held in the first data holding unit 10 and the second data holding unit 20, respectively, and the execution of the division operation is started. Here, the dividend / partial remainder data output from the first data holding means 10 is data a [8: 0] and the divisor data supplied from the second data holding means 20 is data b [8: 0]. Then this 2
The two data a [8: 0] and b [8: 0] are simultaneously supplied to the first subtraction means 30 and the comparison means 80. In the first subtraction means 30, a subtraction of (a [8: 0] -b [8: 0]) is executed, and the result of the subtraction is output. In the comparing means 80, the 3 bits on the MSB side of the dividend / partial remainder data output from the first data holding means 10, that is,
a [8: 6] and the 3 bits on the MSB side of the divisor data supplied from the second data holding means 20, that is, b [8:
6] is performed.

Next, the output of the first selecting means 50 is controlled according to the comparison result. As a comparison result, 1) a [8: 6]> b [8: 6] 2) a [8: 6] <b [8: 6] 3) a [8: 6] = b [8: 6] There are three types of results, and the subsequent operations will be described in detail for each case.

In the case of 1), it is always true that a [8: 0]> b [8: 0] from the comparison result of the comparing means 80, so that the subtraction processing (a [8 : 0] -b [8: 0]) is not terminated, but the result is positive. Therefore, the partial quotient of the first bit is “1”. Since the result of the subtraction processing by the first subtraction means 30 is positive, it is necessary to input the output from the first subtraction means 30 to the second subtraction means 30 by shifting the output to the left by one bit. That is, the first selecting means 5
0 is controlled so that the subtraction result output from the first subtraction means 30 is selectively shifted left by one bit and output to the second subtraction means 40. The second selecting means 90 is controlled according to the operation result of the first subtracting means 30, and in this case,
Since the subtraction result of the first subtraction means 30 is positive, the output from the first subtraction means 30 is selectively shifted left by 2 bits and output. The third selecting means 60 is controlled according to the subtraction result of the second subtracting means 40. If the subtraction result of the second subtraction means 40 is positive or 0, the output from the second subtraction means 40 is selectively shifted left by one bit and output. If negative, the output from the second selecting means 90 is selectively output. By operating as described above,
In the case of 1), a partial quotient of “10” or “11” is generated.

In the case of 2), it is always true that a [8: 0] <b [8: 0] from the comparison result of the comparing means 80, so the subtraction processing (a [8 : 0] -b [8: 0]), the result is negative even if it does not end. Therefore, the partial quotient of the first bit is “0”. Since the result of the subtraction processing in the first subtraction means 30 is negative, it is necessary to input the output from the first data holding means 10 to the second subtraction means 10 by shifting the output to the left by one bit. That is, the first selecting means 50 is controlled so as to selectively shift the output from the first data holding means 10 to the left by one bit and output it to the second subtracting means 40. The second selecting means 90 is controlled according to the subtraction result of the first subtracting means 30, and in this case,
Since the subtraction result of the first subtraction means 30 is negative, the output from the first data holding means 10 is selectively shifted left by 2 bits and output. The third selecting means 60 is controlled according to the subtraction result of the second subtracting means 40. If the subtraction result of the second subtraction means 40 is positive or 0, the output from the second subtraction means 40 is selectively shifted left by one bit and output. If negative, the output from the second selecting means 90 is selectively output. By operating as described above, in the case of 2), a partial quotient of “00” or “01” is generated.

In the case of 3), there are cases where the result of the subtraction processing by the first subtraction means 30 becomes positive, becomes 0, and becomes negative. That is, a [5: 0]
If> b [5: 0], the result of the subtraction processing in the subtraction means 30 is positive, and if a [5: 0] = b [5: 0], the result of the subtraction processing in the subtraction means 30 is 0, a [5: 0] <b
If [5: 0], the result of the subtraction processing by the subtraction means 30 becomes negative, and 1
The partial quotient of the bit cannot be determined. However, the data b [8: 0] is stored in the second data holding unit 20.
Paying attention to the normalized divisor data supplied from, the combination of 2-bit partial quotients can be limited. Since the data b [8: 6] is the 3 bits on the MSB side of the normalized divisor data, the pattern is “01”.
Only "0" and "011" can occur, and in these two cases, the combination of the data a and b will be described in more detail.

When the 3-bit data on the MSB side is "010", the maximum value of the 9-bit data is "01011111".
1 "and the minimum value are" 0100000000000 "When a takes the maximum value and b takes the minimum value, the partial quotient becomes" 10 "as a result of the following two subtraction processes.

010111111 -010000001------------------------------------------------------------------------------------------- (Negative) → partial quotient “0” When a takes the minimum value and b takes the maximum value, the partial quotient becomes “01” as a result of the following two subtraction processes.

0100000000 -010111111------------------------------------------------------------------------- −−− 0010001001 (correct) → partial quotient “1” Next, when the MSB side 3-bit data is “011”, the maximum value of the 9-bit data is “0111111111”,
The minimum value is “0110000000”. When a takes the maximum value and b takes the minimum value, the partial quotient becomes “10” as a result of the following two subtraction processes.

011111111 -0110000000 ------------------------- 000111111 (positive) → partial quotient "1" 001111110 (subtraction result is shifted by one bit to the left) -011100000 -------------------------- 0010001010 (Negative) → partial quotient “0” When a takes the minimum value and b takes the maximum value, the partial quotient becomes “01” as a result of the following two subtraction processes.

0110000000 -011111111 -------------------------- 000111111 (negative) → Partial quotient "0" 110000000 (The output of the first data holding means is shifted one bit to the left) -0111111111 ----- −−−− 100000001 (correct) → partial quotient “1” Further, regardless of the values of a and b, when a = b, the partial quotient is “10” as a result of the following two subtraction processes. Becomes

01 ********** -01 **** *** --------------- 000000000 (0) → Partial quotient "1" 00000000 (the subtraction result is shifted one bit to the left) −01100000 −−−−−−−−−− 01100000 (negative) → partial quotient “0” As is clear from the above description, the comparison result by the comparing means 80 is 3) a [8: 6] = b [ 8: 6], the combination of partial quotients can be limited to “10” or “01”. That is, if the subtraction result in the first subtraction means 30 is positive or 0, the partial quotient is "10", and if the subtraction result in the first subtraction means 30 is negative, the partial quotient is "01". . By generating a partial remainder so as not to contradict the result, division can be executed without contradiction as a whole. Furthermore, the partial quotation is "10"
Is obtained by shifting the output from the first subtraction means 30 to the left by 2 bits as it is, and outputting the partial remainder when the partial quotient is "01". The output from the means 10 is shifted left by one bit and input to the second subtraction means 40, and the output from the second subtraction means 40 is shifted left by one bit and output. These two data are controlled by the first selecting means 50 so that the output from the first data holding means 10 is selectively shifted left by one bit and output, and the second selecting means 90
Is controlled so that the output from the first subtraction means 30 is selectively shifted left by two bits and output, and then the third selection means is controlled according to the result of the second subtraction means 40. 60
Can be output from the third selecting means without inconsistency with the partial quotient. That is, the comparing means 80
3) a [8: 6] = b [8: 6]
In the case of (1), the first selecting means 50 is controlled so that the output from the first data holding means 10 is selectively shifted left by one bit and output to the second subtracting means 40, If the subtraction result is positive or 0 in accordance with the result of the subtraction by the first subtraction means 30,
, The output from the first data holding means 10 is selectively shifted left by two bits and output to the third selecting means 60 if the output is negative, thereby executing division without contradiction. can do. As a modified example of the above operation, the comparison result of the comparing means 80 is 3) a [8: 6] = b [8:
6], the 2-bit partial quotient is added to the first subtraction means 3
The determination may be made according to the subtraction result of the second subtraction means 40 instead of the subtraction result of 0. Further, in this case, the third selecting unit 60 that outputs the partial remainder data may be controlled according to the subtraction result of the first subtraction unit 30 instead of the subtraction result of the second subtraction unit 40.

As described above, by the operation of the divider, a 2-bit partial quotient is generated every cycle, and then the output from the third selecting means 60 becomes the first data holding data as partial remainder data. It is input to the means 10 and held.

By repeating this cycle N times,
A quotient of 2N bits can be obtained. Here, a critical path, which is a path for determining the delay / speed when performing this operation, will be described. First, the generation route of the partial remainder is examined. When the partial quotient is “10”, the partial remainder is generated along the route of the first subtraction unit 30 → the second selection unit 90 → the third selection unit 60. , Partial quotation is “01”
In this case, the partial remainder is generated along the path of the first selecting means 50 → the second subtracting means 40 → the third selecting means 60. The path here is the flow of the data itself starting from the first and second data holding units 10 and 20.

From the same viewpoint, the routes of the partial quotient and the partial remainder for each comparison result in the comparing means 80 are summarized as follows.

1) If a [8: 6]> b [8: 6], partial quotient "10" Partial remainder path First subtraction means 30 → second selection means 90 → third selection means 60 Partial quotient “11” Partial remainder path First subtraction means 30 → first selection means 50 → second subtraction means 40 → third selection means 602 2) a [8: 6] <b [8: 6 ], The partial quotient "00" The path of the partial remainder The second subtraction means 40 → the third selecting means 60 The partial quotient “01” The path of the partial remainder The first selecting means 50 → the second subtracting means 40 → 3) Selection means 60 3) If a [8: 6] = b [8: 6], partial quotient “10” Partial remainder path First subtraction means 30 → third selection means 90 → third selection Means 60 Partial quotient “01” Path of partial remainder First selection means 50 → second subtraction means 40 → third selection means 60 Since the path of flow of the main data when generating the remainder, when considering the overall delay, delay required to flow / control of the control in addition to it is necessary to consider. Critical paths are summarized by defining each delay element as follows.

D0: (Comparison processing in the comparison means 80) D1: (Subtraction processing in the first subtraction means 30) D2: (Selection of data in the first selection means 50) D3: (The first processing D4: (subtraction processing in the second subtraction means 40) D5: (selection of data in the third selection means 60) D6: (data selection in the third selection means 60) D7: (Selection of data by the second selection means 90) D8: (Passage of data by the second selection means 90) When the critical paths are arranged according to the above definition, 1) a [8: 6]> b [8: 6], critical path 1 D0 → D2 → D3 → D4 → D5 →
D6 critical path 2 D1 → D3 → D4 → D5 → D6 2) If a [8: 6] <b [8: 6], critical path 3 D0 → D2 → D3 → D4 → D5 →
D6 3) If a [8: 6] = b [8: 6], critical path 4 D0 → D2 → D3 → D4 → D5 →
D6 critical path 5 D1 → D3 → D4 → D5 → D6 Here, comparing the paths of D0 → D2 and D1, D0 →
Since the path of D2 has a sufficiently smaller delay than the path of D1, the most delay critical path is D1.
→ D3 → D4 → D5 → D6. The critical path in the first embodiment is D1 → D2 → D3 → D4 → D5
Since it was D6, the speed was increased by D2.

As is apparent from the above description, according to the dividing apparatus of the second embodiment of the present invention, the comparing means 80 for comparing the upper 3 bits of the dividend data and the divisor data with each other is provided. The output of the first selecting means 50 is controlled. As a result, it is possible to configure a division device that realizes high-speed operation by reducing critical paths while guaranteeing execution of division.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a division device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a division device according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st data holding means 20 2nd data holding means 30 1st subtraction means 40 2nd subtraction means 50 1st selection means 90 2nd selection means 60 3rd selection means 70 Partial quotient holding means 80 Comparison means

Claims (6)

(57) [Claims] 1. A division device for executing division by inputting normalized dividend data and divisor data and generating a 2-bit partial quotient every cycle, wherein the dividend data and the partial remainder data are input data. A first data holding unit for selectively holding data, a second data holding unit for holding the data by inputting the divisor data, and a second data holding unit based on the data output from the first data holding unit. First subtraction means for subtracting the data output from the data holding means and outputting the result, and upper N bits of the data output from the first data holding means and output from the second data holding means Comparing means for inputting the upper N bits of the received data and outputting a comparison result; and data output from the first subtracting means and the first data holding means. Depending on the comparison result of the comparing means the force data as input selectively one bit left shift to the first selecting means for outputting said first from said output data from the selection means second
Second subtraction means for subtracting the data output from the data holding means and outputting the result; and inputting the data output from the first subtraction means and the data output from the first data holding means. Second selecting means for selectively shifting left by 2 bits according to the subtraction result of the first subtracting means and outputting the data; and data obtained by shifting the data output from the second subtracting means by one bit to the left. And third selecting means for selectively outputting data output from the second selecting means as a data input as partial remainder data according to the subtraction result of the first or second subtracting means. Characteristic division device. 2. The comparison means according to claim 1, wherein the comparison means outputs the upper three bits of the data output from the first data holding means and the upper three bits of the data output from the second data holding means as inputs. Claim 1 characterized by the following:
A division device as described. 3. In the first selection means, as a result of the comparison by the comparison means, the upper three bits of the data output from the first data holding means are the data output from the second data holding means. Selectively outputs the data output from the first subtraction means if the data is larger than the upper 3 bits of the data. Otherwise, selectively outputs the data output from the first data holding means. 3. The dividing device according to claim 2, wherein the dividing is performed. 4. As a result of the comparison by the comparing means, the upper 3 bits of the data output from the first data holding means and the upper 3 bits of the data output from the second data holding means.
4. The dividing device according to claim 3, wherein when the bit data is the same, a 2-bit partial quotient is determined according to a subtraction result of the first subtraction means. 5. As a result of the comparison by the comparing means, the upper three bits of the data output from the first data holding means and the upper three bits of the data output from the second data holding means.
4. The dividing device according to claim 3, wherein when the bit data is the same, a 2-bit partial quotient is determined according to a subtraction result of the second subtracting means. 6. A division apparatus for executing division by inputting normalized dividend data and divisor data and generating a 2-bit partial quotient every cycle, wherein the dividend data and the partial remainder data are input data. A first data holding unit for selectively holding data, a second data holding unit for holding the data by inputting the divisor data, and a second data holding unit based on the data output from the first data holding unit. A first subtraction unit for subtracting the data output from the data holding unit and outputting a result, and a data output from the first subtraction unit and the data output from the first data holding unit as inputs. First selecting means for selectively shifting left by one bit according to the result of the subtraction by the first subtracting means, and outputting the data; Serial second
Second subtraction means for subtracting the data output from the data holding means and outputting the result, and inputting the data output from the second subtraction means and the data output from the second selection means. A second selecting means for selectively shifting left by one bit in accordance with the result of the subtraction by the second subtracting means and outputting the result as partial remainder data.