JP3121854B2 - Absolute signal generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating an absolute signal, and more particularly, to an inexpensive method using incremental signals having different resolutions of fine and coarse (using two incremental encoders or electrically obtained from one). The present invention relates to a novel improvement for realizing a high-resolution absolute encoder.

[0002]

2. Description of the Related Art There have been various types of absolute encoders of this type which have been used in the past. One example is the configuration proposed by the present applicant disclosed in Japanese Patent Application Laid-Open No. 64-1911. is there.

[0003]

Since the conventional absolute encoder is configured as described above, the following problems exist. That is, the pattern formed on the rotating disk becomes extremely complicated, and particularly in the case of a multi-rotation absolute encoder, an encoder having two rotating disks having different patterns must be connected via a gear mechanism. It was complicated both electrically and electrically.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in particular, is an incremental signal having different resolutions of fine and coarse (using two incremental encoders or electrically obtaining one from one). It is an object of the present invention to provide an absolute signal generation method capable of realizing a high-resolution absolute encoder at a low cost by using the method.

[0005]

According to the present invention, there is provided a method for generating an absolute signal, comprising the steps of: determining a direction of a coarse incremental signal; inputting a coarse counter; and determining a direction of a fine incremental signal which is a multiple of the coarse incremental signal. A fine counter to be input later, and the pulse timings of the coarse and fine incremental signals are synchronized by a correction synchronization circuit, and the contents of the fine counter are reset by the LSB signal of the coarse counter. And interpolating between the LSB signals of the coarse counter by the fine incremental signal.

More specifically, a method is provided in which the count data of the coarse counter is preset by load data whose absolute value is detected when the power is turned on.

[0007] More specifically, the method is such that the coarse and fine incremental signals are obtained from incremental signals from a single incremental encoder.

[0008]

In the method for generating an absolute signal according to the present invention, two types of incremental signals having different resolutions, fine and coarse, are obtained from one or two incremental encoders, respectively counted, and the fine counter is counted by the LSB signal of the coarse counter. By resetting the contents and interpolating and dividing each LSB signal of the coarse counter by a fine incremental signal, a high-resolution absolute signal can be generated at low cost.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an absolute signal generating method according to the present invention will be described below in detail with reference to the drawings.

In FIG. 1, a signal denoted by reference numeral 1 is an A-phase (sin ωθ) signal 2 and a B-phase (cos ω)
θ) is an incremental encoder that outputs a signal 3, and these signals 2 and 3 are input to the correction synchronization circuit 4. The signals 2 and 3 obtained from the correction synchronization circuit 4 are input to the first direction discriminator 6 as a coarse incremental signal 5 of 12 bits (4096 C / T).

The coarse incremental signal 5 whose direction has been discriminated by the direction discriminating circuit 6 is input to a 12- to 14-bit coarse counter 7 and counted up or down.

The Z-phase signal 8 and the absolute signal 9 of the incremental encoder 1 are
And the load signal 11 is input at the same time. From the MSB signal 7a, which is the counter data obtained from the coarse counter 7, to the LSB signal 7
b is input to the serial converter 12.

The correction synchronizing circuit 4 is provided with a multiplying circuit 13, which is a fine incremental signal 14 (sin50 × ωθ, 262144C / T, 18) obtained by multiplying the coarse incremental signal 5 by, for example, 50 times. ) Is input to the 8-bit fine counter 16 via the second direction discriminating circuit 15 and counted up or down.

The LSB signal 7b of the coarse counter 7 is input to the reset terminal 16a of the fine counter 16 via the one-clock shift circuit 17, and the fine counter 16 receives the LSB signal 7B. It is a configuration that is reset every time.

The count data 16 of the fine counter 16
A is input to the serial converter 12. Therefore, the coarse and fine incremental signals 5 and 14 having different resolutions obtained as described above are combined with the coarse counter 7.
And the fine counter 16 are counted.
6 is reset by the LSB signal 7b of the coarse counter 7. Further, between the LSB signals 7b of the fine counter 7 is interpolated and divided as described later by the counter data 16A obtained by counting the fine incremental signals 14, so that a very high-precision (50 times) division capability can be obtained. , The serial absolute signal 12 from the serial converter 12
A is output.

The above-mentioned incremental signals 5, 5
The 14 pulse timings are completely synchronized by the correction synchronization circuit 4. Further, the MSB signal 7a, which is the counter data in the coarse counter 7,
Up to b, the power is turned on and preset by load data 10 (data of which absolute value is detected) by the absolute signal 9. The coarse and fine incremental signals 5 and 14 described above have waveforms shown in the timing chart of FIG. 2, and are obtained by being completely synchronized and multiplied by the correction synchronization circuit 4 and the multiplication circuit 13. . Therefore, as shown in the waveform of the timing chart of FIG. 2, a coarse area signal 7A composed of the MSB signal 7a, which is count data obtained from the coarse counter 7, and a fine area composed of count data 16A from the fine counter 16. By synthesizing the signal 16B in the serial converter 12, a serial absolute signal 12A can be obtained from the two types of incremental signals 5, 14.
Further, as shown in the waveform of the above-mentioned timing chart, the fine count data 16 is obtained by using the LSB signal from the coarse counter 7 obtained from the coarse incremental signal 5.
A is reset, and the fine incremental signal 14 is generated by multiplying the coarse incremental signal 5 by synchronizing with the coarse incremental signal 5 using the multiplying circuit 13 of a well-known multiplication method such as resistance interpolation. I have. That is, the interval between the LSB signals 7b of the coarse counter 7 is interpolated and divided by the fine incremental signal 14. As described above, an electrical interpolation method for obtaining an absolute signal having a resolution of 2 ⁿ is disclosed in Japanese Patent Laid-Open No.
No. 332816.

In the above-described embodiment, the case has been described where each of the incremental signals 5 and 14 is electrically obtained from the signal from one incremental encoder. For example, two incremental encoders are connected in series. The same effect can be obtained when incremental signals having different resolutions are obtained.

[0018]

The method for generating an absolute signal according to the present invention is configured as described above, so that the following effects can be obtained. That is, since an absolute signal is obtained by using two incremental signals having different resolutions, a high-resolution absolute encoder can be obtained at low cost. It is possible to obtain high precision that cannot be obtained by pattern formation of a disk.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a method for generating an absolute signal according to the present invention.

FIG. 2 is a timing chart showing each signal of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Incremental encoder 4 Correction synchronous circuit 5 Coarse incremental signal 7 Coarse counter 7a MSB signal (counter data) 7b LSB signal (counter data) 10 Load data 14 Fine incremental signal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01D 5/245

Claims (3)

(57) [Claims] 1. A coarse counter (7) to be inputted after discriminating the direction of a coarse incremental signal (5), and a fine incremental signal obtained by multiplying the coarse incremental signal (5) by several tens in a multiplying circuit (13). A fine counter (16) to be inputted after discriminating the direction of the signal (14), and the pulse timing of the coarse and fine incremental signals (5, 14) is
(4), the contents of the fine counter (16) are reset by the LSB signal (7b) of the coarse counter (7), and each LSB signal (7) of the coarse counter (7) is reset.
A method for generating an absolute signal, wherein the interval between b) is interpolated and divided by the fine incremental signal (14). 2. The counter data (7) of the coarse counter (7).
a, 7b) is the load data detected as an absolute value when the power is turned on.
2. The method for generating an absolute signal according to claim 1, wherein the method is preset in (10). 3. The coarse and fine incremental signals (5, 1
4. The method according to claim 1, wherein the step (4) is obtained from an incremental signal from one incremental encoder (1).
Or the absolute signal generation method according to 2.