JP2837147B2 - Separate forward converter for power - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an isolated power forward switching converter, and more particularly to a synchronous rectification forward converter.
ward converter).

[0002]

2. Description of the Related Art In a known forward switching power supply circuit using a synchronous rectifier, a secondary-side diode is replaced with a transistor to reduce a voltage drop in an on state. These transistors must be controlled to conduct from source to drain when the diode conducts from anode to cathode (for N-channel power MOSFETs), and conversely, when the diode conducts from cathode to anode. When shutting off in the direction toward the gate, the gate must be controlled so as to shut off the voltage from the drain to the source.

In these known synchronous rectifier circuits, the gate signal to these transistors must be synchronized as close as possible to the inflection points of the output inductor current, which is It corresponds to the zero crossing point of the square wave output inductor voltage. "Self-driving" these gate signals (ie, directly connecting the gate signals to the circuit), or "controlling and synchronizing"
(That is, the synchronization signal is extracted from a predetermined point of the circuit and supplied to the MOSFET gate driving circuit).

Conventional examples of synchronous rectifiers are disclosed in US Pat. No. 4,903,189 to Ngo et al., US Pat. No. 5,430,640 to Lee, US Pat. No. 5,457,624 to Hastings, and: Can be found in the dissertation. That is, Clemente
Synchronous Rectifiers Improve Efficie published in HFPC, May 1995 Proceedings, pp. 347-350.
ncy in Low Output Voltage forward Converters (synchronous rectifiers improve efficiency in low output voltage forward converters) and H by Digital (Jitaru)
FPC, May 1995 Proceedings, pp.1-10
e Impact of Low Output Voltage Requirements on Pow
er Converters (effects of low output voltage requirements on power converters).

In a conventional synchronous rectifier circuit, in order to synchronize gate control of a synchronous transistor, a control signal on a primary side is monitored and such a control signal is transmitted to a secondary side of a power converter (ie, a secondary side of a power converter). , Isolation boundary
(Forward). Unfortunately, maintaining isolation between the primary and secondary parts of the circuit requires complex circuits that are expensive and not optimal. For example, the use of optical isolators to maintain isolation introduces errors into the system due to undesired delays and unpredictable gain variations.

[0006] Other conventional synchronous rectifier circuits use additional transformer windings to synchronize the synchronization information to maintain isolation.
Transfer to the transistor of the next circuit. However, such transformers are more expensive and complex, and the transformer reset problem (t
ransformer reset problem).

Accordingly, a novel synchronous rectifier circuit that does not require an optical coupler or additional transformer winding to transfer synchronization information across the separation boundary between the primary and secondary circuits in a forward power converter. Is required.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to overcome the above disadvantages in conventional synchronous rectifier circuits, and is intended to overcome the separation boundary between primary and secondary circuits. It is an object of the present invention to provide a separated power forward converter using synchronous rectification that does not require an optical coupler for transferring synchronization information or an additional transformer winding.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention monitors the voltage across the output inductor of a converter so that one transistor is always on when the other transistor is off. The gates of these transistors are alternately controlled according to the voltage transitions across the output inductor (and vice versa).

[0010] That is, an isolated power forward switching converter according to the present invention includes a primary circuit connected to a primary winding of an isolated transformer, and a secondary circuit of the isolated transformer.
And a secondary circuit connected to a secondary winding. The secondary circuit is connected in series to the secondary winding at a first node, and is connected to an output capacitor whose output voltage is taken out from both ends. An output inductor connected at a second node, a first MOS gated transistor connected in series with the secondary winding and the output inductor, and forming a shunt from the first node to ground. A second MOS gate type transistor connected to the
And a synchronous rectifier control circuit connected to the second MOS gate type transistor, wherein a voltage between both ends of the output inductor is detected, and the first and second MOS gate type transistors are alternately switched according to the voltage. And a synchronous rectifier control circuit for turning on and off.

Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

[0012]

Referring now to the drawings, in which like numerals indicate like elements, FIG. 1 shows a synchronous rectifier 10 according to the present invention, which comprises a primary circuit 20 and a secondary rectifier. It has a circuit 30. The primary circuit 20 includes a voltage source Vin, a primary winding 11 of a transformer 12, a switch Sp, a reset winding 13 for resetting a core of the transformer 12, and a reset diode Dr.
Contains. Switch Sp is shown as a single pole, single throw switch for simplicity. However, in practice, this switch may be a MOS such as a power MOSFET or an insulated gate bipolar transistor (IGBT).
It may be a gate type (MOS-gated) semiconductor switch.

The secondary circuit 30 includes a secondary winding 14, an output inductor L, an output capacitor C, a first power transistor S1, and a second power transistor S2.
Each of the power transistors S1 and S2 has an anti-parallel diode between both ends.

To detect the voltage VL between both ends of the output inductor L, that is, to detect the potential difference between the potentials VA and Vout, a comparator 40 is connected to both ends of the output inductor L. This comparator 40 has an output connected to the gate of transistor S1 and an inverted output connected to the gate of transistor S2.

When the voltage VL across the inductor L is positive, the transistor S1 is turned on and the transistor S2 is turned off. Conversely, when the voltage VL is negative, the transistor S2 is turned on and the transistor S1 is turned off.

Thus, rectifier 10 has two modes of operation. In mode 1, which is the first mode, the transistor S1 is turned on to conduct current, and the transistor S2 is turned off to cut off current. In mode 2, which is the second mode, the transistor S1 is turned off to cut off the current, and the transistor S2 is turned on to conduct the current.

Mode 1 can be better understood by referring to the equivalent circuit shown in FIG. In FIG. 2, Vs represents the voltage across the secondary winding 14, the transistor S1 is represented by an ideal diode S1, and the output voltage is represented by an output voltage source Vo. The relationship between the various voltages is as follows. That is, Vs = VL + Vo, and VL = Vs-Vo. Vs
Is greater than Vo, so VL is positive.

Further, IL in mode 1 is increasing, that is, increasing. Therefore, di / dt is positive.
Since VL = L (di / dt), this analysis also indicates that VL is positive in mode 1.

Mode 2 in which the transistor S1 interrupts the current and the transistor S2 conducts the current can be represented by an equivalent circuit shown in FIG. In FIG.
Transistor S2 is represented by an ideal diode S2. As in the equivalent circuit for mode 1, Vs = VL + Vout, so VL = Vs-
Vout. Here, VL is negative because VA is zero volts and smaller than Vout. Also, in mode 2, IL is decreasing, ie, falling. Therefore,
di / dt is negative. Since VL = L (di / dt), this analysis also indicates that VL is negative in mode 2.

FIG. 4 shows the waveforms at different points of the circuit of FIG. 1 during operation. Next, referring to FIG. 5, there is shown a detailed configuration example of the comparator 40 shown in FIG.
The comparator 40 includes a non-inverting transistor comparator Q1,
The (push-pull) driving transistors Q3 and Q4 connected thereto, the inverting transistor comparator Q2, and the (push-pull) driving transistor Q5 connected thereto.
And Q6. Transistors Q1 and Q2
Responds to a voltage Vsense referenced to a ground point (ground), which varies as a function of VL and VA.

In mode 1, VA is greater than Vout (ie, VA = Vin · (Ns / Np)) and therefore Vse
nse is a positive voltage approximately equal to Vout + VfD1. Here, VfD1 is a forward voltage drop of the diode D1.
As a result, the transistor Q1 is turned on and the transistor Q2 is turned off. Therefore, the output from the emitter of transistor Q1 is a positive voltage, which turns on Q3 and turns off Q4. Therefore, the voltage at the gate of the transistor S1 is approximately Vz
It rises to z, and the transistor S1 turns on. Conversely, the output from the collector of transistor Q2 is approximately zero volts, which turns on Q6 and turns on transistor S2.
To carry off the charge of the gate of the transistor and turn off S2.

In mode 2, VA is less than Vout (ie, VA ≒ 0 volts) and therefore Vsen
se = VA ≒ 0 volts. As a result, the transistor Q1
Is turned off, and the transistor Q2 is turned on. Therefore, the output from the collector of transistor Q2 is a positive voltage, which turns on Q5 and turns off Q6. Therefore, the voltage at the gate of the transistor S2 rises to almost Vzz, and the transistor S2 turns on. Conversely, the output from the emitter of transistor Q1 is approximately zero volts, which turns on Q4 and carries away the charge on the gate of transistor S1 and turns off S1.

In this way, the gating of the gates of transistors S1 and S2 is controlled by the voltage V across inductor L.
It is a function of L. That is, when VL is positive, transistor S1 is turned on (the voltage of the gate of S1 to its source is positive), and transistor S2 is turned off (the voltage of the gate of S2 to its source is reduced (goes low). )). On the other hand, when VL is negative, transistor S1 is turned off and transistor S2 is turned on.

The gates of these transistors are advantageously "self driven" by detecting the state of secondary circuit 30, ie, inductor voltage VL. Thus, an expensive (with gain variation), unpredictable and slow opto-isolator, or transformer 12
No additional windings are required. In addition, efficient use of discrete components eliminates the need for expensive integrated circuit type comparators.

Diode D1 is advantageously connected to Vout
It should be noted that the voltage of Vsense above is limited to one diode drop, which also limits the voltage applied to transistors Q1 and Q2. Therefore, this circuit is not affected by back oscillation at the peak value of VA (is immune to back oscillation). This is because such a peak value is not fed back in the circuit of the present invention. Also, by limiting the maximum excursion (bias) of Vsense to approximately Vout, these transistors can be turned on when Vout is under voltage (ie, when Vout is less than 1).
The converter is turned off, which contributes to improving the starting characteristics of the converter.

The diode D1 includes transistors Q1 to Q6.
Allow an extra diode drop in the drive voltage to drive (i.e., Vsense = Vout + VfD).
It should be noted that 1). Nevertheless, if Vout is designed to have a very low output that does not provide an appropriate drive voltage to transistors Q1-Q6, the cathode of diode D1 may be connected to Vzz. In this way, a higher voltage will be obtained to drive transistors Q1-Q6 (ie, Vsense = Vzz + VfD).

Capacitors C1 and C2 are used to introduce respective time delays in the circuits of Q1 and Q2 to provide the required dead time.

The reason for providing the dead time is as follows. That is, the gate signal of the synchronous rectifier must be synchronized as close as possible to the VL transition (ie, the zero-crossing point). If the period during which each gate is turned on is too long (that is, if it is turned on early and turned off late), S
Overshoot or oscillation of the current occurs due to cross conducting between 1 and S2. If each gate is turned on too late or turned off too soon, the anti-parallel diode of the power MOSFET will conduct, causing greater conduction losses while it conducts, and Reverse recovery effect when turned off when the voltage changes to the opposite polarity
Occurs.

Therefore, to avoid mutual conduction, V
When A is larger than Vout, the transistor S1 turns on after a predetermined dead time, and the transistor S2 turns off. Conversely, when VA is smaller than Vout, transistor S1 turns off and transistor S2 turns off after a predetermined dead time. Advantageously, the length of the dead time can be predetermined in view of the different types of power MOSFETs depending on the design.

The resistor R8, the capacitor C3, and the diode D2 play a role as a driving power supply or an auxiliary power supply for DC power. Instead, the transistor S1
And Vout is high enough to provide a sufficient drive voltage to the gates of transistors S1 and S2 to reduce the forward resistance of S1 and S2 (ie, to make transistors S1 and S2 fully conductive). , Vout can be used as Vzz.

The resistor R8 serves as a bleeding resistor for charging the capacitor C3. Capacitor C3 supplies current to the circuit and maintains voltage Vzz based on breakdown voltage VD2 of Zener diode D2. If VA is greater than VD2,
Vzz is approximately equal to the breakdown voltage of Zener diode D2. On the other hand, when VA is smaller than VD2, Vzz is substantially equal to the peak value of VA.

Conveniently, this Vzz supply requires that the power MOSFETs be at a voltage high enough to make the power MOSFETs fully conductive and reduce their forward resistance.
It is possible to drive the FET. This alleviates the need for additional windings or power supplies in the transformer.

FIG. 6 shows another embodiment 40 'of the comparator 40 shown in FIG. In the embodiment of FIG.
Instead of the bipolar transistors Q1 to Q6 shown in FIG.
ET transistors (MOS transistors) Q7 to Q11 are used. The operation of this embodiment essentially corresponds to FIG.
This is the same as the embodiment. More specifically, when VA is larger than Vout, a high voltage (High voltage) is input to the gate of the transistor S1, and a low voltage (Low voltage) is input to the gate of the transistor S2. Conversely, when VA is smaller than Vout, the transistor S
A low voltage (Low voltage) is input to one gate, and a high voltage (High voltage) is input to the gate of the transistor S2.

Although the present invention has been described with respect to particular embodiments thereof, it will be apparent to those skilled in the art that many other variations, modifications, and other uses are possible. Accordingly, the invention is not limited to the specific disclosure herein.

[Brief description of the drawings]

FIG. 1 is a circuit diagram partially illustrating a synchronous rectifier according to the present invention in the form of a block diagram.

FIG. 2 is a diagram showing an equivalent circuit of the secondary circuit of FIG. 1 in a first operation mode.

FIG. 3 is a diagram showing an equivalent circuit of the secondary circuit of FIG. 1 in a second operation mode.

FIG. 4 is a diagram showing waveforms at various points during operation in the circuit of FIG. 1;

FIG. 5 is a circuit diagram of the circuit of FIG. 1 including the comparator shown in the block diagram of FIG. 1 and showing the configuration of the comparator in detail.

FIG. 6 is a circuit diagram showing another embodiment of the comparator shown in FIG. 5;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Primary winding 12 ... Transformer 14 ... Secondary winding 10 ... Rectifier 30 ... Secondary circuit 40 ... Comparator S1 ... 1st power transistor S2 ... 2nd power transistor L ... Output inductor C ... Output capacitor R1 ... Resistance R8: Resistance D1: Diode D2: Zener diode C3: Capacitor Vzz: Breakdown voltage of Zener diode Q1: Non-inverting transistor comparator (bipolar transistor) Q2: Inverting transistor comparator (bipolar transistor) Q3, Q4: Driving transistor (bipolar) Q5, Q6: Driving transistor (bipolar transistor) Q7: Non-inverting transistor comparator (MOS transistor) Q8, Q9: Driving transistor (MOS transistor) Q10, Q11: Driving transistor (MOS transistor)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-298610 (JP, A) JP-A-63-245261 (JP, A) JP-A-4-58087 (JP, U) (58) Survey Field (Int.Cl. ⁶ , DB name) H02M 3/00-3/44 H02M 7/21

Claims (9)

(57) [Claims] 1. A power supply connected to a primary winding of a separated type transformer.
A secondary circuit connected to a secondary winding of the separation type transformer, wherein the secondary circuit is connected in series to the secondary winding at a first node. An output inductor connected at a second node to an output capacitor from which an output voltage is taken out from both ends; a first MOS gate transistor connected in series to the secondary winding and the output inductor; A second MOS gate type transistor connected to form a shunt from a node of the second MOS gate type to ground; and a synchronous rectifier control circuit connected to the first and second MOS gate type transistors. Detecting a voltage between both ends of the inductor;
And a synchronous rectifier control circuit for alternately turning on and off a second MOS gated transistor and limiting the detected peak value of the voltage across the output inductor to the output voltage. Separate forward switching converter. 2. The forward switching converter of claim 1, wherein one end of a resistor is connected to the first node, a cathode of a diode is connected to the second node, and An isolated forward switching converter for power, wherein an anode is connected to the other end of the resistor at a third node, and a detected voltage across the output inductor is obtained from the third node. 3. The isolated forward switching converter for electric power according to claim 1, wherein said secondary circuit further comprises a DC auxiliary voltage source, wherein said DC auxiliary voltage source is taken out from both ends of a Zener diode. An isolated forward switching converter for power, wherein the Zener diode is connected to the first node via a blocking diode and a current limiting resistor. 4. The isolated forward switching converter for electric power according to claim 3, wherein a detected peak value of a voltage across the output inductor is limited to at least the output voltage or the DC auxiliary voltage source. Separate forward switching converter for power. 5. The isolated forward switching converter for power according to claim 4, wherein one end of a resistor is connected to the first node, a cathode of the diode is connected to the DC auxiliary voltage source, and An isolated forward switching converter for power, wherein an anode is connected to the other end of the resistor at a third node, and a detected voltage across the output inductor is obtained from the third node. 6. The separated forward switching converter for electric power according to claim 1, wherein the detected voltage is supplied to a non-inverting detecting circuit and an inverting detecting circuit. 7. The separated forward switching converter for power according to claim 6, wherein the non-inverting detection circuit has a non-inverting amplifier connected to a first driving circuit, and the driving circuit is Connected to the gate of a first MOS gate type transistor, wherein the inversion detection circuit has an inversion amplifier connected to a second drive circuit, and wherein the second drive circuit comprises the second MOS gate type transistor A separate forward switching converter for power connected to the gate of 8. The separated forward switching converter for power according to claim 7, wherein the non-inverting amplifier includes a bipolar transistor connected in the form of an emitter follower, and the first driving circuit includes a bipolar transistor. The inverting amplifier includes a bipolar transistor, and the second driving circuit includes a bipolar push-pull transistor pair. 9. The separated forward switching converter for power according to claim 7, wherein the non-inverting amplifier has a MOS gate type transistor, and the first driving circuit is a MOS gate type push-pull transistor. A separated forward switching converter for power, comprising: a pair; an inverting amplifier having a MOS gate type transistor; and the second drive circuit having a MOS gate type push-pull transistor pair.