JP2824484B2 - Pipeline processing computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly, to a data processor for checking a data dependency between an instruction executed before and an instruction executed after the preceding instruction. The present invention relates to a pipeline processing computer provided with a scoreboard.

2. Description of the Related Art In a computer that performs a pipeline process, a data dependency between an instruction to be executed in advance and an instruction to be executed following the preceding instruction, for example, a result of an operation by the first instruction is described as follows. When there is a relationship that is used as operation data in the instruction, it is necessary to perform processing that does not disturb the dependency. As a control method for managing the interdependency of the data used for the calculation, there is a method using a scoreboard.

[0003] In this method, a scoreboard is provided as storage means for indicating use / unused in correspondence with each of the general-purpose registers. When an instruction that needs to write to a general-purpose register is executed, the bit of the scoreboard corresponding to the register number is set to indicate that writing to the register is performed. When a result is written to a general-purpose register by a certain instruction, the bit of the scoreboard corresponding to the register number is reset to indicate that the writing is completed.

In a subsequent instruction, a bit of a scoreboard corresponding to a register number storing operation data is read in order to confirm whether or not the register executed by the previously executed instruction is rewritten. If it is set, it means that the rewriting by the previously executing instruction has not been completed, so the following instruction
It is necessary to wait for the operation to start. If the scoreboard bit is reset, the previously executing instruction will not rewrite the contents of the register, i.e., the subsequent instruction will wait for the operation to start, resulting in the register being updated by the previously executing instruction. Since the rewriting has been completed, the operation of the subsequent instruction can be started.

The necessity of processing using a scoreboard will be described with reference to FIGS. 7 and 8. FIG. 7 shows that there is a case where the mutual relation of data cannot be correctly processed without waiting for the completion of writing to the register by the preceding instruction. In the figure, a first multiplication instruction (multi)
Shows an instruction for multiplying the content (gr2) of the register 2 by the content (gr3) of the register 3 and storing the result in the register 4, and an addition instruction (ad
In d), an instruction to add the contents of the register 5 and the contents of the register 6 and store the result in the register 4 is shown. In addition, an addition instruction as a third instruction which is a little away from the position is an addition as a second instruction. The instruction to add the contents of the register 4 storing the result of the instruction and the contents of the register 7 and store the result in the register 8 is shown. In this case, if the processing is executed without using the scoreboard, as shown in the figure, for example, in the multiplication instruction as the first instruction, the operation execution (E) stage is 3
Because of the stage, in the processing of the addition instruction as the third instruction, the contents of the register 4 storing the result of the multiplication instruction as the first instruction are read out, and the addition is executed. The result will be obtained.

FIG. 8 shows a process in a case where a subsequent instruction waits for completion of data writing to a register by a preceding instruction.
In the figure, the scoreboard bit for the register 4 is set to "1" at the first execution (E) stage of the multiplication instruction as the first instruction, and the result is written to the register 4, and the scoreboard bit is set to "1". The execution of the second addition instruction is interlocked until it becomes 0 ', that is, until the reset is performed, indicating that the processing of reading out the correct data is performed in the processing of the second addition instruction.

Setting a bit in the scoreboard indicates that the value of the register cannot be read (written). Many execution stages of a basic instruction such as an addition instruction generally have only one execution stage, and the result generated in the execution stage by the bypass function can be read as data. For an instruction whose execution stage ends in one stage, there is no possibility that the subsequent instruction will overtake an erroneous operation as shown in FIG. Therefore, in the case of a basic instruction such as an addition instruction, that is, an instruction which can be executed in one flow and takes only one stage and has the shortest execution time, mutual interference of data is prevented without setting / resetting the scoreboard. Can do it.

FIG. 9 is a block diagram showing the configuration of a conventional pipeline computer using a scoreboard. In FIG. 1, a pipeline computer includes an instruction decoder 1 for decoding an instruction code, a general-purpose register (GR) 2 for storing operation data and operation results, for example, an operation unit 3 as an adder,
For example, an arithmetic unit 4 as a shifter, operation data for the arithmetic unit 3, that is, operand registers 3a and 3b for holding operands, operand registers 4a and 4b for holding operands for the arithmetic unit 4, a scoreboard 5, and a pipeline operation are controlled. A pipeline controller 6, a pipeline tag register 7 for holding a pipeline tag under the control of the pipeline controller 6,
And an AND circuit 8.

In FIG. 9, an instruction code is decoded by an instruction decoder 1 to obtain a source register address 0 and a source register address 1 as read register numbers and a destination register address as a write register number. Read data 0 and read data 1 are input to the read register port of GR2 and held as operand data in the operand registers 3a, 3b, 4a, and 4b. The outputs of these operand registers are input to arithmetic units 3 and 4, and the operation result is input as write data to the write data port of GR2. Simultaneously with this operation result, the destination register address as the write register number is input to the write register port of GR2 as the write register address, with the timing adjusted by the pipeline tag register 7. The write control signal is also generated by the instruction decoder 1 and is input to the GR 2 with the timing adjusted by the pipeline tag register 7, but this control signal is not shown.

The above is the operation in the case where there is no mutual interference of data. If there is mutual interference of data, the read register number and the write register number output from the instruction decoder 1 are read from the read register of the scoreboard 5. The check ports (RD0 CHK, RD1 CHK) and the write register check port (WR CHK) are input to the check ports, and these register numbers are used as selection signals for selecting registers in the scoreboard 5 indicating busy / unused. Used. Signal SRC0 REG BUSY, SRC1 REG B from selected register
USY and WR REG BUSY are input to the pipeline controller 6 and are used to determine whether to interlock the decode stage as shown in FIG.

The above-mentioned 3 to the pipeline controller 6
If one of the two signals indicates that the scoreboard bit is '1', the output of the D stage release signal, ie, the signal indicating that the decoding stage can be completed and the execution stage can be performed, is suppressed. Is done.

In the preceding instruction, for example, the writing to the register is completed, the register indicating whether the scoreboard 5 is in use or unused is reset, and all of the above three signals to the pipeline controller 6 are output. If the result indicates that the scoreboard bit is not set, the D stage signal is output to the four operand registers and the signal is output to the clock enable terminal of the D flip-flop in the pipeline tag register 7. And an AND circuit 8 in front of the scoreboard 5.

The execution stage processing for the subsequent instruction is thereby performed. At this time, the destination register address from the instruction decoder 1 provided as the other input of the AND circuit 8 is supplied to the WR SET terminal of the scoreboard 5. And the bit of the scoreboard corresponding to the write register number is set. Furthermore,
When the E-stage release signal output from the pipeline controller 6 is input to the pipeline tag register 7, the destination register address is set as the write register address and the WR RE of the scoreboard is used.
The signal is applied to the S terminal, the corresponding scoreboard bit is reset, and the write register address is applied to GR2 as described above.

[0014]

Before describing the problems to be solved by the present invention, first, multiflow processing and use of a scoreboard at the time of executing instructions in parallel will be described. The multi-flow processing is also referred to as a stage development processing, and is a processing in which one instruction is divided into a plurality of flows and executed as if they were a plurality of instructions.

For example, when executing an instruction to transfer the value of two 4-byte general-purpose registers (GR) as a pair to an 8-byte floating-point register (FR), only one port is used on the general-purpose register side. Multi-flow processing is to read four bytes at a time and transfer it to the floating-point register twice. FIG.
Is an example of this processing, and shows how the contents stored in the register pair indicated by r1 and r1 + 1 are transferred in two flows.

FIG. 11 shows an example of multiflow processing for a multiplication instruction. Generally, the execution frequency of the multiplication instruction is low, and even if the performance is reduced, the influence on the performance of the entire system is small. Therefore, in FIG. 11, two operation data for multiplication are transferred to the multiplier in two separate flows, whereby the bus width of the data bus for transferring the operation data is reduced.

However, FIG. 12 shows an example in which a hang-up state occurs when a scoreboard is set in a multiplication instruction for performing such multiflow processing. FIG. 12 shows a state in which the contents of the register 2 are multiplied by the contents of the register 3 and the multiplication instruction for storing the result in the register 3 is executed in two flows. First, in the first flow, the contents of the register 2 are sent to the multiplier. In order to store the multiplication result in the register 3, the scoreboard bit corresponding to the register 3 is set in the execution stage of the first flow. . For this reason, even if an attempt is made to read the contents of the register 3 in the second flow, the reading cannot be performed because the bit of the scoreboard is set, and an interlock state is set. This scoreboard bit is reset by writing to register 3, but is not reset until the result of the execution stage of the second flow is obtained, and is permanently set because the second flow is interlocked in the decoding stage. It cannot be reset, resulting in a hang-up state. Such a hang-up state is a hard failure state, also called a deadlock, and is a state that cannot be resolved forever. In contrast, in the interlock state shown in FIG. 8, the processing is restarted by resetting the scoreboard bit.

Next, problems at the time of parallel execution of instructions will be described. FIG. 13 is an explanatory diagram of the problem. In this example, the addition instruction and the multiplication instruction are executed in parallel. In the addition instruction, the contents of the register 1 and the contents of the register 2 are added and stored in the register 3, and in the multiplication instruction, the contents of the register 2 and the register 3 are added. And the result is stored in the register 4 . Of these instructions, the add instruction ends in the first three stages, while the multiply instruction is split into two flows, ie, performed as a multi-flow operation.

In order to avoid the problem described with reference to FIG.
For example, even if the scoreboard bit is set when reading the contents of the register 3 in the second flow of the multiplication instruction,
At this time, the result of the addition instruction is stored in the register 3, and the processing of the multiplication instruction is performed using this addition result. As described above, for parallel execution of instructions, a scoreboard bit is set in consideration of data interdependency, and execution of a basic instruction as an instruction having the shortest execution time is performed in consideration of data interdependency. There is a problem that it is necessary to delay.

According to the present invention, when an instruction requiring multi-flow processing is executed, processing is performed while maintaining the interdependency of data by the scoreboard correctly, and instructions which can be executed by a single flow and multi-flow processing are executed. An object of the present invention is to enable correct processing to be performed without impairing the interdependency of data during parallel execution with a required instruction.

[0021]

FIG. 1 is a block diagram showing the principle of the present invention. The figure includes a scoreboard for checking a data dependency between an instruction executed in advance and an instruction executed in succession to the preceding instruction, and one instruction is divided into a plurality of flows. FIG. 2 is a block diagram showing the principle of a pipeline processing computer that can be executed by a computer.

In FIG. 1, the final flow detecting means 10
Is a multi-flow controller, for example, for detecting the final flow of multi-flow processing as processing for executing one instruction by dividing it into a plurality of flows. The scoreboard update control means 12 is, for example, the scoreboard 1
The two AND circuits provided on the input side of the input unit 1 update the contents stored in the scoreboard 11 corresponding to the above-described data dependency in the final flow of the multiflow processing.

[0023]

According to the present invention, the processing for updating one instruction divided into a plurality of flows, that is, the update processing of the content stored in the scoreboard, that is, the set / reset processing is performed only in the final flow of the multi-flow processing. The operation of the present invention will be described with reference to FIG.

As described with reference to FIG. 1, in the present invention, when the final flow detecting means 10 detects the final flow of the multiflow processing, for example, the score corresponding to the register in which the result of executing the instruction of the flow is written. The board bit is set. This set is performed by the scoreboard update control means 12. In FIG. 2, the same instruction as in FIG. 12 is processed, but in FIG. 12, when it is determined that the multiplication result is stored in the register 3 in the first flow, the scoreboard is executed in the execution stage of the first flow. Although the bit is set to '1', the scoreboard is set in the second flow in FIG. 21, that is, in the first execution stage of the final flow.
As a result, the content of the register 3 is transferred to the general-purpose register GR in the first execution stage of the second flow, and thereafter, when the multiplication process is executed and the multiplication result is stored in the register 3, the scoreboard bit is set to “0”. Is reset to

As described above, in the present invention, the scoreboard set /
Reset processing is performed. As a result, processing that does not disturb the data dependency between the preceding instruction and the succeeding instruction is guaranteed by the processing including the pipeline interlock.

When simultaneously executing an instruction that requires multiflow processing and an instruction that does not require multiflow processing, the scoreboard set / reset processing is performed in the final flow of the multiflow processing, and the instruction that does not require multiflow processing is executed. Is also delayed until the final flow of the multi-flow process.

[0027]

FIG. 3 is a block diagram showing the overall configuration of a pipeline processing computer according to the present invention. In this figure, the same parts as those in the conventional example of FIG. 9 are denoted by reference numerals. 3 differs from the conventional example of FIG. 9 in that a multiflow controller 20 for detecting the final flow in the multiflow processing is added, and an AND circuit 21 is provided on the input side of the scoreboard 5 instead of the AND circuit 8. , And a new AND circuit 22
Is provided.

The multi-flow controller 22 receives from the instruction decoder 1 a two-flow operation indicating that the multi-flow is divided into two flows or a three-flow operation signal indicating that the multi-flow is divided into three flows. Also, a D stage release signal is input from the pipeline controller 6. Then, the last flow detection signal from the multi-flow controller 20 is input to the two AND circuits 21 and 22, and the flow counter signal is output to the instruction decoder 1. A destination register address indicating a write register number and a D stage release signal are input to the AND circuit 21 as well as the last flow detection signal as in FIG. A register set input is provided. The AND circuit 22 is supplied with a write register address from the pipeline tag register 7 together with the last flow detection signal. When these signals are completed, a write register reset signal is input to the scoreboard 5.

An outline of the processing of each stage in FIG. 3 will be described. First, in the decode (D) stage, the instruction is decoded to determine that the instruction is a multi-flow instruction, the number of flows required for executing the instruction, and that the instruction requires updating of the scoreboard. The result of decoding, the value of the multiflow counter, and the like are stored in the pipeline tag, and used in the subsequent stages.

The number of bits of the scoreboard corresponding to the write register number is checked, and if set, interlock is performed in the instruction decode stage. Check the number of bits of the scoreboard corresponding to the read register number,
If set, interlock at the instruction decode stage.

In the case of a multi-flow instruction, the output of the multi-flow counter indicating the current flow of processing indicates a value equivalent to executing the first flow whenever the instruction is not a multi-flow instruction. ing. Further, in order to detect the final flow, the value of the multiflow counter is compared with the number of flows required for executing the instruction. If the instruction is not a multi-flow instruction, the multi-flow counter always indicates a value equivalent to executing the first flow, so that the final flow is detected.

In the operation execution (E) stage, in addition to the execution of the operation, if the instruction that is executing the operation stage is an instruction that requires updating of the scoreboard and the final flow is being executed, the instruction corresponding to the write register number is executed. Set the scoreboard bit. For some instructions, register reading may be performed at this stage.

In the write (W) stage, in addition to processing such as writing the result obtained in the operation stage to a register, the instruction executing the write (W) stage is an instruction that requires updating of the scoreboard, and If the final flow has been executed, the bit of the scoreboard corresponding to the write register number is reset.

FIG. 4 is a block diagram showing an embodiment of the multi-controller. In FIG.
0 is a two-flow operation from the instruction decoder 1,
And an OR circuit 23 to which a three-flow operation signal is input, an inverter 24 to which an output of the OR circuit 23 is supplied, an AND circuit 25 to which a D-stage release signal and a clock signal output from the pipeline controller 6 are input, and a flow counter 26 , An AND circuit 27 to which the output of the flow counter 26 and the two-flow operation signal are inputted, an AND circuit 28 to which the output of the flow counter 26 and the three-flow operation signal are inputted, and the outputs of the inverter 24 and the AND circuits 27 and 28 are inputted. And an inverter 30 for inverting the output of the OR circuit 29.

In FIG. 3, the instruction decoder decodes how many flows the instruction to be executed is composed.
In the case of a multi-flow instruction, FLOW COUNTE
The value of R indicates the flow number of the instruction currently being executed, and detects that it is the last flow (LAST
FLOW signal), if it is the final flow, the update control of the program counter and the selection of an instruction from the instruction buffer (queue) are performed.

The instruction decoder is a FLOW COUNTER
The decoding result is partially changed for the same instruction depending on the flow using the value of. For example, in the transfer from GR to FR described with reference to FIG. 10, two registers are read by giving different register numbers to the read register numbers for the first and second flows.

In FIG. 4, the instruction decoder 1 does not output a two-flow operation signal and a three-flow operation signal for an instruction processed by a single flow other than the multi-flow processing, and the output of the OR circuit 23 becomes' 0, the output of the inverter 24 becomes '1', and the output of the OR circuit 29 indicates that the flow is the last flow.

On the other hand, when the multi-flow process includes two flows, the instruction decoder 1 supplies a two-flow operation signal to the uppermost input terminal of the AND circuit 27. Therefore, the output of the AND circuit 27 becomes "1" when "1" is given to the second input terminal from the top and "0" is given to the third input terminal, and the output of the OR circuit 29 indicates the last flow. become. That is, at this time, the output of the flow counter is “01”. AND circuit 2
5, the D-stage release signal from the pipeline controller 6 is input together with the clock signal, and if the D-stage release signal is given when the clock signal rises, the output of the flow counter 26 is incremented. When the flow in the multi-flow process is “2”, the output of the flow counter 26 is “0” for the first flow, and the D stage indicating that the D stage of the second flow has been completed When the release signal is input, the output of the flow counter 26 becomes “1”. As a result, the OR circuit 29 outputs a last flow detection signal.

If the multi-flow processing consists of three flows, a three-flow operation signal is applied to the top input terminal of the AND circuit 28,
Becomes "1" when the input to the second input terminal is "0" and the input to the third input terminal is "1". That is, the output of the flow counter 26 is “2”, that is, “10” when the D stage release signal is input for the third flow, and at this time, the OR circuit 29 outputs the last flow detection signal. .

In FIG. 4, when the D-stage release signal is "1" and the last flow detection signal is "1" at the time of rising of the clock signal, that is, after the last flow is detected, the first multi-flow process is started. The flow counter is reset when the D stage release signal is output with respect to the flow of, and the flow counter is incremented when the D stage release signal is "1" at the rise of the clock signal and the last flow detection signal is "0". It shows that the output of the flow counter does not change when the D-stage release signal is "0" at the rising of the clock signal. This operation is performed by the inverter 30.

FIG. 5 is a block diagram showing an embodiment of a scoreboard according to the present invention. In the figure, the scoreboard comprises two 4-input 16-output decoders 33, 34, 16 SR flip-flops 35, and three 16-input 1-output selectors 36, 37 and 38.

In FIG. 5, the decoder 33 sets one of the 16 SR flip-flops 35 upon input of the D stage write enable signal (DWE) in accordance with the contents of the 4-bit WR SET signal from the AND circuit 21. The decoder 34 resets one of the SR flip-flops 35 according to the contents of the 4-bit WR RES signal output from the AND circuit 22 when the W stage write enable signal (W WE) is input.

Next, the selector 36 reads the read register number SRC_REG_AD output from the instruction decoder 1.
SRC0 which supplies one of the outputs of 16 SR flip-flops 35 to pipeline controller 6 according to the contents of input signal RD0 CHK4 bits to score board read register test port as R0 signal
It is output as a REG BUSY signal. Similarly, the register 37 outputs one of the 16 flip-flops 35 according to the contents of the 4-bit input signal RD1 CHK to the read register test port SRC1.
The selector 38 outputs the REG BUSY signal to the pipeline controller 6, and the selector 38 outputs one of the outputs of the 16 flip-flops 35 as the WR REG BUSY signal according to the contents of the 4-bit input signal WR CHK to the write register inspection port. Output to the controller 6.

FIG. 6 is a block diagram showing the configuration of an embodiment of the pipeline controller. In FIG. 3, the pipeline controller 6 has three BUSs from the scoreboard 5.
The Y signal and other interlock condition signals are provided, and the three BUSY signals and other D stage interlock condition signals are input to the OR circuit 40. The output of the OR circuit 40 and a D stage valid signal, that is, a signal indicating that there is an instruction executing the D stage, and an output of an AND circuit 45 described later are input to the AND circuit 41. The output of the AND circuit 41 is a D stage release signal indicating that the instruction executing the D stage has been completed. The value of the output is a D stage valid signal of “1”, and the value of the OR circuit 40 and the AND circuit 45 It becomes '1' when both outputs are '0'. That is, even if the D stage valid signal is "1" and the D stage is valid, the OR circuit 40 outputs "1" and the D stage interlock condition exists, or the AND circuit 45 outputs "1". When the instruction being executed in the E stage is interlocked, the output of the AND circuit 41 is "1".
Does not. This is because, for example, if an instruction executed in the D stage advances to the E stage, the register interlocked in the E stage is not completed, for example, the register is overwritten. The interlock by the board inspection is considered as one of the D interlock conditions.

The D-stage release signal as the output of the AND circuit 41 is supplied as an E-stage valid signal via the flip-flop 42, that is, a signal indicating that there is an instruction executing the E-stage by the end of the D-stage. 43 and 45. The AND circuit 43 includes the pipeline controller 6 in FIG.
E as another interlock condition signal to
A stage interlock condition signal and an output of an AND circuit 48, which will be described later, are provided. These two signals are supplied to an AND circuit 45 via an OR circuit 44.
Has been given to. That is, the output of the AND circuit 45 is
As described above, it indicates that the instruction executed at the E stage is interlocked by the E stage interlock condition.

The output of the AND circuit 43 is such that the E stage valid signal is “1” and both the E stage interlock condition signal and the output of the AND circuit 48 are “0”.
It becomes '1' when. The output of the AND circuit 43 indicates the E stage release signal, that is, the completion of the instruction executing the E stage, and similarly to the D stage release signal, even if the E stage is valid, the E stage interlock condition Or W
If the instruction to be executed in the stage is interlocked, its value will not be '1'. That is, when the instruction executed in the E stage advances to the W stage, for example, the register is overwritten without completing the instruction interlocked in the W stage.

The output of the AND circuit 43, that is, the E stage release signal is supplied to the AND circuit 47 via the flip-flop 46 as a W stage valid signal indicating that there is an instruction executing the W stage. The AND circuit 47 is supplied with a W stage interlock condition signal. When the W stage valid signal is “1” and the W stage interlock condition signal is “0”, the AND circuit 47 outputs a W stage release signal. , That is, a signal indicating that the instruction executing the W stage is completed. On the other hand, the W stage valid signal and the W stage interlock condition signal are input to the AND circuit 48,
When these are "1", the output of the AND circuit 48 is "1", and the output is as described above.
And an OR circuit 44.

Next, an embodiment of the present invention at the time of executing a parallel instruction will be described. In order to solve the problem described with reference to FIG. 13, when an instruction requiring multi-flow processing and an instruction only for a single flow are executed in parallel, the scoreboard of the final flow of the multi-flow processing is used. In addition to performing set / reset, it is necessary to delay execution of instructions of only a single flow until the time of its final flow.

Therefore, for example, when a load instruction (memory access instruction) and a multiplication instruction are executed simultaneously, execution of the load instruction as a single flow and set / reset of the scoreboard are delayed until the final flow of the multiplication instruction. As a result, it is possible to perform a process for preventing data interference.

In the embodiment described above, the data used for the operation is two, so that the read register has two data.
Although the description has been made of the case where the number of write registers is one, the number of these data and the number of registers is not limited to this. These register numbers (addresses)
Is 4 bits, and therefore, the case where the number of flip-flops in the scoreboard in FIG. 5 is 16 has been described. However, it is needless to say that the number of these bits and the number of flip-flops are not limited thereto. Further, the multiflow controller of FIG. 4 has been described with the number of flows of the multiflow being 2 or 3, but the number of flows of the multiflow processing is not limited to this.

[0051]

As described above in detail, according to the present invention, even in a multi-flow process in which one instruction is divided into a plurality of flows and processed, the interdependency of data is broken by using a scoreboard. Processing can be performed without instructions, and even when instructions are executed in parallel, a set of scoreboards /
By performing the reset in the final flow and delaying the execution of an instruction that does not require multiflow processing until the final flow, it is possible to solve the mutual interference of data.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing a state of execution of a multiplication instruction in the present invention.

FIG. 3 is a block diagram illustrating a configuration of an embodiment of a pipeline processing computer according to the present invention.

FIG. 4 is a block diagram illustrating a configuration of an embodiment of a multi-flow controller.

FIG. 5 is a block diagram showing a configuration of an embodiment of a scoreboard.

FIG. 6 is a block diagram illustrating a configuration of an embodiment of a pipeline controller.

FIG. 7 is a diagram illustrating an operation when a subsequent instruction does not wait for completion of a preceding instruction.

FIG. 8 is a diagram illustrating an operation of a process using a scoreboard.

FIG. 9 is a block diagram showing a configuration of a conventional example of a pipeline processing computer.

FIG. 10 is a diagram illustrating an example of multiflow processing.

FIG. 11 is a diagram illustrating an example of multiflow processing of a multiplication instruction.

FIG. 12 is a diagram illustrating an example of a hang-up state of a multiplication instruction.

FIG. 13 is a diagram illustrating a problem in parallel execution of instructions.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction decoder 2 General-purpose register (GR) 3, 4 Operation unit 5, 11 Scoreboard 6 Pipeline controller 7 Pipeline tag register 10 Final flow detection means 12 Scoreboard update control means 20 Multiflow controller

Claims (2)

(57) [Claims] 1. A scoreboard for checking a data dependency between an instruction executed before and an instruction executed after the preceding instruction, and a single instruction is transmitted to a plurality of flows. A pipeline processing computer that can be executed separately; a final flow detection means (10) for detecting a final flow of the plurality of flows; and a scoreboard corresponding to the dependency in the detected final flow. 12. A pipeline processing computer comprising: a scoreboard update control means (11) for updating the stored contents of (12), and guaranteeing processing without disturbing the dependency. 2. When at least one instruction executed in a plurality of flows is executed among instructions executed in parallel by the pipeline processing computer, an instruction executed in a plurality of flows is executed. In the final flow of the plurality of flows, the content stored in the scoreboard is updated. For an instruction that can be executed in a single flow, the execution of the instruction and the update of the content stored in the scoreboard are performed by 2. The pipeline processing computer according to claim 1, wherein a delay is made until a final flow of instructions to be executed by dividing into a plurality of flows.