JP2800741B2 - Power circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit for boosting or stepping down a constant power supply voltage, and more particularly to a low power consumption power supply circuit which suppresses voltage fluctuations during load operation.

[0002]

2. Description of the Related Art Conventionally, a power supply circuit using a charge pump circuit has been proposed.
FIG. 5 shows a basic configuration of a booster power supply circuit using a charge pump circuit disclosed in Japanese Patent Application Laid-Open No. H11-209,036. This power supply circuit generates a voltage V2 that is higher than a high-potential-side power supply voltage V1 supplied from the outside, detects a fluctuation between the generated voltage V2 and a desired boosted voltage V3, and as a result, Detector 504 that outputs a control signal corresponding to the control signal, voltage-controlled oscillator 503 that modulates the cycle of clock signal CLK generated according to the control signal, and clock signal C that is generated
The driver circuit 501 outputs a voltage to the output node E1 based on LK, and a charge pump circuit 502 boosts the output voltage of the driver circuit 501. Then, the voltage V2 generated by the charge pump circuit 502 is stably held by the storage capacitor C0, and a boosted voltage is supplied to the load 505.

Here, the voltage controlled oscillator 503 is a PMO
For example, five inverters 511 each including an S transistor P4 and an NMOS transistor N4 are connected in a ring shape. And V generated by detector 504
Control signal CT corresponding to the displacement ΔV2 from the set value V3 of
The gate voltage of N4 is controlled by L and the inverter 511
Of the clock signal CLK generated by the oscillator 503 is modulated. The driver circuit 501 includes a PMOS transistor P3 and an inverter of an NMOS transistor N3. Further, the charge pump circuit 502 includes diodes D1 and D2 and a pump-up capacitance C1.

In this power supply circuit, a generated voltage V
2 is expressed by the following equation using the current Iw consumed by the load 105 and the current Is supplied from the power supply circuit to the load 505. V2 = V3 + ΔV2 = V3 + 1 / C0∫ (Is−Iw) · dt (1) where V3 represents a target set value of V2, and ΔV2 represents a fluctuation value of V2 from V3.

Here, the supply current Is will be described. (A) When CLK = GND The output CLK of the voltage controlled oscillator 503 is equal to the ground voltage (hereinafter, referred to as “ground voltage”).
FIG. 6 shows the operation waveform of each node when the state transitions to (GND).
(A). In the initial state, CLK = V1. Therefore, the potential of the output node E1 of the driver circuit 501 becomes GND.
And the internal node E2 of the charge pump circuit 502 is charged up to V1-Vd through D1. Where Vd is the voltage drop across the diode. CL
When K = GND, P3 is turned on, N3 is turned off, and E1 is charged. Due to the coupling that occurs on both sides of C1, first, E1 and E2 are respectively V2-V
It rises to 1 + 2Vd and V2 + Vd. When E2 rises to V2 + Vd or more, D2 turns on and the electric charge becomes V2 + Vd.
Supplied to At this time, the same amount of charge
Charged to 1. The charge is supplied until E1 finally reaches V1, and the total charge Qs supplied by this one operation is given by the following equation. Qs = C1 · (2 · V1−V2-2 · Vd) (2)

(B) In the case of CLK = V1 FIG. 6B shows the operation waveform of each node when transitioning to CLK = V1. In the initial state, CLK = GND,
Therefore, the potential of E1 is V1, and the supply of the charge to the load through D2 ends, and E2 becomes V2 + Vd. Here, when CLK = V1 is applied, P3 is turned off, N3 is turned on, and the electric charge of E1 is discharged. E
1 finally drops to GND, but due to the coupling that occurs at both ends of C1, when E2 falls below V1-Vd, D1 turns on, charges E2, and E2 becomes V
Keep 1-Vd. At this time, the total charge amount of each of charge and discharge is equal to Qs.

Here, it is assumed that the load consumes charges of Qs / 2 and Qs / 3 in a certain period T as shown in FIG. From the equation (1), in order to minimize the variation ΔV2 from the target design value of V2, the load consumption current Iw and the power supply circuit supply current Is must be matched. Further, based on the above operation principle, the clock signal CLK
The total amount of charge that the power supply circuit supplies to the load during one cycle is Qs
It is. Therefore, in this power supply circuit, ΔV2 is minimized by modulating the cycle of the clock signal CLK to T, 2T, and 3T, respectively, using the voltage controlled oscillator 503.

[0008]

As described above, in the conventional power supply circuit, the period of the clock signal CLK for driving the driver circuit 501 is controlled so that Iw and Is in the equation (1) are made equal to each other and set to the set value V3. The generation control of the near boosted voltage V2 was performed. However, in this circuit operation, even if the current consumption Iw of the load suddenly changes within one cycle of the clock signal CLK generated from the voltage controlled oscillator 503,
In principle, the control of the boosted voltage could not be performed. The maximum amount of the boost voltage fluctuation in such a case is
This occurs when the load suddenly stops consuming the current Iw, but the charge pump circuit 502 cannot stop the operation and supplies the load with a single pumping operation. The maximum value of ΔV2 is given by the following equation. ΔV2 (max) = 1 / C0∫ΔIs · dt = Qs / C0 = C1 / (C0 + C1) · (2 · V1−V2-2 · Vd) (3)

In general, it is difficult to determine an accurate CLK cycle in the voltage controlled oscillator 503, and even if a sudden change in load current does not occur, the displacement of the boosted voltage V2 from the target set value V3 is always constant. In addition to this, when the displacements represented by the equation (3) overlap, the maximum value of ΔV2 is C1 / (C0 + C1) · (2 · V1−V2-2 ·
Vd). Further, since the conventional voltage controlled oscillator is a ring type, the power consumption is large. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems of the conventional power supply circuit and to provide a power supply circuit capable of stably and more accurately generating a desired boosted voltage.

[0010]

A power supply circuit according to the present invention comprises an oscillator for generating a clock signal, a driver circuit for alternately outputting a power supply voltage and a ground voltage as a driver signal voltage in response to the clock signal, and a driver circuit for the driver circuit. A charge pump circuit that is charged by a signal voltage and outputs a predetermined voltage; and a detector that detects a change in a voltage output from the charge pump circuit and supplied to a load and outputs a control signal corresponding to the change. The driver circuit presupposes that the output signal voltage is controlled based on the output control signal of the detector and the clock signal, and has the following features.
You.

That is, the oscillator includes a circuit for switching between a high level and a low level of a clock signal, a first delay element for outputting a signal for switching the clock signal from a high level to a low level, and a circuit for switching from a low level to a high level. A second delay element for outputting a switching signal, wherein the second delay element outputs a switching signal according to a comparison result of comparing an output of the driver circuit with a predetermined voltage, and the first delay element outputs a clock signal. A switching signal is output after a certain time after the state change. Here, the driver circuit is
An inverter in which two MOS transistors are cascaded and
And the gate of one of the MOS transistors
Clock signal is input to the other MOS transistor
The logic of the clock signal and the output control signal of the detector on the gate of
Preferably, a product or logical sum signal is input.
Good.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment in which the present invention is applied to a boost power supply circuit. The detector 104, the charge pump circuit 102, and the storage capacitor C0 have the same configuration as that of the conventional circuit shown in FIG. 5, and the detector 104 includes a boosted voltage V2 generated by the power supply circuit and a fluctuation from a desired boosted voltage V3. And outputs a control signal CTL. The charge pump circuit 102 includes diodes D1 and D2 and a pump-up capacitor C1, and boosts the voltage at the node E1 to V2. Further, the storage capacitor C0 is used to stably hold V2.

An oscillator 103 for generating a clock signal CLK, and a driver circuit 101 for driving the charge pump circuit 102 using the control signal CTL output from the detector 104 and the clock signal CLK from the oscillator 103 Have. Note that the driver circuit 10
The charge pump circuit 102 and the oscillator 103 are supplied with V1 as a power supply voltage. The load 105 is supplied with the voltage V2 and the current Is, and the load consumes the current Iw.

In the driver circuit 101, a PMOS transistor P1 and an NMOS transistor N1 constitute an inverter, and the gate of P1 has the clock signal C
The output of the OR circuit 110 that receives the LK and the control signal CTL from the detector 104 is input, and the clock signal CLK is input to the gate of N1. The output of the inverter outputs a voltage to the node E1.

The oscillator is connected to a flip-flop in which a NAND circuit 111 is cross-connected, a first delay element 113 connected between one output and input of the flip-flop, and another input. And a second delay element 114. As shown in FIG.
The first delay element 113 outputs a signal as one input CLKB2 of the flip-flop with almost no time delay when V1 is input as one output CLKB of the flip-flop, and outputs a signal for a fixed time when GND is input. Signals are output with a delay, and the output state of the flip-flop is switched by each signal.

Further, as shown in FIG.
Reference numeral 14 denotes a differential amplifier 112 that compares the output E1 of the driver circuit 101 with V1. E1 <V1, that is, the case where the charge pump circuit 102 has the ability to supply charges to the load, and E1 = V1, that is, the charge The pump circuit 102 outputs a signal and switches the output state of the flip-flop when the pump circuit 102 has finished supplying the charge to the load and the pump-up capacitor C1 needs to be charged. As a result, the first delay element 113 determines the time T1 at which CLK = V1, and the second delay element 114 determines the time T1.
= TGND is determined.

The operation of the power supply circuit having the above configuration will be described with reference to FIG. Here, the detector 104 determines that V2> V3
, And output GND when V2 ≦ V3. Such a detector can be easily configured using a commonly used differential amplifier.

(A) When CLK = GND and CTL = GND (V2 ≦ V3) Since the OR circuit 110 outputs GND, P1 is turned on.
N1 is turned off, and charge is supplied to E1 through P1. Thereby, similarly to the conventional example, the diode D is changed from E2.
2, a charge (current Is) is supplied to the load 105.
In response to the supply of charges, the potential of E1 rises from GND to V1.

(B) When CLK = GND, CTL = V1 (V2> V3) Since the OR circuit 110 outputs V1, both P1 and N1 are turned off, and supply of electric charge to E1 through P1 is temporarily stopped. Stopped. Therefore, the supply of charges from E2 to the load is also temporarily stopped. During that time, the potential of E1 is kept at a constant value between GND and V1.

(C) When CLK = V1 Since the OR circuit 110 outputs V1, P1 is off and N
1 is turned on, and electric charge is discharged from E1 through N1. During this time, E2 passes through D1 and V1−Vd as in the conventional example.
To charge the pump-up capacity C1 for the operation of the above 1).

As described above, in the power supply circuit according to this embodiment, when the clock signal CLK is at a fixed GND, that is, at a timing corresponding to one cycle of the CLK signal, V2 and the boosted voltage set value V3 by the detector 104 are set. The operation modes (a) and (b) can be switched in accordance with the result CTL of the comparison. In other words, the supply of the charge from the power supply circuit to the load and the suspension of the supply can be switched even within one cycle of the clock signal CLK, which was conventionally impossible, so that the boosted voltage is controlled with higher precision. It became possible.

As described above, in the power supply circuit of this embodiment,
Based on the principle described in the section of the related art, the charge pump circuit 102 uses the fact that the amount of charge supplied to V2 through D2 is equal to the amount of charge charged to E1 through P1 of the driver circuit 101. 10
This means that the gate voltage of P1 is controlled by the CTL signal to control the amount of charge supplied to E1, that is, the amount of charge (current amount Is) supplied to the load 105. Therefore, in the present invention, the output current of the driver circuit 101 is controlled by the output of the detector 104, and thereby the current supplied to the load 105 of the power supply circuit is controlled.

In the power supply circuit described above, the relationship between the actually generated voltage V2 and the desired boosted voltage V3 is as follows.
It is assumed that a delay time from when the relationship between V2> V3 and V2 ≦ V3 is reversed to when the power supply circuit stops or starts the current supply is t0. Then, consider the case where the current consumption of the load repeats between 0 and I0 every time t1. In the case of the conventional power supply circuit, the maximum C1 / (C0 + C
1) V2 fluctuates by (2V1-V2-2Vd).
On the other hand, in the case of the power supply circuit of the present embodiment, V2 fluctuates by ± I0 · t0 / C0 across V2 due to the existence of the delay time t0. Here, C1 · (2V1-V2-2Vd) can be represented by I0 · t2. Here, t2 is the maximum cycle of the oscillator in the power supply circuit, and is usually 10 times or more of t0. In addition, since C0ＶC1, the V
The two fluctuations are I0 · t2 / C0, which is five times or more the 2 · I0 · t0 / C0 of the V2 fluctuation of the power supply circuit of the first embodiment. Therefore, according to the present invention, V2 is one of the conventional fluctuation amount.
It can be reduced to about / 5.

Here, in the operation mode (c), that is, when CLK = V1, the charge is charged from V1 to the pump-up capacitor C1 through D1, and during this period, current cannot be supplied to the load. State. Therefore, in the configuration shown in FIG. 1, even if V2 falls below V3 during this period, the boosted voltage cannot be controlled. Therefore, as shown in FIG. 3, the driver circuit 101 and the charge pump circuit 1
A plurality of sets of 02 (n sets, n is an integer of 2 or more) may be provided, and the oscillator 201 may be provided with multi-phase clock signals having different phases. N in the simplest case
= 2, two sets of the driver circuit 101 and the charge pump circuit 102 are prepared, and a clock signal CLK having a phase difference of 180 degrees is supplied to them. Thus, even if the first set of driver circuits is in the operation mode of (c), the other set of driver circuits can be in the operation mode of (a) or (b). Current can be supplied to the load.

In the embodiment in which the present invention is applied to a step-down power supply circuit, the driver circuit and the second
FIG. 4 shows a circuit connection state of the differential amplifier 112 as a delay element.
Shown in The driver circuit comprises P2 for charging E1, and E1
And CTL, CLK as inputs and AND
It is composed of a circuit 115. However, the AND circuit 115
When one of CTL and CLK is GND, it outputs GND, and when both are V1, it outputs V1. When CLK = V1, the current flowing through N2 can be stopped and restarted according to the output CTL of the detector 104. Also, the second delay element 1
The differential amplifier 112 functioning as 14A includes E1 and GN
D is compared, and a coincidence signal is output when E1 = GND.

[0026]

As described above, according to the present invention, a driver circuit for alternately outputting a power supply voltage and a ground voltage to a charge pump circuit to output a predetermined voltage from the charge pump circuit is provided. The control is performed based on an output control signal from a detector that detects a change in the voltage output from the power supply and supplied to the load and outputs a control signal corresponding thereto, and a clock signal generated by an oscillator. Therefore, even within one cycle of the clock signal,
Switching between supply of power from the power supply circuit to the load and suspension of supply can be performed, voltage control can be performed with higher accuracy, and output voltage can be stabilized. Also,
Since the oscillator does not need to be formed by a ring-type circuit like a conventional voltage controlled oscillator, it is effective in reducing power consumption.
Furthermore, since the delay element is operated using the output of the driver circuit to which the clock signal is input, it is possible to determine the cycle with high accuracy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a power supply circuit of the present invention.

FIG. 2 is a signal waveform diagram illustrating a relationship between a clock signal of an oscillation circuit, a control signal of a detector, and a driver output.

FIG. 3 is a circuit diagram of an embodiment in which the present invention is improved.

FIG. 4 is a partial circuit diagram of an embodiment in which the present invention is applied to a step-down power supply circuit.

FIG. 5 is a circuit diagram of an example of a conventional power supply circuit.

6 is a signal waveform diagram showing a relationship between a clock signal and an output in the power supply circuit of FIG.

FIG. 7 is a diagram illustrating a control method for a load in the power supply circuit.

[Explanation of symbols]

 101 Driver circuit 102 Charge pump circuit 103 Oscillator 104 Detector 105 Load 110 OR circuit 111 NAND circuit 112 Differential amplifier 113 First delay element 114 Second delay element P1, N1 MOS transistor V1 Power supply voltage C1 Pump-up capacity

Claims (5)

(57) [Claims] An oscillator for generating a clock signal, a driver circuit for alternately outputting a power supply voltage and a ground voltage as a driver signal voltage in response to the clock signal, and outputting a predetermined voltage charged by the driver signal voltage A charge pump circuit that detects a change in the voltage output from the charge pump circuit and supplied to the load, and outputs a control signal corresponding to the change, and the driver circuit includes an output of the detector. The output signal voltage is controlled based on a control signal and the clock signal ,
The oscillator controls the high and low levels of the clock signal.
Circuit to switch the state and the clock signal from high to low
A first delay element for outputting a signal for switching to a level,
Second to output a signal to switch from low level to high level
Wherein the second delay element includes a driver
Cut off according to the result of comparing the output of the circuit with the specified voltage.
The first delay element outputs a clock signal
A power supply circuit for outputting a switching signal after a predetermined time after a state change . 2. The driver circuit is configured as an inverter in which two MOS transistors are connected in cascade. A clock signal is input to the gate of one MOS transistor, and the clock signal and the output of the detector are input to the gate of the other MOS transistor. The power supply circuit according to claim 1 , wherein a logical product or a logical sum signal of the control signals is input. Wherein the second delay element makes a comparison between the output and a power supply voltage of the driver circuit, and outputs a switching signal when the power supply voltage reaches the voltage higher than the output voltage, the charge pump circuit The power supply circuit according to claim 1 , wherein the power supply circuit is configured to output a voltage that is higher than the power supply voltage. 4. The second delay element compares an output of the driver circuit with a ground voltage, and outputs a switching signal when the ground voltage becomes lower than the output voltage. 3. The power supply circuit according to claim 1 , wherein the power supply circuit is configured to output a voltage lower than the voltage. 5. The set of driver circuits and a charge pump circuit and a plurality of sets connected in parallel, according to one of claims 1 <br/> and 4 have the driver circuits phase to enter a different clock signal Power circuit.