JP2795049B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to a logic circuit in an n-type depletion MESFET integrated circuit.

[0002]

2. Description of the Related Art Conventional n-type depletion MESFE
SCFL (Source Couple)
FIG. 5 shows a logic circuit of (d FET Logic).

Conventional n-type depletion MESFET
The logic circuit of the SCFL formed by the above is composed of n-type depletion MESFETs 21 to 27, a diode 28,
29 and resistors 32 and 33. In order to form a positive-phase signal and a negative-phase signal of an input voltage with respect to a reference voltage by a differential pair including n-type depletion MESFETs 21 to 23 and resistors 32 and 33, and obtain an interface with an input level of another logic circuit. , N-type depletion MESF
The signal is level-shifted by a level shift circuit including ETs 24 to 27 and diodes 28 and 29, and output.

If there is a load capacity, the output “Hig
The upper n-type depletion MESF at the time of “h” level
Charged by the ETs 24 and 25, and when the output is at the “Low” level, the lower n-type depletion MESFETs 26 and 2
7 discharges.

[0005]

However, in the above-described SCFL logic circuit formed by the conventional n-type depletion MESFET, the current of the output level shift circuit is controlled by the n-type depletion MESFET and its bias voltage. Vcs) and outputs “High” and “L”.
Since the operation is performed at a constant current irrespective of the level of "ow", the constant current must be increased depending on the load capacity of the output, and there is a problem that the current increases.

There is another problem that the speed is reduced unless the constant current is increased.

[0007] The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide a novel logic circuit capable of solving the above-mentioned various problems inherent in the prior art. It is in.

[0008]

In order to achieve the above-mentioned object, a logic circuit according to the present invention comprises a differential pair and a level shift circuit. It comprises a resistor and a diode for controlling the current of the level shift.

More specifically, the logic circuit according to the present invention comprises a first n-type depletion MESFET having a gate connected to an input terminal, a source connected to a reference voltage and a source connected to the first n-type depletion MESFET. Type depletion MESFE
A second n-type depletion M connected to the source of T
An ESFET, a third n-type depletion MESFET having a drain connected to the sources of the first and second n-type depletion MESFETs, a gate connected to the bias voltage, and a source grounded; 1, a first resistor connected to the drain of the n-type depletion MESFET and the other end connected to the power supply, and one end connected to the drain of the second n-type depletion MESFET and the other end connected to the power supply A second resistor, a fourth n-type depletion MESFET having a gate connected to the drain of the first n-type depletion MESFET and a drain connected to the power supply, and a gate connected to the second n-type depletion MESFET. Fifth n-type depletion ME connected to the drain of the depletion MESFET and having the drain connected to the power supply
An SFET, a first diode having an anode connected to the source of the fourth n-type depletion MESFET and a cathode connected to the negative-phase output terminal, and an anode connected to the source of the fifth n-type depletion MESFET; A second diode having a cathode connected to the positive-phase output terminal, third and fourth resistors connected in series between the negative-phase output terminal and ground, and a second diode connected between the positive-phase output terminal and ground. And a sixth n-type depletion MESFET having a drain connected to the negative-phase output terminal and a gate connected to a connection point of the fifth and sixth resistors.
A seventh n-type depletion MESFET having a drain connected to the positive-phase output terminal and a gate connected to the connection point of the third and fourth resistors, and an anode connected to the sixth n-type depletion A third diode is connected to the source of the MESFET and the cathode is grounded, and a fourth diode is connected to the source of the seventh n-type depletion MESFET and the cathode is grounded.

[0010]

Next, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment according to the present invention.

Referring to FIG. 1, a first embodiment of a logic circuit of an n-type depletion MESFET according to the present invention comprises n-type depletion MESFETs 1 to 7, diodes 8 to 11, and resistors 12 to 17. Consisting of Since the differential pair of the input section is the same as the conventional example, the level shift circuits (n-type depletion MESFETs 4 to 7,
The diodes 8 to 11 and the resistors 14 to 17) will be described.

In FIG. 1 and FIG. 2, which is an explanatory diagram of the operation of the first embodiment, the input signal, ie, the in-phase output Q is "High".
, The gate-source voltage Vg of the n-type depletion MESFET 7 formed by the voltage of the negative-phase output QB
s becomes smaller, and the drain-source current of the MESFET 7 decreases. For that purpose, n-type depletion MESF
It becomes easy to charge the load capacity by ET.

Conversely, when the positive-phase output becomes "Low", n
The gate-source voltage Vgs of the type depletion MESFET 7 increases, and the gm of the MESFET 7 increases. Therefore, n-type depletion MESFET7
This facilitates discharge from the load capacity.

The negative-phase output operation is the reverse operation of the normal-phase output operation.

FIG. 3 is a circuit diagram showing a second embodiment according to the present invention.

Referring to FIG. 3, a second embodiment according to the present invention comprises n-type depletion MESFETs 1 to 7,
It comprises diodes 8, 9 and resistors 12-19.

In the second embodiment, resistors 18 and 19 are used in place of the diodes 10 and 11 of the first embodiment.
You are using In the second embodiment, the variation width of Vgs is made smaller than that of the first embodiment because of the resistance, but there is an effect of suppressing the element variation.

FIG. 4 is a circuit diagram showing a third embodiment according to the present invention.

Referring to FIG. 4, a third embodiment according to the present invention comprises n-type depletion MESFETs 1 to 7, 2 and
A two-input OR (NOR) gate consisting of 0, diodes 8 to 11 and resistors 12 to 17 has almost the same effect as in the first embodiment.

[0021]

As described above, according to the present invention,
“The level shift circuit controls the current of each level shift by a signal having the opposite phase to the signal entering each level shift, thereby reducing the current consumption without lowering the operating frequency as compared with the conventional constant current level shift. The effect that can be obtained is obtained.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a logic circuit according to the present invention.

FIG. 2 is an explanatory diagram of the operation of the first embodiment according to the present invention.

FIG. 3 is a circuit diagram showing a second embodiment according to the present invention.

FIG. 4 is a circuit diagram showing a third embodiment according to the present invention.

FIG. 5 is a circuit diagram of a conventional example.

[Explanation of symbols]

 1 to 7, 20: n-type depletion MESFET 8 to 11: diode 12 to 19: resistor

Claims (1)

(57) [Claims] A first n-gate having a gate connected to an input terminal;
-Type depletion MESFET, a gate connected to the reference voltage and a source connected to the first n-type depletion M
A second n-type depletion MESFET connected to the source of the ESFET; and a drain connected to the first and second n-type depletion MESFETs.
A third depletion type MESFET having a source connected to a source, a gate connected to a bias voltage, and a source grounded.
An n-type depletion MESFET, a first resistor having one end connected to the drain of the first n-type depletion MESFET and the other end connected to a power supply, and one end connected to the second n-type depletion MESFET. A second resistor connected to the drain of the first MESFET and having the other end connected to the power supply; and a fourth n-type transistor having a gate connected to the drain of the first n-type depletion MESFET and a drain connected to the power supply. A fifth n-type depletion MESFET having a gate connected to the drain of the second n-type depletion MESFET and a drain connected to a power supply; and an anode connected to the fourth n-type depletion MESFET. A first diode connected to the source of the MESFET and having a cathode connected to the negative-phase output terminal; A second diode connected to the source of the depletion MESFET and having a cathode connected to the positive-phase output terminal; third and fourth resistors connected in series between the negative-phase output terminal and ground; Fifth and sixth resistors connected in series between the output terminal and the ground, and a sixth resistor having a drain connected to the opposite-phase output terminal and a gate connected to a connection point of the fifth and sixth resistors. n-type depletion MES
An FET, a seventh n-type depletion MESFET having a drain connected to the positive-phase output terminal and a gate connected to a connection point of the third and fourth resistors, and an anode connected to the sixth MESFET.
A third diode connected to the source of the n-type depletion MESFET and having a cathode grounded, and a fourth diode connected to the source of the seventh n-type depletion MESFET and having the cathode grounded. A logic circuit comprising: