JP2766876B2 - Glitch pattern detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is to supply a DA converter with an optimal provisional time obtained from a glitch pattern detection result.
The present invention relates to a glitch pattern detection circuit that detects a pattern that generates a glitch.

[Background Art] A DA converter that converts digital data into an analog signal requires time from the application of digital data to the stabilization of the analog signal. This time to stabilization is called the settling time. This settling time differs depending on the amount of change in the digital data. On the other hand, if digital data
When the value changes from (= 0111) to 8 (= 1000), the change amount of the digital data is only 1, but a glitch occurs because all bits change. If a glitch occurs, the settling time becomes longer.

FIG. 3 shows an apparatus for controlling the settling time of a conventional DA converter. Digital data to be converted into an analog signal is supplied from an input terminal 11 to a data change amount calculation circuit 12 and to a data latch 13. The digital data of one cycle before is stored in the data latch 13 and is supplied to the data change amount calculation circuit 12, and the data change amount calculation circuit
At 12, the difference between the current data and the previous data is calculated,
The settling time table 14 is read with the data change amount,
A settling time corresponding to the data change amount is generated. The settling time table 14 stores a settling time obtained by adding a stabilizing time according to the data change amount and a stabilizing time according to the maximum glitch amount.

As described above, in the conventional apparatus, a settling time table is created by adding a stabilizing time according to the maximum glitch amount in advance.
A glitch occurs only when two subsequent data have a specific pattern relationship. In most cases where no glitch occurs, an unnecessarily long settling time is taken.

In order to improve such a problem, an apparatus shown in FIG. 4 has been proposed. The digital data from the terminal 11 is supplied to the data change amount calculation circuit 12 and the data latch 13 and also to the glitch pattern detection circuit 15. The data one cycle before the data latch 13 is the data change amount calculation circuit
12 and the glitch pattern detection circuit 15. The difference between the current data and the previous data is calculated by the data change amount calculation circuit 12, and the settling time table is calculated based on the difference data.
14 is read. The glitch pattern detection circuit 15 detects a pattern to generate a glitch from the current data and the previous data, and reads the glitch time table 16 according to the glitch pattern. The settling time table 14 stores a stabilizing time according to the difference between the current data and the previous data. The glitch time table 16 stores the time until the glitch is stabilized according to the glitch pattern, that is, the glitch time. The output of the settling time table 14 and the output of the glitch time table 16 are added by the adding circuit 17 and output as settling time data.

In this way, settling time data close to the actual settling time is always obtained, and there is no danger that an unnecessarily long settling time will be taken.

An object of the present invention is to provide a glitch pattern detection circuit for detecting a glitch pattern.

According to the present invention, the difference between the input data and the data one cycle before the input data and the data having a different number of consecutive bits after the MSB is detected by the plurality of subtraction circuits, respectively. That the output of the subtraction circuit is +1 or -1, that is, that the LSB between two data input to each subtraction circuit is different is detected by a plurality of 1LSB change detection circuits, and the One of the outputs of the 1LSB change detection circuit is selected and input to the data latch. Further, a plurality of non-matching circuits detect that there is a mismatch between the corresponding higher-order bits of the input data and the data one cycle before, and one output selected from the outputs of the plurality of non-matching circuits and a plurality of outputs. The logical product with one output selected from the 1LSB change detecting circuit is taken by the logical product circuit and input to the data latch. The bit change between the data one cycle ago and the current data is calculated as a glitch pattern indicating the number of bits counted from the MSB and LSB, respectively, from the data latch through the calculation of the glitch time table and the provisional time table. , Supplied to the DA converter.

FIG. 1 shows an embodiment of the present invention. Input data b ₉ ~b ₀ from the terminal 21 is supplied to the data latch 23 is supplied to one input terminal of the subtraction circuit 22 ₁ to 22 _4. Subtraction circuit
22 _{1-22 4} the other input terminal from the data latch 23 one cycle before the data is input. Subtraction circuit 22 ₁ bit b ₉
Performs subtraction of the data consisting of ~b _5, subtraction circuit 22 ₂ performs the subtraction of the data consisting of bits b ₉ ~b _6, pull data subtraction circuit 22 ₃ is comprised of bits b ₉ ~b ₇ Calculation and subtraction circuit 22
₄ performs subtraction of data consisting of bits b ₉ ~b _8. For example, the current input data consisting of bits b _{9 to} b ₅ is “01111” (= 15)
In the case one cycle before the data is "10000" (= 16), the respective outputs of the subtraction circuits 22 _1, 22 _2, 22 _3, 22 _4, "11110" (= - 1), " 1110 "(= -1)," 110 "
(= −1) and “10” (= −1) (“11111” to “11”
Is a two's complement operation and "-1" is added.) Subtraction circuit
Each output of 22 _{1-22 4} is supplied to the ILSB change detection circuit 23 ₁ to 23 _4. ILSB change detection circuits 23 ₁ to 23 ₄ are subtraction circuits 22
Whether to _{1-22 4} data inputted respectively to the LSB (least significant bit) is changed, i.e. it is detected the output of the subtraction circuit 22 ₁ to 22 ₄ is +1 or -1.

1LSB change detection circuit 23 _1, 23 _2, 23 _3, 23 a specific example of a ₄ second
Shown in the figure. In this circuit, for example, subtraction circuits 22 ₁ , 22 ₂ , 2
2 _3, 22 ₄ each output of "11110" (= - 1), "1
110 "(= -1)," 110 "(= -1)," 10 "(= -1)
In the case of 1LSB change detection circuit 23 ₁ , 23 ₂ , 23 ₃ , 23 ₄ (second
The output of each NAND circuit 24 in FIG.
The output of 5 is “1”, and the output of each NAND circuit 24 and each AND circuit
₁ LSB change detection circuit 23 ₁ , 2 which is the output of the OR circuit of 25 outputs
3 _2, 23 _3, 23 ₄ output of each "1". Subtraction circuit
The output of each of 22 ₁ , 22 ₂ , 22 ₃ , and 22 ₄ is “00000” (=
1), “0000” (= 1), “000” (= 1), “00” (=
In the case of 1) (“00001” to “01” are subjected to two's complement operation and “−1” is added.) The output of each NAND circuit 24 is “1”, but the output of each AND circuit 25 is It becomes “0”. That is, "0000
0 "to" 00 "and circuit 24 for detecting the," 11110 "~" 10 .ILSB change detection circuit 23 ₁ constituted by a circuit 25 for detecting a "
Is output to the AND circuits 26 ₁ , 26 ₂ , and 26 ₃ and the AND circuit 2
6 _1, 26 _2, 26 Ilsb change detection circuit 23 ₂ to _3, 23 _3, the outputs of 23 ₄ is supplied, the output from the Ilsb detecting circuit 23 ₁ is obtained,
Output of other ILSB detection circuit 23 _{2-23 4} is inhibited by the AND circuit 26 ₁ to 26 _3. AND circuits 26 ₁ to 26 ₃ constitute a priority circuit 26. The inverted output of the ILSB change detection circuit 23 ₂ is connected to the AND circuits 26 ₂ and 26
Is supplied to the _3, the inverted output of ILSB change detection circuit 23 ₃ is supplied to the AND circuit 26 _3. Thus (for example 1 cycle before the data in the current input data is "01111" is "10000") output of 1LSB change detection circuit 23 ₁ is "1" when, 1LSB change detection circuit
23 _1, 23 _2, 23 _3, 23 ₄ of the output also becomes a "1", the AND circuit 2
6 _1, 26 _2, 26 ₃ by 23 _2, 23 _3, 23 ₄ of the data is prevented, only the data of 1LSB change detection circuit 23 ₁ to the data latch circuit 23 is inputted, the b ₅ bit change It is informed that there was. Also for example, the output of 1LSB change detection circuit 23 ₁ and 23 ₂ is "0" output at 23 ₃ and 23 ₄ is "1" when (e.g. one cycle before the data in the current input data "01000" is "00110" If), that there was a bit change is notified to b ₃ through an aND circuit 26 _{3. 1} LSB change detection circuit 23 ₁ output, AND circuit 26
Each output of _{1-26 3} are supplied to the OR circuit 27.

Meanwhile, mismatch between the most significant bit b ₉ upper bits b ₉ uppermost one cycle before the data in the data input terminal 21 is detected by mismatch detection circuit 28 _1. Similarly for the second bit b ₈ from the most significant bit mismatch between the current data and the previous data is detected by mismatch detection circuit 28 _2, further bits b _7,
mismatch of b ₆ are respectively detected by the mismatch detection circuit 28 _3, 28 _4.

The output of mismatch detection circuit 28 ₁ to 28 ₄ are AND circuits 29 ₁ to 29 ₄
To be supplied, OR is to these AND circuits 29 ₁ to 29 ₄
The output of circuit 27 is provided. Inverted output of mismatch detection circuit 28 ₁ is supplied to the AND circuit 29 _{2-29 4,} mismatch detection circuit
28 ₂ inverted output is supplied to the AND circuit 29 _3, 29 _4, the inverted output of mismatch detection circuit 28 ₃ is supplied to the AND circuit 29 _4.
AND circuits 29 ₁ to 29 ₄ as upper bits, priority priority circuit
Make up 29. The output of the AND circuit 29 ₁ to 29 ₄ become glitch pattern detection output.

As described above, according to the present invention, the change of the least significant bit is detected by the ILSB change detection circuit. If this change is detected and the upper bits do not match, it is detected that the pattern is a glitch pattern. For example, in the case of one cycle before the data is "00100" in the current input data is "01000", the 2nd lower counted from the MSB by the output of the AND circuit 29 ₂ that for which the bit changes, also the AND circuit 26 ₂ The output indicates that the bit has changed in the third most significant position from the LSB, that is, the bit change width is 2
Is notified to the data latch 23. Also for example, in the case of one cycle before the data in the current input data is "10000" is "01000", the output of the AND circuit 29 ₁ that there was a bit change in MSB, counted from the LSB by the output of the AND circuit 26 ₃ It is informed that a bit change has occurred at the fourth highest position, that is, the bit change width is 2.

[Effects of the Invention] As described above, according to the present invention, when there is a continuous bit change between data before and after data input every cycle in the preceding stage of the DA converter, this is used as a glitch pattern. Can be detected. At this time, a plurality of exclusive OR circuits and one or more subtraction circuits on the MSB side
Glitch detection can be given a range by a circuit that detects each bit change on the LSB side by the LSB change detection circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a block diagram showing a conventional settling time control device, and FIG. 4 is a block diagram showing an example of a proposed settling time control device.

Claims (1)

(57) [Claims] 1. A glitch pattern detection circuit for supplying a glitch pattern to a DA converter for converting input data every cycle, comprising: input data and data one cycle before the input data; A plurality of subtraction circuits for detecting the difference between the data obtained by extracting the plurality of bits having different numbers of bits, and a plurality of subtraction circuits for detecting that the output of each subtraction circuit is +1 or -1. A 1LSB change detection circuit, a priority circuit that selects one output from the outputs of the plurality of 1LSB change detection circuits with a higher priority as the number of input bits is larger, A plurality of mismatch detection circuits for comparing corresponding bits and detecting the mismatch, and comparing the outputs from the plurality of mismatch detection circuits. The higher the bit, the higher the bit, the higher the priority, the higher the priority, the logical product of the output of the priority circuit, and the input data. A data latch that outputs to each of the subtraction circuits and each of the non-coincidence detection circuits after a cycle, inputs the outputs of each of the non-coincidence detection circuits and each of the 1LSB change detection circuits, and supplies them to the DA converter. A glitch pattern detection circuit.