JP2677697B2 - Module element - Google Patents

Module element

Info

Publication number
JP2677697B2
JP2677697B2 JP2008216A JP821690A JP2677697B2 JP 2677697 B2 JP2677697 B2 JP 2677697B2 JP 2008216 A JP2008216 A JP 2008216A JP 821690 A JP821690 A JP 821690A JP 2677697 B2 JP2677697 B2 JP 2677697B2
Authority
JP
Japan
Prior art keywords
transistor
module element
arc
module
fuse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2008216A
Other languages
Japanese (ja)
Other versions
JPH03214657A (en
Inventor
千尋 岡土
誠 秀島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2008216A priority Critical patent/JP2677697B2/en
Publication of JPH03214657A publication Critical patent/JPH03214657A/en
Application granted granted Critical
Publication of JP2677697B2 publication Critical patent/JP2677697B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Fuses (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は電力用半導体制御素子に係り、特に防爆特性
を改良したモジュール素子に関する。
The present invention relates to a power semiconductor control element, and more particularly to a module element having improved explosion-proof characteristics.

(従来の技術) 電力用半導体制御素子は第3図に示すように、インバ
ータブリッジ4のスイッチ素子61〜66としてバイポーラ
トランジスタ,MOSFET,IGBT(Iisulated Gate Bipolar T
ransistor)など各種のものが使用されている。
(Prior Art) As shown in FIG. 3, a power semiconductor control element includes a bipolar transistor, a MOSFET, and an IGBT (Iisulated Gate Bipolar Transistor) as switching elements 61 to 66 of an inverter bridge 4.
ransistor) various things are used.

第3図は、交流電動機駆動用トランジスタインバータ
の一般的な構成例である。
FIG. 3 is a general configuration example of a transistor inverter for driving an AC motor.

第3図において、直流電源1とフィルタ用コンデンサ
2から成る電源が高速ヒューズ3を介してトランジスタ
ブリッジ4に供給され、その交流出力によって電動機5
が駆動される。
In FIG. 3, a power supply composed of a DC power supply 1 and a filter capacitor 2 is supplied to a transistor bridge 4 via a high-speed fuse 3, and its AC output causes the motor 5 to move.
Is driven.

トランジスタブリッジ4は、トランジスタ61,62,63,6
4,65,66から成る三相インバータブリッジを構成してい
る。
The transistor bridge 4 includes transistors 61, 62, 63, 6
It forms a three-phase inverter bridge consisting of 4,65,66.

現在これに使用されているトランジスタは主としてモ
ジュール形であり、主電極と冷却面は電気的に絶縁さ
れ、主電極はボンディングワイヤを介してトランジスタ
のチップに接続されている。
The transistors currently used for this are mainly of modular type, the main electrode and the cooling surface are electrically insulated, and the main electrode is connected to the transistor chip via a bonding wire.

第4図はモジュール形トランジスタの構造の一例を示
すもので、冷却フィンに放熱させる銅ベース80の上に熱
伝導性の良い絶縁セラミックス81を接着し、その上に銅
材82,83,84が接着されて電極となり、トランジスタペレ
ット85のコレクタが銅材82にエミッタ端子を上側にして
接着され、エミッタ端子はボンディングワイヤ87でエミ
ッタ電極89にボンディングされ、コレクタ側はボンディ
ングワイヤ86でコレクタ電極88に接続されている。
Fig. 4 shows an example of the structure of a module type transistor. An insulating ceramics 81 with good thermal conductivity is adhered on a copper base 80 that radiates heat to a cooling fin, and copper materials 82, 83, 84 are placed on it. The collector of the transistor pellet 85 is bonded to the copper material 82 with the emitter terminal facing upward, the emitter terminal is bonded to the emitter electrode 89 with a bonding wire 87, and the collector side is bonded to the collector electrode 88 with a bonding wire 86. It is connected.

実際には、この他にベース信号端子も接続され、モジ
ュール外部には第5図に示すようにエミッタE,コレクタ
C,ベースBの端子が引き出され、外壁は絶縁性のモール
ド材でカバーされている。
In fact, in addition to this, the base signal terminal is also connected, and as shown in Fig. 5, the emitter E and collector are connected outside the module.
The terminals of C and base B are pulled out, and the outer wall is covered with an insulating molding material.

第3図のようにブリッジ構成されたインバータ回路に
おいて、上下のトランジスタの一方がパンクすると直流
電源が短絡されてトランジスタに過電流が流れ、図示し
ない過電流保護回路がこれを検出しトランジスタをすべ
てオフすることにより過電流保護をしている。しかし、
直流電圧が高い場合や制御回路の異常の場合はトランジ
スタの安全動作領域内で保護できず、他方のトランジス
タもパンクし短絡電流が増大し、ボンディングワイヤが
溶断してアークを出し、モジュール形トランジスタの外
壁が飛散して危険となるので、高速ヒューズ3によって
故障電流を限流遮断している。
In the inverter circuit configured as a bridge as shown in Fig. 3, if one of the upper and lower transistors blows out, the DC power supply is short-circuited and an overcurrent flows through the transistor. An overcurrent protection circuit (not shown) detects this and turns off all the transistors. By doing so, overcurrent protection is provided. But,
If the DC voltage is high or the control circuit is abnormal, protection cannot be performed within the safe operating area of the transistor, the other transistor will also puncture and the short-circuit current will increase, the bonding wire will melt and an arc will occur, and the module type transistor Since the outer wall is scattered and dangerous, the fault current is cut off by the high-speed fuse 3.

インバータの容量が大きくなると、モジュール素子を
多数並列に使用する必要があり、この場合モジュール素
子の外壁の破裂を防ぐために、第6図に示すように各ト
ランジスタモジュールのコレクタ側にそれぞれ高速ヒュ
ーズを接続している。これは第3図のような直流側の共
通ヒューズ3とすると、並列接続したすべてのモジュー
ル素子の保護に適合するヒューズが無いからである。
When the capacity of the inverter becomes large, it is necessary to use a large number of module elements in parallel. In this case, in order to prevent the outer wall of the module element from bursting, connect a high-speed fuse to the collector side of each transistor module as shown in FIG. doing. This is because, assuming the common fuse 3 on the DC side as shown in FIG. 3, there is no fuse that is suitable for protection of all module elements connected in parallel.

また第6図ではヒューズを各トランジスタのコレクタ
側に挿入しているが、これはトランジスタのベース駆動
信号を各トランジスタのエミッタ側を共通な基準電位と
して印加しているのでエミッタ側の電位変動がないよう
にする必要があるからである。
Further, in FIG. 6, a fuse is inserted in the collector side of each transistor, but since the base driving signal of the transistor is applied as a common reference potential to the emitter side of each transistor, there is no potential fluctuation on the emitter side. It is necessary to do so.

第6図はトランジスタブリッジの1相分を示したもの
で、複数のトランジスタ61−1〜61−nの各エミッタお
よびベースをそれぞれ並列に接続すると共にそれぞれの
トランジスタに高速ヒューズ31−1〜31−nを挿入して
いる。
FIG. 6 shows one phase of a transistor bridge. The emitters and bases of a plurality of transistors 61-1 to 61-n are connected in parallel, and high-speed fuses 31-1 to 31-are connected to the respective transistors. n is inserted.

また同じようにトランジスタ62−1〜62−nの各ベー
スおよびエミッタをそれぞれ並列に接続すると共に、そ
れぞれのトランジスタに高速ヒューズ32−1〜32−nを
挿入している。
Similarly, the bases and emitters of the transistors 62-1 to 62-n are connected in parallel, and the high-speed fuses 32-1 to 32-n are inserted in the respective transistors.

さらにコンデンサ8を直流母線のサージを吸収するた
めに出来るだけ素子の近くに配置している。
Further, the capacitor 8 is arranged as close as possible to the element in order to absorb the surge of the DC bus.

(発明が解決しようとする課題) しかしながら、第6図に示すように各トランジスタの
コレクタ側にヒューズを接続すると、そのための配線長
が長くなってインダクタンスLが増加し、ターンオフ時
のサージ電圧(L di/dt)が高くなって素子の信頼性を
低下させるという問題がある。
(Problems to be Solved by the Invention) However, when a fuse is connected to the collector side of each transistor as shown in FIG. 6, the wiring length for that is increased and the inductance L is increased, so that the surge voltage (L There is a problem that the di / dt) becomes high and the reliability of the device is lowered.

特に最近開発されているIGBTやMCT(MOS Controlled
Thyristor)などは、スイッチング速度がバイポーラト
ランジスタの数倍高速であるためにdi/dtも数倍(5〜
6倍)高くなり、その分だけサージ電圧が上昇して従来
の回路方式は使用できない。
In particular, recently developed IGBTs and MCTs (MOS Controlled
Thyristor) has a switching speed several times faster than bipolar transistors, so di / dt is several times faster (5 to 5 times).
6 times higher), and the surge voltage rises accordingly, and the conventional circuit system cannot be used.

このため第7図に示すようなサージ電圧の吸収回路が
用いられてきている。
Therefore, a surge voltage absorbing circuit as shown in FIG. 7 has been used.

すなわち、配線インダクタンスLa,Lb,Lc,Ldがそれぞ
れのIGBT71,72の主回路に存在するとき、コンデンサ9
とダイオード10によってIGBT71のコレクタ・エミッタ間
のサージエネルギーをクランプし、抵抗16を介してコン
デンサ2に放電し、またIGBT72に対してもダイオード1
1、コンデンサ12によってサージエネルギーをクランプ
抵抗15を介してコンデンサ2に放電する。
That is, when the wiring inductances La, Lb, Lc, Ld exist in the main circuits of the respective IGBTs 71, 72, the capacitor 9
And the diode 10 clamp the surge energy between the collector and the emitter of the IGBT71 and discharge it to the capacitor 2 via the resistor 16 and also the diode 72 for the IGBT72.
1. The surge energy is discharged by the capacitor 12 to the capacitor 2 through the clamp resistor 15.

しかし、この回路は、使用部品が多くなって複雑にな
ること、各素子ごとにサージクランプ回路を設ける必要
があること、抵抗15,16にエネルギーの損失が発生し効
率が低下することなどの欠点がある。
However, this circuit has drawbacks such as the number of components used becomes complicated, it is necessary to provide a surge clamp circuit for each element, and energy loss occurs in the resistors 15 and 16, resulting in reduced efficiency. There is.

本発明は高速ヒューズの挿入することによるインダク
タンスの増加を抑制するため、高速ヒューズを省略し、
高速ヒューズによる事故電流の遮断はモジュール素子の
ボンディングワイヤの溶断を利用することにより、経済
的でサージ電圧の発生の少ないトランジスタブリッジ用
のモジュール素子を提供することを目的としている。
Since the present invention suppresses the increase in inductance due to the insertion of the high speed fuse, the high speed fuse is omitted,
The purpose of interrupting the fault current by a high-speed fuse is to provide a module element for a transistor bridge, which is economical and generates less surge voltage, by utilizing melting of a bonding wire of the module element.

〔発明の構成〕[Configuration of the invention]

(発明を解決するための手段) 本発明は、密封された容器内に収容された半導体ペレ
ットと、該容器外に導出される電極端子を備えた電力用
半導体制御素子において、該半導体ペレットと該電極端
子間をワイヤーボンディングにより接続すると共に、該
容器を補強してその中に消弧剤を充填しモジュール素子
を構成する。
(Means for Solving the Invention) The present invention relates to a semiconductor pellet housed in a hermetically sealed container and a power semiconductor control element equipped with an electrode terminal led out of the container. Electrode terminals are connected by wire bonding, and the container is reinforced and an arc extinguishing agent is filled therein to form a module element.

(作用) モジュール素子に過電流が流れたとき、ボンディング
ワイヤの接続部が溶断しアークを出すが消弧剤により冷
却されてアークが消滅し事故電流がしゃ断される。ま
た、モジュール素子の破裂が防げるので破裂防止用の高
速ヒューズが省略でき、インバータブリッジの高速ヒュ
ーズ配線によるインダクタンス分が減少しサージ電圧が
著しく低下する。
(Function) When an overcurrent flows through the module element, the connecting portion of the bonding wire is blown to generate an arc, but the arc quenching agent cools the arc and extinguishes the accident current. Further, since the bursting of the module element can be prevented, the high-speed fuse for preventing the bursting can be omitted, the inductance component due to the high-speed fuse wiring of the inverter bridge is reduced, and the surge voltage is remarkably reduced.

(実施例) 第1図に本発明によるモジュール素子の実施例を示
す。第1図はモジュール素子の構成図で、第4図と重複
する部分には同一番号を付し説明を一部省略する。
(Example) FIG. 1 shows an example of a module element according to the present invention. FIG. 1 is a block diagram of the module element, and the same parts as in FIG.

トランジスタペレット85のコレクタCは銅材82に接着
され、銅材82からボンディングワイヤ86によりコレクタ
電極88にボンディングし、コレクタ端子92として出力す
る。トランジスタペレット85のエミッタEからボンディ
ングワイヤ87により、エミッタ電極89に接続され、エミ
ッタ端子93として出力する。
The collector C of the transistor pellet 85 is adhered to the copper material 82, and the copper material 82 is bonded to the collector electrode 88 by the bonding wire 86 and output as the collector terminal 92. The emitter E of the transistor pellet 85 is connected to the emitter electrode 89 by the bonding wire 87 and is output as the emitter terminal 93.

トランジスタペレット85のベースB(またはゲート)
をボンディングワイヤ91によりゲート電極90に接続しゲ
ート端子94として出力される。
Base B (or gate) of transistor pellet 85
Is connected to the gate electrode 90 by a bonding wire 91 and is output as a gate terminal 94.

モジュール素子は側面カバー95と上面カバー96で成る
ケースにより覆われ、内部には消弧剤97が充填されてい
る。
The module element is covered with a case including a side cover 95 and a top cover 96, and an arc extinguishing agent 97 is filled inside.

ボンディング部A点は銅材82に接続してあるので冷却
効果が良いが、ボンディング部B点はトランジスタペレ
ット85のエミッタE部に接続されているので冷却効果が
悪く、トランジスタ部が劣化したり、過大損失が発生す
ると必ずB点付近で溶断が発生する。B点で溶断が発生
しアークが出たとき周囲の消弧剤97により、アークが消
弧され、事故電流がしゃ断される。この時内部のガス圧
が上昇するのでケースが破裂しないように補強されてい
る。
Since the bonding point A is connected to the copper material 82, the cooling effect is good, but the bonding point B is connected to the emitter E of the transistor pellet 85, so the cooling effect is poor and the transistor part is deteriorated. When excessive loss occurs, the fusing always occurs near point B. When fusing occurs at point B and an arc is generated, the arc is extinguished by the arc extinguishing agent 97 around the arc, and the accident current is interrupted. At this time, the internal gas pressure rises, so the case is reinforced so as not to burst.

第2図にモジュール素子のケースの補強例を示す。通
常のケースでは、ガス圧のために側面カバーが膨らみ破
裂することもあるので第2図に示すように、側面カバー
95に部分的に凸部dを設け補強すると同時に、上下部に
もe,fに示す突起を設けて上、下のケースにはめ込み、
側面カバーの膨れを防止する。
FIG. 2 shows an example of reinforcing the case of the module element. In a normal case, the side cover may swell and burst due to gas pressure. Therefore, as shown in FIG.
95 is partially provided with a convex portion d to reinforce, and at the same time, protrusions e and f are provided on the upper and lower portions to fit in the upper and lower cases,
Prevent side cover swelling.

また、側面カバーの破裂による飛散を防ぐため、ゴム
製のカバー98で周囲を保護することも併用できる。
Further, in order to prevent the side cover from scattering due to bursting, it is also possible to protect the surrounding area with a rubber cover 98.

さらに、側面カバーの強度を増すため繊維(ガラス繊
維等)の混入材を用いることもできる。
Further, in order to increase the strength of the side cover, a mixed material of fibers (glass fiber etc.) can be used.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明によれるば、モジュール素
子の中央に位置するトランジスタ・エミッタのボンディ
ング部が最初に溶断することを利用して、この周囲に充
填して消弧剤によりアークを消弧して事故電流をしゃ断
し、この過程で発生するガス圧による破裂を、ケースを
補強することにより防止することができる。これによ
り、従来使用していた高速ヒューズを省略することがで
き、経済的で小形のインバータブリッジを構成すること
ができる。また、ヒューズ配線に伴うインダクタンス分
が減少するのでスイッチング時のサージ電圧(エネルギ
ー)が減少し、サージ吸収回路の省略または小形化が可
能となり高効率になると同時にサージ電圧減少によりス
イッチング素子の安全動作領域に対してマージンが増加
し、信頼性の高いインバータブリッジが構成できるモジ
ュール素子を提供することができる。
As described above, according to the present invention, the fact that the bonding portion of the transistor / emitter located in the center of the module element is melted first is used to fill the periphery and extinguish the arc with the arc-extinguishing agent. Then, the accident current is cut off, and the rupture due to the gas pressure generated in this process can be prevented by reinforcing the case. As a result, the conventionally used high-speed fuse can be omitted, and an economical and compact inverter bridge can be constructed. In addition, since the inductance associated with the fuse wiring is reduced, the surge voltage (energy) at the time of switching is reduced, which makes it possible to omit or downsize the surge absorption circuit, resulting in high efficiency and at the same time reducing the surge voltage to ensure a safe operating area for the switching element. With respect to the above, it is possible to provide a module element in which a margin is increased and a highly reliable inverter bridge can be configured.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の実施例図、第2図は本発明の部分実施
例図、第3図,第6図,第7図は従来のモジュール素子
を用いたインバータブリッジの構成図、第4図,第5図
は一般的なモジュール素子の構成図、第8図は本発明に
よるモジュール素子を用いたインバータブリッジの一実
施例図である。 1……直流電源、2,8,12……コンデンサ 3,31,32……ヒューズ 4……トランジスタブリッジ、5……電動機 15……抵抗 71,72……本発明によるモジュール素子 80……銅ベース、81……絶縁セラミックス 82,83,84,88,89……銅材 86,87,91……ボンディングワイヤ 95,96……カバー、97……消弧剤 92,93,94……端子
FIG. 1 is an embodiment diagram of the present invention, FIG. 2 is a partial embodiment diagram of the present invention, and FIGS. 3, 6, and 7 are configuration diagrams of an inverter bridge using a conventional module element. FIG. 5 and FIG. 5 are configuration diagrams of a general module element, and FIG. 8 is an embodiment diagram of an inverter bridge using the module element according to the present invention. 1 ... DC power supply, 2,8,12 ... capacitor 3,31,32 ... fuse 4 ... transistor bridge, 5 ... motor 15 ... resistor 71,72 ... module element according to the present invention 80 ... copper Base, 81 …… Insulating ceramics 82,83,84,88,89 …… Copper material 86,87,91 …… Bonding wire 95,96 …… Cover, 97 …… Arc extinguishing agent 92,93,94 …… Terminal

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】密封された容器内に収容された半導体ペレ
ットと、該容器外に導出される電極端子を備えた電力用
半導体制御素子において、該半導体ペレットと該電極端
子間をワイヤーボンディングにより接続すると共に、該
容器内に消弧剤を充填したことを特徴とするモジュール
素子。
1. A power semiconductor control device comprising a semiconductor pellet housed in a sealed container and an electrode terminal led out of the container, wherein the semiconductor pellet and the electrode terminal are connected by wire bonding. In addition, the module element is characterized in that the arc-quenching agent is filled in the container.
JP2008216A 1990-01-19 1990-01-19 Module element Expired - Lifetime JP2677697B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008216A JP2677697B2 (en) 1990-01-19 1990-01-19 Module element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008216A JP2677697B2 (en) 1990-01-19 1990-01-19 Module element

Publications (2)

Publication Number Publication Date
JPH03214657A JPH03214657A (en) 1991-09-19
JP2677697B2 true JP2677697B2 (en) 1997-11-17

Family

ID=11687028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008216A Expired - Lifetime JP2677697B2 (en) 1990-01-19 1990-01-19 Module element

Country Status (1)

Country Link
JP (1) JP2677697B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1941362B (en) * 2005-09-27 2010-05-12 塞米克朗电子有限及两合公司 Semiconductor power module with excess current protection unit

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3612226B2 (en) * 1998-12-21 2005-01-19 株式会社東芝 Semiconductor device and semiconductor module
DE10200372A1 (en) * 2002-01-08 2003-07-24 Siemens Ag Power semiconductor module has one contact surface of semiconductor element contacting metallized structure via solder material and second contact surface contacting metallized structure via bonding wire
ATE514187T1 (en) * 2005-09-27 2011-07-15 Semikron Elektronik Gmbh POWER SEMICONDUCTOR MODULE WITH OVERCURRENT PROTECTION DEVICE
US9178410B2 (en) * 2012-01-06 2015-11-03 General Electric Company Adaptive power conversion system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1941362B (en) * 2005-09-27 2010-05-12 塞米克朗电子有限及两合公司 Semiconductor power module with excess current protection unit

Also Published As

Publication number Publication date
JPH03214657A (en) 1991-09-19

Similar Documents

Publication Publication Date Title
US5757599A (en) Protection arrangement for a switching device
US5859772A (en) Parallel connection of controllable semiconductor components
US6268990B1 (en) Semiconductor protection device and power converting system
US5123746A (en) Bridge type power converter with improved efficiency
JP3193827B2 (en) Semiconductor power module and power converter
JP2008235502A (en) Resin-sealed semiconductor device
JP6815524B2 (en) Power converter
US6100745A (en) Combination positive temperature coefficient resistor and metal-oxide semiconductor field-effect transistor devices
JP2677697B2 (en) Module element
JP3292614B2 (en) Power module element
KR920001401B1 (en) Semiconductor device
JP6395164B1 (en) Power converter
JP2000150776A (en) Semiconductor module
KR102612691B1 (en) Transient voltage suppression device with thermal blocking
JPH1012806A (en) Semiconductor device
JP3176306B2 (en) Combination structure of IGBT and freewheeling diode
JP2807297B2 (en) Bridge circuit of semiconductor switch element
JP2000324797A (en) Snubber device
JPH0378432A (en) Protective circuit for transistor bridge
JP6797289B2 (en) Power converter
CN110310944A (en) A kind of large power semiconductor device with failure open circuit feature
JP3991581B2 (en) SSR
CN218783732U (en) Semiconductor circuit with a voltage regulator circuit
JP2003086753A (en) Emitter wiring structure of semiconductor chip, and modular semiconductor device using it
CN114765163A (en) Semiconductor device with a plurality of semiconductor chips