JP2635031B2 - Mutual coupling of parallel computers - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mutual connection method of element processors of a parallel computer, and particularly to a switch configuration suitable for a case where communication between processors is irregular and high reliability is required. About.

[Conventional technology]

A conventional device is a method in which adjacent ones of element processors arranged in a lattice are connected to each other as described in JP-A-58-181168, or described in JP-A-58-181166. In many cases, a method of connecting all the element processors with a cross-by-switch is used. In recent years, as described in the following document 1, a method of connecting all processors by a multi-stage switch has attracted attention.

Literature 1: Proceedings of the Ninetains Anyu Hawaii Hawaii International Conference on System Sciences, 1986, 214
Page to page 221 (Proceedings of the Nineteenth Annua
l Hawaii International Conference on System Scienc
es, 1986, pp. 214-221) [Problems to be Solved by the Invention] Among the above conventional techniques, the grid-like coupling method is very inefficient for irregular interprocessor communication, and the complete crossbar coupling method is Although arbitrary high-speed connection is possible, there is a problem that the hardware scale increases in proportion to the square of the number of element processors, so that it cannot be applied to a large-scale parallel computer. In addition, the multistage switch can realize arbitrary coupling on a relatively small hardware scale, but efficiently performs a grid-like calculation (a calculation for obtaining a state of a grid-like target system by an iterative method) which is a mainstream of large-scale calculation. And it takes a long time to communicate.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inter-processor interconnection method that can realize arbitrary inter-processor coupling with a relatively small hardware scale, can perform high-speed communication, and can also perform grid-like computation with high efficiency. It is in.

[Means for solving the problem]

The above object can be achieved by providing a cross bus switch having excellent basic performance as a coupling method and providing the cross bus switch for each row and each column of a processor group arranged in a two-dimensional array. Because even if the total number of processors is large,
Since the number of units per row or column is small, it is easy to combine them with a cross bus switch.
In addition, a processor may send data to an appropriate relay processor using, for example, a row-oriented switch, for a processor to which it cannot directly receive data due to a (single) row or column cross bus switch to which the processor has direct access. Next, since the relay processor can always send the data by resending the data using the switches in the column direction, communication between the processors can be realized. Further, since each processor can immediately access the processors adjacent in the east-west direction by the switches in the row direction and the processors adjacent in the north-south direction by the switches in the column direction, the grid calculation can be performed with high efficiency.

[Action]

N = α + β (α, β: positive integer) for each element processor
A bit identification number is assigned, and the lower α bit is a vertical position (row number) in a processor group arranged in a two-dimensional array.
So that the upper β bit indicates the horizontal position (column number). If the switch in charge of the row is to decode only the upper β bit of the preceding processor number attached to the head of the communication packet and the switch in charge of the column is to decode only the lower α bit and send the packet, the switch in the source processor and the destination If the row numbers or column numbers of the processors are the same, only the column or row switch is used once, and even if both are different, they are used only once (two times in total), and can always be sent to any predecessor. it can.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to FIG.

The entire system is configured as a set of row cross bus switches 1, column cross bus switches 2, and element processors 3. Element processors are numbered sequentially as shown. In the example of FIG, 2 ⁴ from 0000 to 1111 have been identified. These processors can be viewed as one-dimensional or two-dimensional arrays, as shown in FIG. When viewed as a two-dimensional array, it is necessary that the vertical and horizontal arrays have an array configuration of a power of two. Α of vertical 2
When the power and width are 2 to the power of β, the lower α bit of the processor number indicates the vertical position and the upper β bit indicates the horizontal position. Hereinafter, a processor group having the same lower α bit of the processor number is referred to as the same row processor group, and a processor group having the same upper β bit is referred to as the same column processor group.

A cross bus switch that completely connects the same row processor group is called a row cross bus switch, and a cross bus switch that completely connects the same column processor group is called a column cross bus switch. Each element processor can be associated with only one other element processor for one row or column cross path switch. Therefore, when there is no competition, 2 β powers or 2
There may be α independent power transmission paths.

As shown in FIG. 2, each element processor has a processing unit 31 and a memory 32 like a normal processor, and also exchanges data with a communication unit 33 and a row or column cross bus switch 1, 2. It has an input / output port 34.

Next, a method of performing communication using a row or column cross bus switch will be described. The communication unit of each processor is
The packet shown in FIG. 3 is knitted. The processor number of the processor to which data is to be sent is attached to the head of the packet as a switch address, and stored in the input / output port for exchanging data with the row or column cross bus switch. The lower α bit of the processor number is hereinafter referred to as SN bit, and the upper β bit is referred to as EW bit. At this time, when the EW bit of its own processor number is equal to the EW bit of the processor to which data is sent, the communication unit outputs a packet to the column cross bus switch, and otherwise outputs a packet to the row cross bus switch.
The column cross bus switch selects only the SN bit and sends a packet to the processor whose SN bit of the processor number in the responsible column processor group is equal to it. The row cross bus switch selects only the EW bit, and sends a packet to the processor whose EW bit of the processor number in the assigned row processor group is equal to the EW bit. When the communication unit of each processor receives the packet, it checks the switch address, and if it is not itself (because it is a packet received from the row cross bus switch), it sends it out again to the column cross bus switch. This time the SN bit is chosen and reaches the final destination processor. This will be described using an example.

Consider the case where data is sent to processors 0111 to 1101 and 0100 in FIG. When the packet is sent to the processor 1101, the EW bit is different, so that the packet shown in FIG. 3B is sent out to the row cross path switch. The row cross bus switch sees the EW bit or 11, and sends a packet to processor 1111. In the communication unit of the processor 1111, since the switch address 1101 of the packet is not equal to itself, the packet is retransmitted to the column cross bus switch. In the column cross bass switch
Look at SN bit 01 and send it to processor 1101. When the data is sent to the processor 0100, the data is sent to the column cross bus switch because the EW bits are equal (FIG. 3 (c)). In this case, it reaches processor 0100 directly.

If the element processor at the relay point breaks down or a deadlock occurs with the element processor at the transmission source, another transfer path is re-established for transmission. At this time, the route resetting bit in the packet is set to 1 and the packet is retransmitted to the column cross bus switch. The communication unit of each element processor that receives the packet whose route reset bit is 1 automatically bypasses the failure part by retransmitting the packet to the row cross bus switch. In the above example, if the processor 1111 fails, 0111 → 0101 → 1101
The packet is sent along the route. FIG. 5 is a flowchart of the processing procedure of the communication unit.

The mutual coupling method of the present invention, the lattice-like coupling (connection only to the east-west-north-south element processor) and the complete cross-path switch (connection to any processor and cross-bus switch), which are conventional representative coupling methods, Compare. The distance between processors and the number of switching elements are taken as comparison items. The inter-processor distance is the number of times of switching until communication becomes possible, and is 1 when a direct communication path exists. The number of switching elements is the number of switching elements existing on all communication paths. The former is an evaluation scale of communication efficiency or communication speed, and the latter is an evaluation scale of hardware scale. N × for simplicity
Consider an array of N element processors. At this time, the distance between the processors is as follows.

Complete cross bus switch connection 1 The present invention 1-2 Complete cross bus switch coupling 1 Present invention 1-2 The number of switching elements is as follows.

Lattice connection 2 (N-2) ² +4 (N−
1) Complete cross-path switch N ^{4 The} present invention 2 (N-1) N ^{2 In} other words, the present invention has the same communication capability even though the hardware scale is the first order lower than that of the complete cross-bus switch. is there. For example, if N = 100, the inter-processor distance and the number of switching elements are as follows.

Lattice connection 70,19604 Perfect cross bass switch connection 1,10 ⁸ Invention 1-2,1.98 × 10 ⁶ [Effects of the invention] According to the present invention, the coupling degree of freedom among element processors applied to a parallel computer is the highest. High degree of freedom and a degree of freedom close to that of full cross-bath switch coupling, while enabling mutual coupling with a small hardware scale.
In a large-scale parallel computer having a large number of element processors, there is an effect that arithmetic processing including irregular communication can be realized which cannot be handled by the grid connection method which has conventionally been mainstream. Applications include advanced image processing centered on FFT (Fast Fourier Transform) processing, reactor safety analysis using the node junction method, elimination of simultaneous linear equations with large sparse matrices, etc. A group of problems that conventional parallel computers could not handle efficiently due to communication difficulties,
Particularly effective. However, problems that are suitable for lattice-like coupling, such as fluid calculation and particle tracking calculation, can be handled in the same manner.

[Brief description of the drawings]

FIG. 1 is a conceptual configuration diagram of a matrix cross bus switch which is an interconnection method of the present invention, FIG. 2 is a configuration diagram of an element processor using a matrix cross bus switch, FIG. 3 is a configuration diagram of a transmission packet, and FIG. FIG. 5 is a flowchart showing an example of processor numbering, and FIG. 5 is a flowchart of a processing procedure in the communication unit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazuo Nakao 1099 Ozenji Temple, Aso-ku, Kawasaki City Inside System Development Laboratory, Hitachi, Ltd. (56) References JP-A-63-278170 (JP, A) JP-A-64- 4856 (JP, A) JP-A-1-131950 (JP, A) Yoichi Hamasaki, Yoshikuni Okada, "Kernel of Dialog g. H", Proc. Of the 33rd IPSJ Annual Conference (I)), (1986) p. 357-358 Suzuki Setsu, et al., "Concept of Massively Parallel AI Machine", Proc. Of the 35th IPSJ Annual Convention (late 1987) (I), (1987) 135-136 Suzuki Setsu, et al., "Architecture of Parallel AI Machine Prodigy", Proc. Of the 36th Annual Meeting of the Information Processing Society of Japan (Early 1988) (I), (1988) P. 255- 256

Claims (1)

(57) [Claims] 1. A vertical 2 ^alpha number, (the alpha and beta positive integer) horizontal 2 ^beta pieces in the mutual coupling type parallel computer having a plurality of element processors arranged in a grid-like, for each row of said element processors has a line crossbar switch to another full coupling between 2 ^beta number of element processors belongs the line respectively, mutually fully bonded between 2 ^alpha number of element processors belonging to the column for each column of said element processors Each of the element processors includes, when the element processor is a data transmission source, the transmission data including an α-bit vertical address and a β-bit horizontal address in the transmission data. The communication packet is organized by adding the destination address of the above, and one of the row crossbar switch and the column crossbar switch is selected to output the communication packet, One, the row crossbar switch,
When a communication packet is input from one of the column crossbar switches, it is determined whether or not its own element processor is the processor of the destination address. If not, the communication packet is sent to a crossbar switch different from the crossbar switch that input the communication packet. A mutual connection method for parallel computers, comprising a communication unit for transferring data.