JP2583506B2 - Data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing technique and a technique particularly effective when applied to an instruction format in a system of a program control system. The present invention relates to a technology that is effective for the configuration method.

[Conventional technology]

Instructions of the program control system include two-operand instructions that use two operands when executing the instruction,
There are a one-operand instruction that uses one operand, a zero-operand instruction that does not require an operand, and the like. Of these, in the two-operand instruction, it is necessary to calculate the effective address of the operand twice, and there have conventionally been two methods for configuring the two-operand instruction. One method is to put all the information necessary for calculating an operation code and two operands in one word (unit for addressing an instruction) (Hitachi, Ltd., September 1982, "Hitachi microcomputer, SEMICONDUCTER DATA BOOK, 8/16 bit microcomputer", pp. 945 to 952).

[Problems to be solved by the invention]

With such an instruction format, an operation code (op code) and information necessary for calculating an effective address of an operand can be simultaneously decoded, so that there is an advantage that the execution speed of a two-operand instruction is high. However, 2
If the information required for calculating one operand is put in the same word together with the operation code, the width of the operation designating part becomes narrow, so that the number (type) of instructions is disadvantageously reduced.

In this case, it is conceivable to increase the number of bits in one word in order to prevent the number of instructions from decreasing. However, since the number of bits of information to be decoded at a time also increases, the circuit scale of the decoder becomes extremely large.

On the other hand, as another example of the configuration method of the two-operand instruction,
There is a method in which the operation designating part and the operand designating part are put in different words, and are executed by a plurality of words. According to this instruction method, the field width of the operation specifying section can be made larger than in a method in which the operation specifying section and the operand specifying section are put in the same word, and thus there is an advantage that the number of instructions is increased. Also, since the number of bits of information to be decoded at one time can be reduced,
The circuit size of the decoder can be reduced.

However, in the conventionally proposed method of constructing a one- or two-operand instruction using a plurality of words, a word including an operation designating part, that is, an operation word, is followed by a word including an operand designating part. For this reason, we first need to decode the operation word and know that address calculation is necessary.
Next, the effective address is calculated by decoding the word including the operand designation section, and the operand is fetched based on the calculation result. Then, since the instruction is executed, there is a disadvantage that the execution speed of the instruction is low.

An object of the present invention is to provide an instruction format that can increase the number of instructions (types of instructions) without lowering the execution speed of the instructions.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application is as follows.

In other words, the instruction is divided into a plurality of words, and the first word contains the minimum necessary information for calculating the effective address of the operand. Enable to start calculating the effective address of the operand and fetch the operand before decoding the word containing the part. The operation word is decoded while the address calculation or the operand fetch is being performed, so that the instruction can be executed immediately after the operand address calculation or the operand fetch is completed.

[Action]

According to the above-described means, decoding of a word including the operation designating unit and address calculation or operand fetch operation can be performed in parallel. Therefore, the execution speed of an instruction requiring an operand can be increased. Also,
Since the instructions are divided into a plurality of words, the number of instructions can be increased, and the increase in the scale of the decoder can be limited.

〔Example〕

FIG. 1 shows an embodiment of an instruction format of a two-operand instruction when the present invention is applied to an instruction system in which 16 bits are used as an instruction read unit.

That is, the microprocessor that executes the two-operand instruction of this embodiment uses 16 bits as a basic unit.
Therefore, the address for the instruction also has a minimum unit of 16 bits. In the microprocessor, since these 16 bits are always read at the same time, the arrangement in the 16 bits has no essential meaning. The minimum unit of such an instruction is called a word.

The two-operand instruction shown in FIG. 1 is configured such that the first word at the head includes an operand designating unit EA1 in which information necessary for calculating the effective address of the first operand is coded. Operand designating section EA1 is composed of, but not limited to, 8 bits.

The 8-bit code constituting the operand specification section EA1 is
Although not particularly limited, it is defined as shown in Table 1 below.

However, in Table 1, P is an address pointer size designating bit.
Considered to represent 64 bits. Rn is a register number designation bit, Disp is a displacement value, and Lit is a literal value, that is, an immediate value. SS indicates the bit configuration of the extension part. For example, 01 indicates 16 bits, 10 indicates 32 bits, and 11 indicates 64 bits.

In Table 1, for example, the frame pointer relative short displacement and the stack pointer relative short displacement indicate an address mode with displacement relative to the frame pointer and an address mode with displacement relative to the stack pointer, respectively. These modes are applied when the displacement value is small because the displacement value is 4 bits. According to these modes, since the displacement value is set in the operand designating section, it is not necessary to set the displacement value in a portion such as the extension section.

According to the code configuration of Table 1, the operand is obtained as follows. For example, in the stack pointer relative short displacement, the operand is configured from the content at the address which is increased by the displacement value of the operand designating part with respect to the address value indicated by the stack pointer in the memory address.

In FIG. 1, the first word is provided with a class designation section CL, a mode designation section MD, and a size designation section SZ1 in addition to the operand designation section EA1. The class specification section CL is composed of the upper 5 bits of the 16 bits in this instruction, and when the upper 5 bits are in a specific state (for example, all “1” or all “0”), this instruction Specifies that this is an instruction.

The mode designating unit MD and the size designating unit SZ1 are composed of 1 bit and 2 bits, respectively, and each code is defined as shown in Table 2, for example. That is, the mode designating unit MD designates whether or not to fetch the operand after calculating the address. Some instructions perform only address calculation without performing operand fetch and put the result in a desired register. Therefore, the instruction can be identified using this bit.

On the other hand, in the size specification section SZ1, the operand size is 8,1
Specify whether it is 6, 32 or 64 bits. As a result, data of the number of bits corresponding to the code can be extracted from the memory or the register.

In some 2-operand instructions, one or more words or two or more extensions may be required to store displacement (or offset) according to an addressing mode such as register relative. Therefore, in this embodiment, the extension part EX1 of the first operand is configured to continue to the second word or less after the first word.

The n-th word following the first operand extension EX1 is provided with an operation designator OP for designating details of the operation such as addition and subtraction. However, the width of the operation specification part OP does not need all 16 bits in relation to the type of the required instruction. Therefore, in this embodiment, the upper 6 bits of the n-th word are used as the operation specifying unit OP, and the remaining field has a second operand specifying unit EA2 having an 8-bit width and a 2-bit width specifying the size of the second operand. The unit SZ2 is provided.

In this way, the operation specifying unit OP and the second operand specifying unit EA2 form the n-th word, and if necessary, the expansion unit EX2 of the second operand sets the (n + 1) th word next to the n-th word. It is as follows.

FIG. 4 shows an example of a hardware configuration of a microprocessor operated by an instruction system having two operand instructions according to the present invention.

The microprocessor of this embodiment includes a microprogram control type control unit. That is, a micro ROM (read only memory) 2 in which a micro program is stored is provided in the LSI chip 1 constituting the microprocessor. The micro ROM 2 is accessed by the micro address generating circuit 5 and sequentially outputs micro instructions constituting a micro program.

The micro address generation circuit 5 is supplied with a signal obtained by decoding the code of the macro instruction fetched into the instruction register 3 by the instruction decoder 4. The micro address generation circuit 5 forms a corresponding micro address based on this signal and supplies it to the micro ROM 2. As a result, the first instruction of a series of microinstructions for executing the macro instruction is read. The micro-instruction code forms control signals for various temporary registers, data buffers, an execution logic unit ALU, an execution unit 6 including an address calculation unit AU, and the like.

2 of a series of microinstructions corresponding to macroinstructions
The reading of the micro-instruction after the first is performed by supplying the code of the next address field of the micro-instruction read immediately before to the micro ROM 2. That is, a microinstruction latch 9 for holding the next in the immediately preceding microinstruction is provided, and based on the output of the microinstruction latch 9 and the address from the microaddress generation circuit 4,
The reading of the micro-instruction after the first is performed. The series of microinstructions thus read is decoded by the microinstruction decoder 10, and the output control signal controls the execution unit 6 to execute the macroinstruction.

The address calculation unit AU calculates an extension part EX for specifying the address of the operand (for example, the address of the operand based on the information of the second word shown in FIG. 1 and the information in a predetermined register in the execution unit 6). The extension unit EX is supplied to the address calculation unit AU via the extension unit dedicated register 11 without being decoded by the instruction decoder 4. Also, an instruction including the operand designating unit EA (for example, as shown in FIG. 1) The address calculation unit AU is controlled by address calculation control information INF obtained by decoding the first word).

In this embodiment, although not particularly limited, a buffer storage system is adopted, a cache memory 7 is provided in the microprocessor LSI, and program data having a high access frequency among the data in the external memory 8 is stored in the cache memory 7. Registered within. This speeds up the loading of the program.

As described above, in this embodiment, since the two-operand instruction is composed of a plurality of words, the field width of the operation specifying unit OP can be made large.
Therefore, it is possible to have many types of instructions. Moreover,
Since the first word contains information necessary for calculating the effective address of the first operand (source operand), the first word
Simply fetching a word and decoding it can start address calculations for the operands. That is, since the extension of the second word is supplied to the address calculation unit AU without being decoded, the address calculation can be started immediately after the decoding of the first word is completed. While the address calculation is being performed, the instruction register 3 and the instruction decoder 4 are vacant. Therefore, during the address calculation or the fetch of the first operand by this address, the n-th word including the operation specifying unit OP is fetched and the operation is performed. The reading operation of the microinstruction corresponding to the code can be performed.

Note that operand fetch refers to storing the contents of an operand stored in the external memory 8 or the like in a predetermined register in the execution unit 6, and an I / O receiving a control signal output from the microinstruction decoder 10. This is executed by the O controller 12 or the like. The address of the operand is calculated by the address calculation unit AU.

FIG. 5A shows an embodiment of the format of a two-operand instruction composed of three words. FIG. 5 (B) shows an execution sequence when an instruction in the format shown in FIG. 5 (A) is executed by the microprocessor shown in FIG. As shown in FIG. 5 (A), the first word includes the first operand specification field EA1, the second word is provided with the first operand specification extension field EX1, and the third word is , An operation code designation field OP and a second operand designation field EA2. As shown in FIG. 5 (B), first, the first word is decoded by the instruction decoder 4 shown in FIG. 4 during the first machine cycle MC1 (51), and it is necessary to calculate the address of the operand. Information INF and address information of the micro ROM are formed. Next, in machine cycle MC2, the second
The address of the first operand is calculated based on the word information and the address calculation information INF (52). In machine cycle MC2, execution of the above address calculation (5
Along with 2), a micro instruction is read from the micro ROM (53). When this microinstruction indicates the fetch of the operand, the operand fetch is executed in machine cycles MC3 and MC4 (5
Four). In the machine cycle MC3, the third word is decoded (55) together with the operand fetch operation (54), and the address information of the micro ROM is formed. Machine cycle based on this address information
In MC4, a micro instruction is read (5
6). This microinstruction includes control information for executing the operation specified by the operation code specification field OP. Also, the operands required to perform this operation have already been fetched (54).
, The operation can be executed immediately from the machine cycle MC5 (57). Since this three-word instruction does not have an extension field for specifying the second operand, address calculation using this extension field is not performed. Further, this embodiment shows a case where the fetch of the second operand is unnecessary. The case where the fetch of the second operand is unnecessary is, for example, the case where the position of the second operand is a register in the microprocessor.

As described above, according to the instruction format of the present invention, while the microprocessor prepares the operands necessary for executing the instruction, that is, the addresses of the operands are calculated and the contents of the operands are fetched into the predetermined registers. In the meantime, the operation code can be decoded. Therefore, it is not necessary to provide a dedicated time for decoding the operation code. Therefore, the speed of executing the instruction can be increased.

In the above embodiment, the decoding step of the third word (55)
And the operand fetch stage (54) overlap, but need not be limited to this. That is, the decoding step (55) of the third word may be overlapped with the address calculation step (52). By doing so, for example, if the operand fetch stage (54) does not exist,
The instruction execution stage (57) can be started one machine cycle earlier.

FIG. 6A shows an embodiment of the format of a two-operand instruction composed of four words. In the first word, the first operand specification field EA
1, the second word is provided with a first operand designation extension field EX1, the third word is provided with an operation code designation field OP and the second operand designation field EA2, and the fourth word is designated with a second operand designation field EA2. An operand specification extension field EX2 is provided. FIG. 6 (B) shows an execution sequence when an instruction in the format shown in FIG. 6 (A) is executed by the microprocessor shown in FIG. First, the first word is decoded by the instruction decoder 4 shown in FIG. 4 during the first machine cycle MC1 (61), and information INF necessary for calculating the address of the operand, address information of the micro ROM, and the like are obtained. It is formed. Next, machine cycle MC2
, The information of the second word and the address calculation information IN
Based on F, the address of the first operand is calculated (62). In the machine cycle MC2, the execution of the address calculation (62) and the reading of the microinstruction from the microROM are performed (63). When the microinstruction indicates the fetch of the operand, the operand fetch is executed in the machine cycles MC3 and MC4 (64). In this machine cycle MC3,
Along with the operand fetch operation (64), decoding of the third word is performed (65), and information INF necessary for calculating the address of the second operand, address information of the micro ROM, and the like are formed. Also machine cycle MC4
, The information of the fourth word and the address calculation information
Based on INF, the address of the second operand is calculated (66). In the machine cycle MC4, the execution of the address calculation (66) and the reading of the micro instruction from the micro ROM are performed (67). When this microinstruction indicates the fetch of the operand, the operand fetch is executed in machine cycles MC5 and MC6 (68). Also read micro instruction (67)
Includes control information for executing the operation specified by the operation code specification field OP. The operands required to perform this operation are:
Since the data has already been fetched (68, 69), the operation can be executed immediately from the machine cycle MC7 (69).

Thus, using the instruction format of the present invention,
The operation code can be decoded while the microprocessor prepares the first operand required for the instruction execution, that is, while calculating the address of the operand and fetching the contents of the operand into a predetermined register. it can. Therefore, it is not necessary to provide a dedicated time for decoding the operation code. Therefore, the speed of executing the instruction can be increased.

In the above embodiment, the case of a two-operand instruction has been described.
The present invention is applicable even in the case of a one-operand instruction. This is because if the operation code can be decoded in parallel with the preparation of the first operand, the effect of the present invention can be obtained.

Further, the plurality of instructions for operating the microprocessor need not all be constituted by the instruction format according to the present invention, and may include an instruction format different from that of the present invention as necessary. Accordingly, a series of instructions can be formed by using the instructions in the format shown in FIG. 1 and the instructions in the formats shown in FIGS. 2 and 3. In such a case, if a period during which the microprocessor does not substantially operate is included between the execution stage of one instruction and the execution stage of the next instruction, the speed of executing a series of instructions is reduced. Therefore, for example, as shown in FIG. 5 (B), it is preferable to immediately continue the operation (54, 57) based on the next instruction immediately after the execution (58) of a certain instruction.

FIG. 2 shows a configuration example of a one-operand instruction, and FIG. 3 shows a configuration example of a zero-operand instruction. These instructions have a 2-bit class designation section CL, which designates a one-operand instruction or a zero-operand instruction, respectively.

The one-operand instruction has an operation specifying part EA and an operand size specifying part SZ, similarly to the n-th word of the two-operand instruction. Thus, the one-operand instruction can quickly calculate the effective address of the operand and execute the instruction. In the case where the one-operand instruction also has an extension part as in the case of the two-operand instruction, the extension part is inserted in the second word or less following the above-mentioned word including the operation designating part OP and the operand designating part EA. To be. The configuration of the operand specification unit EA is the same as that of the operand specification units EA1 and EA2 of the two-operand instruction.

On the other hand, in the 0-operand instruction, all the bits other than the class designation section CL are used for the operation designation section.

〔The invention's effect〕

 According to the present invention, the following effects can be obtained.

The instruction is divided into multiple words and the first
The word contains information necessary for calculating the effective address of the operand, and the word including the operation specification part is configured to follow, so that the calculation of the effective address of the operand can be started before decoding the word including the operation specification part. In addition, the operation word is decoded during the address calculation and the operand fetch, and the instruction can be executed immediately after the operand address calculation and the operand fetch are completed. The effect is that the number of instructions can be increased.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in the above-described embodiment, the description has been given of the two-operand instruction format when the instruction fetch unit is 16 bits. However, the present invention is not limited to the case where the instruction constituent unit is 8 bits or 32 bits. Can be. In addition, according to the above embodiment, when the unit of the instruction is less than 16 bits (for example, 8 bits), one operand instruction is converted into one word (in this case, 8 bits).
Bit). Therefore, even when such a one-operand instruction is configured, the present invention can be applied so that a word including an operand specifying part is followed by a word including an operation specifying part.

In the above description, mainly the case where the invention made by the present inventor is applied to the instruction format of the microprocessor, which is the field of application as the background, has been described. It can be used for a general command format of a data processing system of a program control method.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration example of an instruction format according to the present invention, FIGS. 2 and 3 are explanatory diagrams showing a configuration example of a one-operand instruction and a zero-operand instruction, and FIG. FIG. 5A is a block diagram showing a configuration example of a microprocessor for executing such an instruction, FIG. 5A is an example of an instruction format according to the present invention, and FIG. FIG. 6A is a diagram showing another embodiment of the instruction format according to the present invention, and FIG. 6B is a diagram showing the execution procedure of the instruction shown in FIG. FIG. 1 .... microprocessor, AU ... address calculation unit, ALU ... arithmetic logic unit, INF ... address calculation control information.

Continuation of the front page (56) References JP-A-57-8851 (JP, A) JP-A-62-107339 (JP, A) JP-A-50-92058 (JP, A) JP-A-59-160239 (JP, A) JP-A-62-197830 (JP, A) JP-A-63-55637 (JP, A)

Claims (2)

(57) [Claims] An instruction register for fetching an instruction, an instruction decoder for decoding an instruction fetched in the instruction register, and a series of microinstructions for executing a process corresponding to the instruction are stored in the instruction decoder. A micro-program memory from which a predetermined micro-instruction is read by a decode signal from a micro-instruction, a micro-instruction decoder for decoding a micro-instruction read from the micro-program memory, and an execution unit controlled by a decode signal from the micro-instruction decoder A first word including a class designating unit for designating whether the instruction is a two-operand instruction using two operands, and a first operand designating unit having information necessary for calculating an effective address of the first operand; , Operation to specify operation details A two-operand instruction having an instruction format including a translation designation part and a succeeding word arranged after the first word including a second operand designation part having information necessary for calculating an effective address of the second operand. A data processing device, wherein the execution unit is controlled by a decode signal from the microinstruction decoder and performs first operation means for performing an operation instructed by the operation designating unit;
A register used for the operation; and second operation means controlled by a decode signal from the instruction decoder to calculate an effective address of the first operand and the second operand. In parallel with the second operation means calculating the effective address of the first operand and obtaining the first operand in accordance with the decoding result of the first word included in the operand instruction, the instruction decoder The subsequent word included in the instruction is decoded, and based on the decoding result of the subsequent word, the second arithmetic unit calculates the effective address of the second operand to obtain the second operand, and obtains the second operand. The execution unit uses the second operand and the first operand to A data processing device configured to perform a process specified by an application specifying unit. 2. An instruction register for fetching an instruction, an instruction decoder for decoding an instruction fetched in the instruction register, and a series of microinstructions for executing a process corresponding to the instruction are stored in the instruction decoder. A micro-program memory from which a predetermined micro-instruction is read by a decode signal from a micro-instruction, a micro-instruction decoder for decoding a micro-instruction read from the micro-program memory, and an execution unit controlled by a decode signal from the micro-instruction decoder A first word including a class designating unit for designating whether the instruction is a two-operand instruction using two operands, and a first operand designating unit having information necessary for calculating an effective address of the first operand; , An extension of the first operand specification part A word for an extension part arranged next to the first word, an operation designating part for designating details of the operation, and a second operand designating part having information necessary for calculating an effective address of the second operand. A data processing device capable of executing a two-operand instruction having an instruction format including a subsequent word disposed after the first word, wherein the expansion unit word can be directly fetched without passing through the instruction register. A register for unit words, the execution unit is controlled by a decode signal from the microinstruction decoder, and performs first operation means specified by the operation designating unit; and a register used for the operation. And the first operand controlled by a decode signal from the instruction decoder. And second operation means for calculating an effective address of a second operand, wherein the second operation means stores the extension register in accordance with a result of decoding of a first word included in the two-operand instruction by the instruction decoder. In parallel with calculating the effective address of the first operand using the extension word fetched in the above and obtaining the first operand, the instruction decoder replaces the subsequent word included in the two-operand instruction with Decoding, and based on the decoding result of the succeeding word, the second arithmetic unit calculates the effective address of the second operand to obtain the second operand, and obtains the second operand and the first operand. The execution unit performs the process specified by the operation specifying unit using the operand A data processing device characterized by being configured as described above.