JP2022553339A - Inverter circuit and method, e.g. for use in power factor correction - Google Patents

Abstract

An inverter circuit receives an AC input signal and performs an electrical inversion function using at least two bidirectional switches between the input terminal and the junction node. A resonant circuit is formed by a primary inductor between the junction node and the second node and a capacitor arrangement between the second node and the input terminal.

Description

The present invention relates, among other things, to an inverting circuit and method that eliminates the need for a diode bridge rectifier, eg, to form part of a power factor correction circuit.

A function implemented in mains (or other AC) powered power converters is power factor correction (PFC). The power factor of an AC power system is defined as the ratio of the real power flowing to the load to the apparent power in the circuit. A power factor less than 1 means that the voltage and current waveforms are not in phase and/or have the same shape. Phase shift, for example, reduces the instantaneous product of the two waveforms and the average power delivered over a mains power cycle. Active power is the capacity of a circuit to do work in a specified amount of time. Apparent power is the product of the circuit's current and voltage. Apparent power may be greater than real power due to energy stored in the load and returned to the source, or due to non-linear loads that distort the waveform of the current drawn from the source.

When the power supply is operating at a lower power factor, the load will draw more current for the same amount of useful power delivered than it would at a higher power factor.

The power factor can be enhanced using power factor correction. For linear loads, this may involve the use of a passive network of capacitors or inductors. Nonlinear loads generally require active power factor correction to cancel distortion and increase the power factor. Power factor correction brings the power factor of an AC power circuit closer to unity, for example by supplying opposite sign reactive power with the addition of capacitors or inductors which act to counteract the inductive or capacitive effects of the load.

Active PFC utilizes power electronics to alter the waveform of the current drawn by the load to improve the power factor. Active PFC circuits are most often based on boost switch mode converter topologies. Non-isolated flyback or isolated flyback converter topologies can also be used. Active power factor correction can be single or multi-stage.

In the case of a switched mode power supply, for example, a PFC boost converter is inserted between the reservoir capacitor and the bridge rectifier at the output of the PFC circuit. A boost converter may, for example, try to maintain a constant DC bus voltage at its output while drawing a current that has the same frequency and shape as the line voltage and is always in phase with the line voltage. . A separate switch-mode converter within the power supply may produce the desired output voltage or current from the DC bus. This forms a two-stage system and is a common configuration for high power LED applications (eg, greater than 25 W up to about 1000 W).

Because of their very wide input voltage range, many power supplies with active PFC can automatically adjust to operate on AC power sources from about 110V to 277V, for example.

Diode bridge rectifiers used in typical boost converter PFC circuits occupy considerable space and contribute significantly to the power consumption of the circuit.

Bridgeless boost converters and boost derived converters have already been proposed since eg the 1980s.

More recently, in conjunction with the emerging high voltage (“HV”) GaN transistors (e.g., 650V), conventional boost PFC circuits with diode rectifier bridges have been converted to bridgeless versions in various industrial applications. has been replaced.

In that case, bridge rectifier losses can be significantly reduced. For example, at 120Vac or for a wide mains voltage range (“IntelliVolt®”), the worst-case losses in the mains input rectifier account for about ⅓ of the total PFC front-end losses. Become.

A bridgeless version of the boost converter can be obtained relatively easily, such as by connecting a mains voltage source and a boost inductor in series between two transistor half-bridge junction nodes, these If so, divide the voltage rectification and boosting operations so that the voltage across the bridge is still unipolar. In that case, electrolytic bus capacitors may be used.

However, this approach does not apply to PFC stages with resonant half- or full-bridge converters.

It is also known that monolithically integrated bidirectional switches can be built based on GaN HEMT (High Electron Mobility Transistor) technology. For example, a common drain type bi-directional GaN e-mode HEMT is disclosed.

An isolated bridgeless PFC converter using a semi-resonant boost converter with an active clamp capacitor and a polarity reversal circuit, "Single stage true bridgeless AC/DC power factor corrected converter" by C.D. Davidson, 2015 IEEE International Telecommunications Energy Conference (INTELEC).

In this proposal, three bidirectional switches formed by separate back-to-back connected IGBTs and MOSFETs are employed.

A disadvantage of the typical boost converter type bridgeless front end is the limited size reduction potential. For example, the circuit described in the reference by C.D. Davidson has relatively bulky clamp and polarity reversal circuits, relatively large boost inductors and transformers, and additional bidirectional switches.

The invention is defined by the claims.

According to an example according to one aspect of the invention,
an input for receiving an unrectified AC input signal;
a first terminal and a second terminal for receiving power from the input;
a first bidirectional switch between the first terminal and a junction node;
a second bidirectional switch between the second terminal and the junction node;
a primary inductor between the junction node and a second node;
A bridgeless inverter circuit is provided having a capacitor arrangement between the second node and the first and/or second terminals.

This inverter circuit is "bridgeless" in the sense that no diode bridge is required. This means that the inverter can be used, for example, in a bridgeless power factor correction (PFC) circuit. This inverter circuit combines the size and efficiency advantages of a resonant converter front-end with the benefits of a bridgeless input circuit, loss reduction and power factor improvement. Rectifier-related disturbances are prevented from occurring so that total harmonic distortion (THD) can be made lower.

The capacitor arrangement, for example, comprises a first capacitor between the second node and the first terminal and a second capacitor between the second node and the second terminal.

The first bidirectional switch and the second bidirectional switch preferably comprise anti-series first and second transistors, respectively. In this manner, the switching function of the bidirectional switch is between two said transistors, each of said two transistors having its own gate contact, to create a switching sequence. may be separated and this switching sequence may depend on the polarity at the input. One of the transistors acts as a master and the other as a slave. For example, one of the transistors functions as a switch and the other as a diode, the role depending on the polarity of the input.

Each pair of first and second transistors in series has, for example, a common source or a common drain at a junction node between the first transistor and the second transistor. Thus, common source or common drain connections are possible for the pair of transistors.

The circuit preferably further comprises control circuitry for controlling switching of the transistors. The control circuit may, for example, for each bidirectional switch:
an on mode in which the respective first and second transistors are turned on;
a first transition mode in which the first transistor is turned on and the second transistor is turned off;
and a second transition mode in which the second transistor is turned on and the first transistor is turned off.

Different transition modes are used, for example, during different polarities of the input. For example, the controller
a control sequence for each bidirectional switch utilizing the on mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal;
A control sequence for each bidirectional switch is adapted to implement a control sequence that utilizes the on mode and the second transition mode when the voltage at the first terminal is lower than the voltage at the second terminal. good too.

The control circuit may further be adapted for each bidirectional switch to implement an off mode in which the respective first and second transistors are turned off.

In that case, the controller
a control sequence for each bidirectional switch utilizing the on mode, the off mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal;
When the voltage at the first terminal is lower than the voltage at the second terminal, a control sequence for each bidirectional switch implements a control sequence utilizing the on mode, the off mode and the second transition mode. is adapted for

This provides an alternative control scheme.

Each bidirectional switch comprises, for example, a GaN dual transistor switch.

The present invention also provides a power factor correction circuit comprising an inverter circuit as defined above and an output circuit comprising a secondary inductor coupled to said primary inductor. The power factor correction circuit may further comprise a second inverter circuit as defined above. The capacitor arrangement provides DC blocking and thus may not form part of the resonant tank. The power factor correction circuit may optionally be a resonant circuit, in which case the capacitor arrangement functions as part of a resonant tank.

The invention also provides a resonant converter comprising an inverter circuit as defined above and an output circuit comprising a secondary inductor coupled to said primary inductor.

The present invention is a method for providing electrical reversal,
receiving an unrectified AC input signal at first and second terminals;
controlling switching of a first bidirectional switch between the first terminal and junction node (x) and a second bidirectional switch between the second terminal and junction node (x). the method, wherein a primary inductor is between the junction node and a second node, a capacitor arrangement is between the second node and the first terminal and/or the second terminal;
wherein the method comprises, for each bidirectional switch,
an on mode in which the respective first and second transistors are turned on;
a first transition mode in which the first transistor is turned on and the second transistor is turned off;
and performing a second transition mode in which the second transistor is turned on and the first transistor is turned off.

The method includes:
a control sequence for each bidirectional switch utilizing the on mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal;
when the voltage at the first terminal is lower than the voltage at the second terminal, a control sequence for each bidirectional switch implementing a control sequence that utilizes the on mode and the second transition mode. may

The method may comprise implementing, for each bidirectional switch, an off mode in which the respective first and second transistors are turned off. In that case,
a control sequence for each bidirectional switch utilizing the on mode, the off mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal;
When the voltage at the first terminal is lower than the voltage at the second terminal, a control sequence for each bidirectional switch is configured to utilize the on mode, the off mode and the second transition mode. may

These and other aspects of the invention will be described and clarified with reference to the following embodiments.

For a better understanding of the invention and to show more clearly how it may be embodied, reference will now be made, by way of example only, to the accompanying drawings.
1 shows the front end of a power factor correction circuit with a resonant LLC converter and an inverter with a common source configuration. 4 shows an alternative common drain configuration. For the circuit of FIG. 1, for the portion of the input voltage where the polarity changes (from v(l)>v(n) to v(l)<v(n)), the input AC voltage is on the left and the node x shows the shape of the voltage at The shape of one of the high-frequency pulses is shown on the left when v(l)>v(n), i.e. the left part of FIG. 3, and v(l)<v(n), i.e. the right part of FIG. The shape of one of the high-frequency pulses when is shown on the right. Fig. 2 shows an example schematic of a bi-directional switch and a table of modes of operation; 2 shows a control sequence for the operation of the four transistors in the circuit of FIG. 1; Figure 2 shows the structure of a bi-directional GaN switch; The junction node voltage v(x) and the individual gate drive voltage waveforms for this alternative drive scheme are shown. Figure 9 shows the control sequence for the operation of the four transistors for the drive scheme of Figure 8; 4 shows an alternative configuration of the gate drive circuit;

The present invention will be described with reference to the drawings.

The detailed description and specific examples, while indicating exemplary embodiments of apparatus, systems and methods, are intended for purposes of illustration only and are not intended to limit the scope of the invention. be understood. These and other features, aspects and advantages of the apparatus, systems and methods of the present invention will become better understood from the following description, appended claims and accompanying drawings. It should be understood that the figures are schematic only and are not drawn to scale. It should also be understood that the same reference numbers are used throughout the figures to denote the same or similar parts.

The present invention provides an inverter circuit that receives an AC input signal and uses at least two bidirectional switches between the input terminals and junction nodes to perform an electrical inverting function. A resonant circuit is formed by a primary inductor between the junction node and a second node and a capacitor arrangement between the second node and the input terminal.

FIG. 1 shows the front end of a power factor correction circuit with a resonant LLC converter and an inverter.

Said circuit has an inverter circuit on the input side and a resonant circuit on the output side.

The inverter circuit has an input for receiving the AC input signal V_ac after filtering by the LC filter circuits C_filt1, C_filt2, L_filt1, L_filt2. AC input is the unrectified mains input signal. The input to the inverter circuit has a first terminal T1 and a second terminal T2 for receiving power from the input after the filtering stage. In the example shown, T1 is labeled live (1) and T2 is labeled neutral (n).

A first bidirectional switch BD1 is between the first terminal T1 and the junction node x, and a second bidirectional switch BD2 is between the second terminal T2 and the junction node x.

A primary inductor L1 is provided between the junction node x and the second node N2. A first capacitor C_res1 is between the second node N2 and the first terminal T1, and a second capacitor C_res2 is between the second node N2 and the second terminal T2. These capacitors can be used to form a resonant tank in a resonant power factor correction circuit or resonant converter.

The filtering stage has an LC filter element and no mains rectifier.

The power factor correction circuit has an output stage represented as a DC voltage sink V_out. An output voltage is defined between output nodes N3 and N4. Between N3 and N4 there are two parallel branches each consisting of an inductor (magnetically coupled with inductor L1) and a diode. One of the branches is L2 and D1 and the other is L3 and D2.

There may be additional mains storage capacitors (not shown). This can be considered part of V_out.

Inductors L1, L2 and L3 form a transformer, and capacitors C_res1 and C_res2 form a resonant tank with the inductor of the transformer in some circuit embodiments.

The bidirectional switches BD1, BD2 each comprise a pair of transistor switches. The first high-side bidirectional switch BD1 comprises two anti-series transistors QH1 and QH0. The second low-side bidirectional switch BD2 comprises two anti-series transistors QL1 and QL0. Both the high-side pair GH0, QH1 and the low-side pair GL0, QL1 can be considered to be formed by two individual switches (bottom and top) as shown. Each switch pair may be built by a monolithically integrated device, or by two separate chips that are built into a multi-chip module or simply individually packaged. In either case, there are two gate contacts for each bidirectional switch.

FIG. 1 shows a common-source version in which the contacts between each transistor pair are the source terminals.

FIG. 2 shows an alternative common-drain version in which the contact between each transistor pair is the drain terminal. This drain terminal can be left floating.

An advantage of the common source configuration of FIG. 1 is that less design effort is required for the gate driver since both the top and bottom gates of the pair have the same reference voltage, ie the common source voltage. is.

Gate drive circuitry is not shown. It is supplied by an auxiliary power supply, for example using a bridge rectifier.

The two gates of each bidirectional switch each receive respective gate signals (gH1, gH0, gL1, gL0). One is the master signal and the other is the auxiliary (or slave) signal.

During the positive inverter polarity (ie, v(l)>v(n), eg, throughout the first half of the mains power cycle), the master signal drives the top gates (gH1, gL1). During the negative inverter polarity, the master signal drives the bottom gates (gH0, gL0).

The slave gate can be switched or left on all the time, as described in more detail below. An advantage of switching all four gate signals is that Manchester encoding can be supported in the case of inductive gate drive/gate drive transformers.

FIG. 3 shows the input AC voltage on the left and the voltage at node x on the right for the portion of the input voltage where the polarity changes (from v(l)>v(n) to v(l)<v(n)). It shows the shape of v(x).

The inverter produces a high frequency switched version of the input voltage based on control signals applied to the transistors.

FIG. 4 shows on the left the shape of one of the high frequency pulses when v(l)>v(n), i.e. the left part of FIG. 3, and v(l)<v(n), i.e. , the shape of one of the high-frequency pulses in the right part of FIG. 3 is shown on the right.

Note that v(n) is defined as 0 in these graphs. In the flat portion of the graph of FIG. 4, ie ignoring transients, v(x)=v(l) or v(x)=v(n)=0.

FIG. 5 shows an example schematic of a bidirectional switch and a table of modes of operation. Bidirectional mode is defined when both switches are turned on or off at the same time. If one switch is turned on at a time, the diode mode is defined as shown. FIG. 5 shows a common drain connection.

Each transistor acts as a switch for positive drain-source voltages and as a diode for negative drain-source voltages. The transistor is, for example, a GaN transistor, such as a GaN e-mode HEMT. These have a larger forward-biased voltage in reverse conduction, about 2 V, compared to 0.7 V for pn junction diodes such as those present in Si-MOSFETs. There is no diode in the HEMT, but the transistor can conduct even in quadrant 3 only if the reverse bias voltage exceeds the gate threshold (at a gate-source voltage of 0V), so there is a reverse current at the drain-source terminal. This is how a HEMT behaves when biased.

FIG. 6 shows the control sequence for the operation of the four transistors.

In FIG. 6, v(a,b) indicates the voltage of a with reference to b. For example, v(gH1, sH) denotes the voltage applied to the gate gH1 of transistor QH1 relative to the source voltage sH.

For a transistor, a gate voltage of V1 indicates an on (conducting) state and a voltage of V0 indicates an off state.

Note that control can be based on voltage or current, depending on the type of transistor. Therefore, V0 should be considered more generally associated with OFF commands and V1 more generally associated with ON commands.

Each bidirectional switch has an on mode in which the first and second transistors are turned on (at V1 and V1), and an on mode in which the first transistor is turned on and the second transistor is off (at V1 and V0). ) and a second transition mode in which the second transistor is turned on and the first transistor is turned off (which are V0 and V1).

The upper part of FIG. 6 shows the switching sequence for the positive phase of the AC input, ie when v(l)>v(n) and therefore v(l)>0.

As also shown on the left side of FIG. 4, there are four intervals.

Interval 0 is the transition when v(x) increases from 0 to v(l) at the beginning of a positive v(x) pulse.

Interval 1 is the period of v(x)=v(l).

Interval 2 is the transition when v(x) decreases from v(l) to 0 at the end of the v(x) pulse.

Interval 3 is the period of v(x)=0 between v(x) pulses.

The lower part of FIG. 6 shows the switching sequence for the opposite phase of the AC input, ie when v(l)<v(n) and therefore v(l)<0.

As also shown on the right side of FIG. 4, again there are four intervals.

Interval 4 is the transition when v(x) decreases from 0 to negative v(l) at the beginning of the negative v(x) pulse.

Interval 5 is the period of v(x)=v(l).

Interval 6 is the transition when v(x) increases from v(l) to 0 at the end of the v(x) pulse.

Interval 7 is the period of v(x)=0 between v(x) pulses.

During the positive phase of the live voltage, in intervals 1 and 3, the junction node x is connected live or neutral by a pair in which both transistors are turned on. This is also true for antiphase sections 5 and 7 with negative live voltages.

For opposite transistor pairs, the transistors are individually controlled.

In positive phase, in intervals 1 and 3, only the upper transistors of the opposite pair (hence QL1 and QH1) are in the complementary state, ie off. Thus, during interval 1, QL1 is off, and during interval 3, QH1 is off.

This means that they are subject to the full blocking voltage. The lower transistor (QL0, QH0) of each pair is kept on during the positive phase.

The role of each pair of slave transistors switches between phases.

Thus, in antiphase, in intervals 5 and 7, only the lower transistor of each pair (hence QL0, QH0) is in the complementary state, ie off. This means that they are subject to the full blocking voltage. The upper transistor (QL1, QH1) of each pair is kept on during anti-phase.

Thus, when the voltage at the first terminal is higher (or equal) than the voltage at the junction node and the voltage at the second terminal is lower (or equal) than the voltage at the junction node (and thus in positive phase), each bidirectional switch The control sequence for utilizes the on mode and the first transition mode.

For each bidirectional switch, when the voltage at the first terminal is lower (or equal) than the voltage at the junction node and the voltage at the second terminal is higher (or equal) than the voltage at the junction node (and thus in phase opposition) The control sequence of utilizes the ON mode and the second transition mode.

Using GaN transistors for bidirectional switches allows the switches to be monolithically integrated as shown in FIG.

The structure of FIG. 7 has a silicon substrate 60 , a buffer layer 62 , an i-GaN layer 64 , an i-AlGaN layer 66 and a drain/source contact layer 68 . The gate has a gate stack of p-AlGaN layer 70 and gate electrode layer 72 .

There are various gate structures used for GaN e-mode HEMTs. The structure shown in FIG. 7 employs an additional gate injection transistor (“GIT”, or “p-GaN gate”), which uses voltage rather than voltage to keep the device in on mode. Means that a current must be applied. Voltage drive is the case for an alternative technique using a simple (Schottky) gate structure.

Two transistors with separate gates are side by side. Bidirectional GaN switches benefit from the relatively low on-state resistance of GaN devices, the relatively low output capacitance of GaN devices, and the low gate charge of GaN devices.

For a GaN bidirectional switch based on a voltage-controlled Schottky gate structure, example values for the two gate voltage levels are V1=5V, V0=0V.

In the case of the control scheme of FIG. 6, if the two transistors of the pair are switched in opposition, turning off the transistor subject to the opposite drain-source voltage will force the device to never have a voltage higher than 0.7V or 2V. Don't let it stop you. because it is in diode mode. Thus, the control scheme of FIG. 6 allows the transistor to be turned on throughout the phase (either positive or negative) to keep the gate drive simple and efficient. The master device, controlled by the master signal, is switched to determine whether the bidirectional switch is blocked or conductive, and the slave device remains on.

Alternative gate drive methods are described below in connection with more detailed gate timing schemes.

FIG. 8 shows the junction node voltages v(x) and individual 4 shows waveforms of gate drive voltages. It differs from the first scheme of FIG. 6 in the control of the slave transistors, here the slave transistors are also turned on and off periodically.

The master transistor (which is QH1 and QL1 during the positive phase) is turned on after a dead time Td longer than such transition time (longer by ΔTd). However, the slave device must be turned on at the end of the transition at the latest. Because then the diode mode of the slave device should be terminated and the slave device should be conducting in order to facilitate the diode mode of the master transistor.

Such precise timing is impractical for slave devices, which means that slave devices need to be switched sooner. Instead, the slave devices are switched as early as Td, i.e. when the respective master device of each pair is switched (i.e. QH0 and QL0 operate in a complementary manner to QL1 and QH1). is done). This approach only requires generating two timing signals for each half cycle.

FIG. 9 shows the control sequence for the operation of the four transistors. The same section as in FIG. 6 is confirmed.

The off mode of each bidirectional switch is also used here since the slave transistors are also switched, in which the respective first and second transistors are both turned off.

In positive phase, the control sequence for each bidirectional switch includes an on mode, an off mode, and a first transition mode (upper transistor, e.g., QH1, is off and lower transistor, e.g., GH0, is on). use.

In reverse phase, the control sequence for each bidirectional switch includes an on mode, an off mode, and a second transition mode (upper transistor, e.g., QH1, is on and lower transistor, e.g., GH0, is off). use.

This drive scheme allows gate drive by a pair of transformers, which can be beneficial at high switching frequencies. Gate drive transformers can replace frequency limited level shifting type gate drivers. A resonant gate drive transformer for a half bridge recovers energy from discharging the gate of one (eg, lower) device to charge the gate of the other (eg, upper) device. However, adjustment of the dead time is cumbersome because charging and discharging cannot be disentangled.

FIG. 10 shows how the gate drive scheme shown in FIGS. 8 and 9 allows employing pairs of gate drive transformers. In particular, the scheme of FIG. 9 makes it possible to provide two pairs of gates, one of which is switched on and the other is switched off simultaneously, which is , suitable for the resonant gate driver transformer approach.

A gate driver must handle both signal transmission and sourcing or sinking of the gate charge to turn on or off the channel of the transistor. For standard level shifters both become difficult at frequencies in the MHz range due to the large (parasitic) capacitances induced. This is also true for bootstrapping techniques used to supply gate drive power. For floating (high-side) transistors, non-galvanic signal transmission (eg optical transmission, signal transformers or RF links) is used.

In connection with gate driving, transformers are used not only to transfer signals, but also as part of the floating gate driver power supply. A transformer can be used for both of these functions at the same time.

For the floating gate driver power supply, a resonant gate driver with two complementary outputs for driving the low-side and high-side transistors of the half-bridge is described. A resonant gate drive transformer for a half bridge recovers energy from discharging the gate of one (eg, lower) device to charge the gate of the other (eg, upper) device. However, adjustment of the dead time is cumbersome because charging and discharging cannot be disentangled.

For high frequency operation, implementing the above timing pattern of FIG. It may imply a relatively complex gate driver configuration using one of the known principles listed above, employing two eg discrete floating gate drive circuits.

Regarding the second driving scheme for the bidirectional half-bridge of FIG. 6, two pairs of gates are simultaneously switched such that one of them is turned on and the other is turned off. Gate pairs can be constructed.

FIG. 10 schematically shows such a gate driver for common drain configuration. At the same time, two gate driver pairs (A and B ). The delay between the first and second pair of switching events is the dead time (Td) of the half-bridge inverter, ie the time during which both (bidirectional) switches are off.

Each assembly consists of a transformer used for power and signal transmission. One gate driver has a primary winding LpA and secondary windings LL0 and LH1. The other gate driver has a primary winding LpB and secondary windings LH0 and LL1. The primary side of the transformer is fed by a central drive circuit that generates the gate drive pattern from set points and feedback information (“FB”), which can be fed from the mains (l, n). . Floating secondary sides are connected to the gates and their respective sources via gate drive pulse conditioning circuits gH0, gL1, gH1 and gL0.

In the common-drain configuration shown, both sources of the first gate drive pair (A) have the same potential and no unwanted oscillation between the outputs due to parasitic capacitance is excited. A similar situation is given for the second assembly (B), since the voltage difference between the two sources is the supply voltage, which contains only a small high-frequency ripple due to the filtering capacitance C_filt2.

Since the gate drive pulses on the two outputs of each gate drive circuit are complementary and no specific delay needs to be arranged between them, the gate discharge energy of one output is required to charge the other. can be used, so that only a small fraction of the required drive energy has to be supplied from the central supply circuit.

The use of inverter topologies is of particular interest for implementing zero voltage switching (ZVS) converters. ZVS is a soft switching technique, meaning virtually lossless switching. To this end, resonant converters can be used to enable high switching frequencies and thus miniaturization of certain passive power components. ZVS means that the transistor is turned on only when the voltage across the drain-source terminals of the transistor is (substantially) zero. This is because it prevents the occurrence of a short circuit of the charged capacitor, ie the output capacitance of the device. This is called hard switching. Therefore, the capacitor must be discharged by the current supplied by the power conversion circuit.

For example, for interval 0, where the junction node is increased from zero to the live voltage, first the low-side switch BD2 is turned off (by turning off QL1). The current that was flowing into the junction node continues to flow, but now flows into both the low and high side branches, thereby charging the output capacitance of QL1 (QL0 is still on), while at the same time Discharge the output capacitance of QH1.

Both the current and the output capacitance of the device determine not only whether the final voltage level (here the live voltage) is achieved, but also the duration and shape of the junction node voltage transition interval. When this voltage is reached, the high-side master switch QH1 can be softly turned on because the voltage across its output capacitance is zero.

Device QH1 need not be turned on exactly at that time. If device QH1 is kept off for some length of time, this current will reverse bias QH1 and put it into diode mode, assuming that current is still flowing into the junction node. This gives some headroom for control of the gate drive signals. This is required if there is adaptive deadtime control. Dead time is the time during which both the lower master switch and the upper master switch are in the off state so that soft charging/discharging of the output capacitance of the device can occur. This time may be fixed or adaptive, and in any case must be long enough to guarantee a complete transition under all operating conditions.

During mains overvoltage events (surges), all four transistors are switched off so that the half-bridge with two bidirectional switches can withstand twice the maximum reverse drain-source blocking voltage. can be done.

An inverter may utilize two half-bridges with resonant tank elements (transformers, resonant capacitors) connected between two junction nodes.

Note that for the common-drain configuration, the roles of the transistor pairs are exchanged. Thus, the common source circuit example above can be routinely converted to a common drain configuration by those skilled in the art.

FIG. 1 shows the front end of a power factor correction circuit with a resonant LLC converter and an inverter. A non-resonant PFC circuit may have the same configuration, but in that case the capacitor does not form part of the resonant circuit. Said capacitor instead comprises a DC blocking capacitor. A relatively large capacitance is used for the DC blocking capacitor, resulting in a small voltage drop, whereas the resonant capacitor operates somewhat close to the resonant frequency formed with one of the inductors. Because of its size, it experiences a large voltage drop. The same circuit can also form a resonant converter circuit (without power factor correction) since the power factor correction function is performed by the control of the converter rather than the power circuit.

Those skilled in the art can understand and effect variations to the disclosed embodiments from a study of the drawings, the specification and the appended claims in the practice of the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and singular forms do not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Where the term "adapted to" is used in a claim or specification, the term "adapted to" is replaced with the term "configured to". Note that they are intended to be equivalent. Any reference signs in the claims should not be construed as limiting the scope.

Claims (14)

an input for receiving an unrectified AC input signal, said unrectified AC input signal comprising a positive polarity and a negative polarity;
a first terminal and a second terminal for receiving power from the input;
a first bidirectional switch between the first terminal and a junction node, the first bidirectional switch including a first transistor and a second transistor coupled in anti-series;
a second bidirectional switch between the second terminal and the junction node, the second bidirectional switch including a third transistor and a fourth transistor coupled in anti-series;
a primary inductor between the junction node and a second node;
A bridgeless inverter circuit having a capacitor configuration between the second node and the first terminal and/or the second terminal,
During said positive polarity,
the first switch and the third switch are configured to receive a master signal, the second switch and the fourth switch are configured to receive a slave signal;
During said negative polarity,
the first switch and the third switch are configured to receive the slave signal, the second switch and the fourth switch are configured to receive the master signal;
The master signal is configured to determine whether the first bidirectional switch or the second bidirectional switch is in a blocking state or a conducting state, and the slave signal is left on at all times. A bridgeless inverter circuit configured as follows. 2. The circuit of claim 1, wherein each pair of first and second transistors in series has a common source or common drain at a junction node between said first transistor and said second transistor. 3. A circuit according to claim 1 or 2, further comprising a control circuit for controlling switching of said transistor. wherein the control circuit, for each bidirectional switch,
an on mode in which the respective first and second transistors are turned on;
a first transition mode in which the first transistor is turned on and the second transistor is turned off;
3. The circuit of claim 2, adapted to implement a second transition mode in which said second transistor is turned on and said first transistor is turned off. the controller
a control sequence for each bidirectional switch utilizing the on mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal;
A control sequence for each bidirectional switch is adapted to implement a control sequence that utilizes the on mode and the second transition mode when the voltage at the first terminal is lower than the voltage at the second terminal. 5. The circuit of claim 4. The control circuit further comprises, for each bidirectional switch:
5. The circuit of claim 4, adapted to implement an off mode in which each said first transistor and said second transistor are turned off. the controller
a control sequence for each bidirectional switch utilizing the on mode, the off mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal;
When the voltage at the first terminal is lower than the voltage at the second terminal, a control sequence for each bidirectional switch implements a control sequence utilizing the on mode, the off mode and the second transition mode. 7. The circuit of claim 6, adapted for: 8. A circuit according to any preceding claim, wherein each bidirectional switch comprises a GaN dual transistor switch. A power factor correction circuit comprising an inverter circuit as claimed in any one of claims 1 to 8 and an output circuit including a secondary inductor coupled to the primary inductor. A bridgeless resonant converter comprising an inverter circuit according to any one of claims 1 to 8 and an output circuit including a secondary inductor coupled to the primary inductor. A method for providing electrical reversal,
receiving at first and second terminals an unrectified AC input signal comprising positive and negative polarities;
controlling switching of a first bidirectional switch between the first terminal and a junction node and a second bidirectional switch between the second terminal and the junction node, wherein the primary a side inductor is between the junction node and a second node, a capacitor arrangement is between the second node and the first terminal and/or the second terminal, and the first bidirectional switch is , a first transistor and a second transistor coupled in anti-series, said second bidirectional switch comprising a third transistor and a fourth transistor coupled in anti-series;
During said positive polarity,
the first switch and the third switch are configured to receive a master signal, the second switch and the fourth switch are configured to receive a slave signal;
During said negative polarity,
the first switch and the third switch are configured to receive the slave signal, the second switch and the fourth switch are configured to receive the master signal;
The master signal is configured to determine whether the first bidirectional switch or the second bidirectional switch is in a blocking state or a conducting state, and the slave signal is left on at all times. How to configure a control sequence for each bidirectional switch utilizing the on mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal;
wherein a control sequence for each bidirectional switch implements a control sequence that utilizes the on mode and the second transition mode when the voltage at the first terminal is lower than the voltage at the second terminal. Item 12. The method according to Item 11. 12. The method of claim 11, comprising for each bidirectional switch implementing an off mode in which the respective first and second transistors are turned off. a control sequence for each bidirectional switch utilizing the on mode, the off mode and the first transition mode when the voltage at the first terminal is higher than the voltage at the second terminal;
When the voltage at the first terminal is lower than the voltage at the second terminal, a control sequence for each bidirectional switch implements a control sequence utilizing the on mode, the off mode and the second transition mode. 14. The method of claim 13, comprising steps.

Images