JP2022056844A - Power module - Google Patents

Abstract

To improve the heat transfer characteristics of a power module that enables a power conversion device with a power density of 150 kW/L, to reduce the power module losses by improving the switching speed, and to reduce the size of a cooler volume.SOLUTION: The module incorporates a self-inductance reduction design that cancels out magnetic fields resulting from current, prevents a value of potential of a gate drive signal from changing to an unexpected value due to inductance, by making a mutual inductance between current loops close to zero in principle by making current loop planes orthogonal to each other present in an inverter or converter, so as to enable high-speed switching. In addition, a module design with good heat transfer characteristics is employed. Thereby, it becomes possible to reduce losses and miniaturize a cooler and passive components.SELECTED DRAWING: None

Description

In the present invention, the terminals in a circuit configured by using a power switch element having a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) structure are exposed to the outside and combined into one package for power. A power module, which is a power semiconductor device equipped with a surface for efficiently transferring heat generated from an element, a gate signal terminal for operating a power switch element, and a gate signal reference potential terminal, and a power module for operating the power module. The present invention relates to a power conversion device composed of a driver circuit, a cooler for cooling a power module, a capacitor for suppressing fluctuations in an input voltage, and the like.

A circuit configuration in which one arm in which a power switch element and a diode are connected in parallel are connected in series and the desired power is taken out from the connection point of each arm is called a half bridge, and a power module equipped with two arms in this way. Is called a 2 in 1 module. Similarly, a circuit configuration having two half bridges and utilizing alternating current appearing between the connection points of the respective arms is called a full bridge. In particular, an inverter device equipped with three half bridges and capable of taking out three-phase alternating current is called a three-phase inverter, and since it includes a total of six arms, it is called a 6-in-one module.

The power density of the power conversion device using such a module has been continuously improved with reference to the graph fitted with the empirical rule of power density development of the power conversion device described in Non-Patent Document 1. Non-Patent Document 1 only describes up to 2020, but if this log-log graph is extended to 2025, it will be a power conversion device of about 60 kW / L in 2020 and about 150 kW / L in 2025. Is expected to be commercialized.

In order to realize such a high output density power conversion device that has been expected for some time, it is necessary to improve the heat transfer characteristics from the power switch element to the outer surface of the module and to reduce the loss of the power switch element. It is said that.

In recent years, as the power module has become smaller and the chip area has been reduced, the heat transfer area becomes narrower, and the heat transfer characteristics of the heat transferred from the elements inside the power module to the heat dissipation equipment deteriorate. Many products that allow this are also sold.

Further, while it is desired to reduce the loss of the power switch element, there is a limit to the improvement of the switching speed, so that the reduction of the loss is also limited, and the miniaturization of the cooler is limited. Further, since there is a limit to the improvement of the switching speed, the operating frequency cannot be improved, and there is a problem that the passive component that requires a value inversely proportional to the operating frequency cannot be miniaturized. In particular, the volume of passive elements occupies a large proportion of the volume of modern power converters. Therefore, the difficulty in miniaturizing the passive element is a major obstacle to the miniaturization of the entire power conversion device and the improvement of the power density.

That is, the factors that hinder the improvement of the switching speed are obstacles to the miniaturization and high output density of the power conversion device.

Here, the difference in switching speed due to the device structure and the device loss will be briefly touched upon. Conventionally, in the power range where the withstand voltage is 1 kV or more and the current flow current is about 100 A or more, both positive and negative carriers can be used for the MOSFET that uses only a single carrier, so that the withstand voltage can be obtained. Even as an element structure with an increased element thickness, an IGBT having a relatively good VI characteristic when turned on has been used. However, since a part of the carriers passing through when the switch is turned off cannot be completely eliminated in this IGBT structure, there is a structural problem called tail current in which the current cannot be cut off immediately.

That is, in the conventional power range where the withstand voltage is 1 kV or more and the current flow current is about 100 A or more, the switching speed is limited due to the cause derived from the element structure. Therefore, in Si-IGBTs using Si (Silicon) semiconductor materials, the trade-off relationship between the VI characteristics per element area and the switching speed can be manipulated by adjusting the concentration of the dopant that becomes the carrier. We have been trying to improve the switching speed. However, it has been difficult to reduce both the conduction loss and the switching loss per unit area in the IGBT by this method. Also, improving the switching speed is difficult in principle compared to unipolar devices.

In recent years, by using a SiC (Silicon Carbide) material instead of a Si material, it is possible to reduce the element thickness while obtaining a sufficient withstand voltage even with a MOSFET structure, so it is turned on even when handling a voltage of several kV or more. Since it is a unipolar device that can reduce resistance and does not cause the problem of tail current, SiC- MOSFETs that can be switched at high speed have been put into practical use and are becoming widespread mainly in trains and the like. If it is a SiC- MOSFET, both low conduction loss and low switching loss can be achieved at the same time.

By improving the performance of the power switch element as described above, in recent years, even when a voltage of 1 kV is applied and a current of 100 A is switched, high-speed switching of several tens of ns is possible on the power switch element chip. It has become.

However, the parasitic inductance generated in the wiring between the gate driver circuit connected to the package or power module that houses the power switch element chip and the gate part of the power switch element chip, and the main current that the power switch element turns on and off. Due to the mutual inductance coupling between the loop and the gate signal current loop, a problem that high-speed switching of several tens of ns units becomes difficult has become apparent.

That is, in modern times, the switching speed of the power switch element is not limited by the element structure, but the parasitic inductance and mutual inductance outside the element chip limit the improvement of the switching speed of the power switch element, which becomes a bottleneck. ing.

Originally, it should not be necessary to supply a large amount of current to the gates of MOSFETs and IGBTs, which are voltage-manipulating devices, but MOSFETs and IGBTs contain junctions of dissimilar materials, resulting in a non-negligible parasitic capacitance. , Self-inductance and mutual inductance become obstacles when passing a current for charging and discharging the capacitance.

In order to instantly operate the gate voltage that determines the on / off of the switch element of the MOSFET or IGBT structure to the desired value, supply sufficient drive current to charge and discharge the above-mentioned parasitic capacitance or apply current. It is necessary to pull out from the gate part at a sufficient speed. Unless the charge charged to the parasitic capacitance is sufficiently transferred, the potential difference between both ends of the parasitic capacitance at the gate portion does not reach the desired value. In other words, the gate-source voltage for MOSFETs and the gate-emitter voltage for IGBTs are designed gate-on voltages such as 15 V and 18 V, and 0 V and -2 V, unless the gate driver current is sufficient. Cannot change to the designed gate-off voltage within the specified time.

The principle of the phenomenon that high-speed switching becomes difficult due to parasitic inductance and mutual inductance, and the conventional technology used to deal with this are described below. Furthermore, it is stated that it is difficult to improve the output density of the power conversion device by the design using this conventional technique.

When the gate driver circuit inputs the on / off signal of the power switch element, the parasitic inductance existing in the path from the gate driver circuit to the gate pad of the MOSFET or IGBT passes through to charge the gate parasitic capacitance. Prevents the rise of.

However, since the gate current rises at a high speed while being hindered by the parasitic inductance, an abnormal voltage is generated in the gate voltage by the product of the time derivative value of the current and the parasitic inductance.

Furthermore, due to the mutual inductance coupling that occurs between the gate signal current loop and the main current loop, the on / off current change of the main current flowing through the power switch, for example, the product of the current differential value of a value such as several hundred A and the mutual inductance. Is fed back to the gate signal, so that the input gate signal is disturbed. This disturbed gate voltage causes a vicious cycle of disturbing the operating characteristics of the power switch element.

The mutual inductance is proportional to the Cos of the current loop surface-to-plane angle, that is, the gate driver circuit is parallel to the upper surface of the circuit pattern in which the power switch element is mounted, even though its influence changes from 0 to 1 times depending on the angle. There are many power converters to prepare for. It can be said that these are power conversion devices having a design in which the influence of the change in the main current flowing through the power switch on the gate driver is in principle maximized with respect to the loop surface angle.

Abnormal voltage caused by parasitic inductance and mutual inductance between current loops, and the phenomenon that abnormal voltage is fed back by the interaction between the gate signal and the main current, such as these, are actually gate voltage and MOSFET drain. Observed as overshoot or ringing of source-to-source voltage and IGBT-collector-emitter voltage. Such a phenomenon causes the power switch element and the gate driver circuit to be destroyed.

In order to reduce the adverse effect on switching due to parasitic inductance and mutual inductance, generally, a resistor is given to the gate portion to reduce the amount of current flowing through the gate pin, and the switching speed is intentionally lowered. As a result, overshoot, undershoot, and ringing of the gate signal caused by the parasitic inductance of the gate signal pin, source signal pin, and emitter signal pin are reduced, and the current flows between the drain source of the MOSFET and the collector-emitter of the IGBT. The anomalous gate voltage propagated by mutual inductance is also reduced by increasing the time to raise and lower the current.

However, if such a design is intentionally made to reduce the switching speed, the switching loss of the element increases due to the slow switching speed, and the increase in the loss increases the increase in the element temperature. Therefore, the cooler Will need to be increased in size. At this time, if the thermal resistance between the power switch element and the cooler is large, the element cannot be sufficiently cooled even if the cooler is at a low temperature, so that the element loss allowed in the power switch element is further reduced. .. As described above, in the case of a heat transfer characteristic or a cooler that cannot sufficiently cool the element, there is an upper limit on the operating frequency that determines the repetitive switching loss per unit time. In addition, the passive element that requires a value inversely proportional to the operating frequency cannot be miniaturized. In addition, in this case, a design method of improving heat transfer characteristics by expanding the element area and module heat dissipation area is required, which leads to an increase in element cost and module area, and further miniaturization of the power conversion device. Make it difficult.

Due to such a relationship, the heat transfer characteristics and parasitic inductance of the power module, the mutual inductance coupling between current loops, and the conventional technique for dealing with these problems are obstacles in improving the output density of the power converter.

Among the background techniques and problems in the above-mentioned power conversion device, the patent documents related to the improvement of the characteristics of the current loop are introduced below.

Patent Document 1 describes the angle of wire bonding connected from one surface of the power switch element to the wiring pattern, and includes an intention of designing a current flow loop.

In Patent Document 2, the electrode structure inside the power module is devised to reduce the radiation of the magnetic flux by reducing the main current loop area, and both positive and negative generated by facing the main current loop directions at the positive and negative electrodes. It extends from the main terminal by reducing the effective parasitic inductance by offsetting the resulting magnetic field and by defining the gate emitter pin loop surface and preventing coupling between the gate pin current loop surface and other current loop surfaces. Attempts to suppress the effects of control terminal noise are described.

In Patent Document 3, a conductor pattern and a switch element are mounted on the insulation so that the main current passing through the switch element passes through the conduction pattern provided on the back side of the insulation when viewed from the switch element. The configured power module is described, and since the current loop of this module has the thickness of one piece of insulation, it is expected that the magnetic flux generated from the main current loop surface is reduced.

All of the cited patent documents include design intent and claims that make the circuit pattern of the current loop more convenient. However, even if the techniques shown in these patent documents are used, the fluctuation of the main current generated when the power switch element in the power converter is switched at high speed propagates to the gate signal pin and the gate driver circuit in the power module. However, it is not possible to achieve both a design that sufficiently suppresses the phenomenon of disturbing the gate signal and a design that can sufficiently transfer the heat generated by the power switch element to the outside.

In Patent Document 1, one of the power switch elements is arranged on the first wiring pattern, and the other of the arranged power switches is connected to the other second wiring pattern by wire bonding, and the angle of the wire is set. It is described that it is substantially orthogonal to the second wiring pattern. As described above, Patent Document 1 includes an intention of designing a main current loop, and also includes a design example in which a gate external terminal and a gate reference potential external terminal are adjacent to each other. That is, a configuration is shown in which the gate pin loop surface and the main current loop surface are orthogonal to each other by reducing the gate pin loop area and making the gate pin perpendicular to the main current loop surface. However, in the invention described in Patent Document 1, no consideration is given to the mutual inductance coupling between the gate driver circuit and the main current loop surface.

Patent Document 2 defines a gate-emitter pin loop surface and describes an attempt to prevent noise from propagating from the current loop surface to the gate pin current loop surface. One of the gate-emitter pin loop surfaces described in the literature is parallel to the main current surface on which the power switch element is mounted, but the generated magnetic flux and the magnetic flux generated from the AC output terminal cancel each other out to form a gate. It is intended to reduce the noise derived from the inductance generated between the pin and the emitter pin. However, when the gate driver circuit is provided at the position described in Patent Document 2, the current loop surface of the gate driver circuit and the main current loop surface of the power switch element mounting surface described above are parallel to each other, resulting in mutual inductance coupling. As a result, potential fluctuations on the gate driver circuit may occur.

In the power module described in Patent Document 3, since the current loop passing through the power switch element has the thickness of one insulator, the magnetic flux generated from the main current loop surface is reduced, and the currents face each other on both sides. Effective reduction of parasitic inductance is expected by passing in the direction. Since this main current loop surface is formed in the side surface direction of the insulating plate, even if the gate driver circuit is provided parallel to the power module plate surface direction described in Patent Document 3, the gate driver circuit current Since the loop surface and the main current loop surface are orthogonal to each other, there is little possibility that the gate signal or the operation of the power switch element will be disturbed due to the mutual inductance coupling between the two current loop surfaces. However, since the power module described in Patent Document 3 needs to have a conduction pattern on both sides of the insulating substrate, the heat transfer characteristic from the power switch element to the external cooler is inferior to the design that does not require this. ..

Although not cited in the literature, the calculated values of the gate driver voltage that fluctuates due to mutual inductance when a gate driver circuit is provided on a general box-type 2 in 1 power module are described. The current loop area S ₁ flowing through the power module is 4.00 × 10 ^-3 m ² , the current flowing through this current loop surface is 200 A, and the loop area S ₂ on the output side after insulation of the gate driver circuit is 1. .44 × 10 ^-4 m ² , the distance d between the loop centers is 3.40 × 10 − ² m ² , and the mutual inductance is 1 when the current change time when cutting off the current flowing through S ₁ is 40 ns. It becomes .47 nH, and the voltage generated _on the loop area S1 by the mutual inductance coupling reaches 7.33 V. Normally, the gate voltage of Si-PWM and Si-IGBT is designed to be 15 V, and the gate voltage of SiC- MOSFET is designed to be about 18 V. The gate withstand voltage of each element is about 20 to 25 V at the upper limit and -5 V at the lower limit. Overshoots and undershoots exceeding 7 V cause destruction of the gates of MOSFETs and IGBTs.

Therefore, as described above, it is necessary to design to reduce the intentional switching speed. For example, in the case of the pattern layout of this power module and the gate driver circuit, the voltage generated in the gate current loop _S2 can be reduced to about 0.98 V by reducing the switching speed from about 40 ns to about 300 ns. ..

However, as described above, when the switching speed is reduced, the switching loss, which is a loss that occurs during the time when the current and the voltage are applied at the same time, increases, and the cooler required to cool this loss increases in size. .. In addition, when the operating frequency is increased, the switching loss per unit time increases more than that of equipment capable of high-speed switching, so it is not possible to increase the operating frequency, which is the repetition frequency of switching loss, and the passive element is made smaller. It becomes difficult to change.

As introduced so far, the power switch element cannot be switched at a sufficient speed by the means described in the background technology. Although the switching speed of a single power switch element is in the unit of several tens of ns, the parasitic inductance of the power module and gate driver circuit and the mutual inductance between each current loop are the bottlenecks of the switching speed of the power switch element. It has become.

JP-A-2002-153079 JP 2016-119430 International Publication No. WO 2019/221242

Hiromichi Ohashi "Trends in the latest power devices" Journal of the Institute of Electrical Engineers of Japan, (2002)

Improvement of the output density of the power conversion device according to the rule of thumb for the development of the power conversion device described in Non-Patent Document 1 has been expected for some time. In order to achieve this, we would like to improve the heat transfer characteristics of the power module and improve the switching speed to reduce the loss of the power module and reduce the volume of the cooler. Furthermore, by making it possible to improve the operating frequency by reducing the loss, we also want to reduce the size of passive elements that require a value that is inversely proportional to the operating frequency. In particular, since the passive element occupies a relatively large proportion of the total volume of the power conversion device with respect to other parts, the miniaturization of the passive element effectively affects the volume reduction of the entire power conversion device. .. In order to improve the switching speed, it is required to reduce the adverse effect of these inductances on switching by reducing the parasitic inductance and the mutual inductance. These problems of heat transfer characteristics and switching characteristics derived from inductance are problems to be solved by the present invention.

The DC positive electrode bus plate on which the power switch element in the power module is mounted and the DC negative electrode bus plate are arranged in parallel without overlapping, and a phase output bus plate that connects the power switch elements mounted on each bus plate is provided. , The DC positive electrode bus plate and the DC negative electrode bus plate are provided on a different plane from the plane. As a power module, the insulating surface provided in the path for transferring heat from the bus plate to the cooler is not provided with any foreign matter on the surface opposite to the bus plate surface. Further, a gate signal pin is provided in a direction orthogonal to the direction of the direct current flowing through the DC positive bus plate and the DC negative negative bus plate, and a gate signal reference potential pin is provided at a position parallel to the gate signal pin, and the gate signal pin and the gate are provided. The distance between the signal reference potential pins should be closer than the distance that can be isolated. On top of that, the main current loop plane including the DC positive electrode bus plate plane and the DC negative electrode bus plate plane, the gate signal current loop plane, and the gate driver circuit current loop plane are orthogonal or 90 ± 10 deg. The internal configuration of the power module equipped with the gate driver circuit and the gate driver circuit within the range of, and the mounting arrangement of each.

Since the heat of the power switch element mounted in the power module can be transferred to the outside from both sides of the power switch element, the heat dissipation is higher than that of the one that dissipates heat from one side. In addition, since the back surface of the insulating surface is not provided with a conduction pattern, fixing brackets, or other insulating materials, the thermal resistance is smaller than that provided with these. Further, since the gate signal pin and the gate signal reference potential pin are close to each other and are in opposite directions, the magnetic fields generated by the currents flowing through both of them cancel each other out, and the parasitic inductance of the pin is reduced. Also, the gate signal pin current loop area is reduced. Further, since the main current loop surface, the gate signal pin current loop surface, and the gate driver circuit current loop surface are orthogonal to each other, the mutual inductance between the respective loop surfaces becomes almost zero. The angle θ between each surface is 90 deg. Not θ = 90 ± 10 deg. If it is within the range of, this mutual inductance value is proportional to Cos θ. Due to these effects of self-inductance and mutual inductance reduction, it is not necessary to reduce the current value of the gate drive signal and design to reduce the switching speed, and high-speed switching of the power switch element is realized. Since the power switch element can be stably switched within a time of about 10 to 40 ns, the frequency can be sufficiently repeatedly increased even in a power conversion device that handles a large amount of power of about 80 kW to 150 kW. For example, this repetition frequency exceeds 100 kHz. Since the passive element can be miniaturized by such high-frequency operation and the cooler can be miniaturized by reducing the loss by high-speed switching, the output density of the power conversion circuit having an input voltage of 600 V or more is significantly improved. can.

6 in 1 module diagram 6 in 1 module circuit schematic diagram Schematic showing a modified example of a simplified 6-in-1 module 6 in 1 module mounting diagram a 6 in 1 module mounting diagram b 6 in 1 module mounting front view Example of three-phase inverter system Exploded view of 3-phase inverter system Circuit schematic diagram of three-phase inverter Orthogonal diagram of current loop in a three-phase inverter

The present invention is characterized in that the main current loop surface in the power module, the gate signal pin current loop surface, and the output section current loop surface of the gate driver circuit are orthogonal to each other.

Power switch elements and power diode elements are mounted on the DC positive bus plate and DC negative negative bus plate in the power module, and the area of these elements and the number of parallel mounts are not limited, but the total of the power switch elements and power diode elements. The closer the area is to the required bottom area of the power module, the more suitable it is, and the rigidity and heat transfer characteristics of the entire power module, as well as the handling power and heat transfer efficiency per module volume are increased.

The power switch element mounted on the DC positive bus plate in the power module may have an IGBT structure, a MOSFET structure, a D MOSFET (Double Diffused MOSFET), or an IE-IGBT (Injection Enhanced-IGBT). , SJ-PWM (Super Junction MOSFET), UPWM (U-happed training gate MOSFET), SJ-UPWM and other structures may be used. Further, the material used for the power switch element may be Si or SiC.

It is more preferable that the gate terminal pad formed on the outer surface of the power switch element is formed not at the center of the power switch element but at the outer edge of the element. A power diode element having a function as an FWD (Free Wheeling Diode) provided in antiparallel to a power switch element may have a PIN (structure in which a P-type semiconductor, an I-type semiconductor, and an N-type semiconductor are overlapped) and a diode structure. It may be good, or it may have an SBD (Shotky Barrier Diode) structure, but a diode that can be switched at high speed is more preferable in view of the problems and means solved by the present invention.

The number of phase output bus plates connecting the power switch elements is provided for the number of phases of the power module. The current flowing through the DC positive electrode bus plate and the DC negative electrode bus plate and the current flowing through the phase output bus plate are combined to form a main current loop surface.

At this time, the current flowing through the power switch element or the power diode element and the current flowing through the phase output bus plate are combined to form a U-shaped current loop surface in the thickness direction of the power module. Although the area of this loop plane is very small, it is desirable that this loop plane is also orthogonal to the above-mentioned three loop planes.

The input / output terminals of the phase output bus plate are arranged in the direction orthogonal to the DC positive electrode bus plate flow direction of the power module, and the current direction flowing to the phase current measuring device connected to this is the gate driver circuit output unit. It is desirable that the direction is orthogonal to the current loop plane through which the current flows.

The phase input / output terminal, the DC input / output terminal, the gate signal pin, and the gate signal reference potential pin may have a shape distorted from a point protruding from the DC positive electrode bus plate, the DC negative electrode bus plate, and the phase output bus plate, respectively. It is desirable that the above-mentioned four types of pins ensure an appropriate insulation distance and a distance between the pin tips so that the female terminals that receive the pins can be appropriately laid out.

Further, since the entire power module generates heat due to the loss of the power switch element and the bus, it is expected that each bus plate and four types of pins will expand and expand. It is desirable that the four types of pins have a slope that can mitigate the effects of such expansion and extension. Further, a design in which the above four types of pins are connected by a female terminal having a spatial margin so as not to hinder the expansion and extension of the pins is more suitable for a high output density power conversion device.

It is more preferable that the insulating material inserted to electrically insulate between the pins provided at the positions where the gate signal pin and the gate signal reference potential pin are close to each other and to provide rigidity against stress is a low dielectric material. .. In light of the gist of the present invention, it is desirable that the parasitic capacitance generated between the gate signal pin and the gate signal reference potential pin is smaller. The parasitic capacitance of the gate signal pin causes a decrease in the rising and falling speed of the gate signal.

The connection between the gate signal pin and the power switch element may be wire bonding, a metal film having room for deformation, or a gate signal pin having sufficient rigidity may be directly soldered. These connection methods may be similarly applied to the upper and lower arms and any of the switches arranged in a plurality of phases.

When wire bonding or a metal film is used, when the distance between the gate signal pin to be connected and the power switch element fluctuates due to deformation of the DC positive electrode bus plate, DC negative electrode bus plate, and phase output bus plate due to heat. The amount of fluctuation can be absorbed by the deformation of the wire or film.

When soldering a metal gate signal pin directly to the gate terminal of a power switch element, each part is to be reduced from the possibility of damage to each part due to the difference in the coefficient of thermal expansion of the metal plate, each bus plate, and the power semiconductor element. Instead of a structure in which a resin with a coefficient of thermal expansion close to that of the part is filled and the gate signal pin soldered directly to the power switch element is supported only by the power switch element, the heat transfer part and gate provided in the direction of the power module surface are provided. Fix the gate signal pin so that it is sandwiched between the support column structure that supports the signal pin.

It is more preferable that the cooler has a strength against deformation of the power module due to the influence of expansion and extension of the DC positive electrode bus plate, the DC negative electrode bus plate, and the phase output bus plate. Further, it is desirable to design the cooler to apply a uniform stress in the direction of the power module surface. At this time, by designing considering how the parts inside the power module, especially each bus plate and each input / output pin, are deformed in the length direction due to the pressure applied to the power module by the cooler. It is possible to configure a power module and a gate driver circuit that are less likely to be destroyed by loss, heat generation, and deformation.

The gate driver circuit board arranged on the surface orthogonal to the main current loop surface of the power module and the gate signal pin current loop surface is the path from the part connected to the gate signal pin and the gate signal reference potential pin to the gate driver IC output pin. It is more preferable that the pattern design is short and the distance between the patterns connected to both pins is narrow.

In addition, the gate driver circuit has a configuration in which the insulation part of the gate driver IC and the insulation part of the power supply for the gate driver IC output side overlap on the same straight line, or the gate driver IC and the gate driver IC output are divided into both sides of the gate driver circuit board. A side power supply is arranged, and the insulation portion between the IC and the power supply is overlapped on a straight line having both sides of the board.

The length in the thickness direction of the cooler of the gate drive circuit board is referred to as the longitudinal direction of the gate driver circuit board. When designing the dimensions of the gate driver circuit board and the dimensions of the cooler so that the end points in the longitudinal direction of the gate driver circuit board facing the gate signal pin are closer to the power module side than the end points in the thickness direction of the cooler. Since the protrusion of the entire power converter system is reduced, the design is more efficient in terms of volume, which is advantageous for miniaturization of the power converter system.

The inside of the power module is filled with a resin material having a thermal expansion coefficient similar to that of the DC positive electrode bus plate, the DC negative electrode bus plate, and the phase output bus plate. As a result, when the power module generates heat and expands, there is a difference in the amount of expansion of the contact surface due to the difference in the coefficient of thermal expansion, and the difference in the amount of deformation of the joint surface reduces the possibility that each part inside the power module will break. do.

When mounting the DC positive electrode bus plate and the DC negative electrode bus plate on the insulating material, metal brazing may be used, or soldering with a thermal expansion coefficient close to that of the insulating material or the bath plate may be performed. good. In addition, a heat conductive material having a high creep property may be used. This also applies to the joint portion between the phase output terminal on the other side of the power switch element or the power diode element and the insulating material.

At this time, by using an insulating material having a thermal expansion coefficient similar to that of the bath plate or the resin filling material, it is possible to reduce the possibility that the power module is destroyed at the time of heat generation and low temperature. In recent years, research has been progressing on using a Si _{3N 4 material} having a thermal expansion coefficient close to that of Si, which is a semiconductor material, as an insulating material. The possibility of material destruction can be reduced.

When filling the inside of the power module with a resin material, pressure is applied inward between the outermost surfaces while maintaining a certain degree of accuracy so that the two insulating materials corresponding to the outermost surfaces are parallel to each other. At this time, the temperature of each component of the power module during manufacturing is preheated to a certain temperature, and the temperature of the entire power module is cooled to the storage temperature after filling with the resin.

(Example 1)
FIG. 1 shows a diagram in which the single-sided insulating surface of the 6-in-1 module in the first and second embodiments is stripped. In the 6-in-1 module, the DC positive electrode terminal 111 and the DC positive electrode bus plate 110, the DC negative electrode terminal 121 and the DC negative electrode bus plate 120, and the DC side insulating plate 102 are placed on the DC side insulating plate via solder, a heat conductive material, or a brazing material. Is implemented. It is even more preferable that the solder for mounting is made by adding a material of the same quality as the DC positive electrode bath plate 110 and the DC negative electrode bath plate 120.

A phase output terminal is provided in a direction orthogonal to the DC positive electrode terminal 111 and the DC negative electrode terminal 121, and the U phase output terminal 131, the V phase output terminal 141, and the W phase output terminal 151, respectively. A capacitor is provided between the DC positive electrode bus plate 110 and the DC negative electrode bus plate 120 via the P-type terminal shown in 161c in FIG. The U phase is provided with capacitors 161a and 161b, the V phase is provided with capacitors 171a and 171b, and the W phase is provided with capacitors 181a and 181b, respectively.

FIG. 2 shows a schematic circuit diagram of the 6-in-1 module in the first and second embodiments. The reference numerals described in the drawings are common to FIGS. 1, 3, 4a, and 4b. Capacitors are drawn at positions according to the layout in the circuit schematic diagram. For example, in the case of U phase, capacitors 161a and 161b are written next to MOSFET and FWD.

Since there are two MOSFETs and two FWDs in the first embodiment, the number of elements is also shown in FIG. FIG. 3 shows a circuit diagram in which the number of elements is different from that in FIG. As shown in FIG. 3, which is a circuit simplified in this way, even if the present invention is applied to a modified example in which one MOSFET and one FWD are used for one arm and no capacitor is provided for each phase. good. Further, a plurality of elements having more than three elements may be introduced in parallel in one arm.

4a and 4b show mounting diagrams of the 6-in-1 module in the first and second embodiments. Two high-side MOSFETs for each phase are mounted on the DC positive electrode bus plate 110 mounted on the DC-side insulating plate 101 so as to contact the drain surface. Further, on the U-phase output bus plate 130, the V-phase output bus plate 140, and the W-phase output bus plate 150, two low-side MOSFETs for each phase are similarly mounted so as to be in contact with the drain surface. This MOSFET may have an IGBT structure as long as it is a switch element, and any element structure such as UPWM, SJ-PWM, IE-IGBT, etc. may be used. Further, Si may be used as the semiconductor material, or SiC may be used.

According to the study, the mounted high-side switch elements 133a, 133b, 143a, 143b, 153a, 153b, low-side switch elements 135a, 135b, 145a, 145b, 155a, 155b, and the element area of 0.42 cm ² SiC- By using MOSFET, a three-phase inverter with an output voltage of 650 V, an output of 150 kW, and an output density of 150 kW / L can be realized. Two FWDs are mounted on each arm of each phase in the vicinity of each MOSFET, and 132a and 132b correspond to this in the case of the U-phase high side. This FWD may have a PIN structure or an SBD structure.

DC positive electrode bus plate 110, DC negative electrode bus plate 120, each phase output bus plate 130, 140, 150, each gate signal pin 136, 139, 146, 149, 156, 159, each source signal pin 137, 138, 147, 148. , 157, 158, DC positive electrode terminal 111, and DC negative electrode terminal 121 are plated to prevent electrolytic corrosion and rust. Further, among the DC positive electrode bus plate 110, the DC negative electrode bus plate 120, and each phase output bus plate 130, 140, 150, a groove is provided only at the position where the MOSFET is mounted, and solder wettability is improved by plating with a gold flash or the like. As well as raising it, it prevents the solder from leaking to an unexpected position.

The gate terminals of the high-side MOSFET are directly soldered to the U-phase high-side gate signal pin 136, the V-phase high-side gate signal pin 146, and the W-phase high-side gate signal pin 156, and each high-side gate signal pin is isolated. It is soldered to the DC positive bus plate 136 with a substance sandwiched between them. This insulating material may be, for example, Al ₂ O ₃ or Si ₃ N ₄ . By using a material with a coefficient of thermal expansion close to that of a Si power switch element or SiC power switch element, the insulating material used here is a gate signal pin, solder, and power due to the difference in the coefficient of thermal expansion between the insulator and the power switch element during heat generation. The possibility that the power switch element is destroyed by the stress generated on the joint surface with the switch element is reduced.

The gate signal pin of the low-side MOSFET is provided with an insulating distance so as to be parallel to the phase output plates 130, 140, 150 mounted on the phase output side insulating plate 101. The U-phase low-side gate signal pin 139 and the U-phase MOSFETs 135a and 135b are connected by using metal films 162a and 162b, respectively. Similarly, the V-phase low-side gate signal pin 149 and the V-phase MOSFETs 145a and 145b are connected by using metal films 172a and 172b, respectively, and the W-phase low-side gate signal pin 159 and the W-phase MOSFETs 155a and 155b are connected by metal films 182a and 182b. Use to connect to each.

At this time, recesses 163, 173, and 183 are provided in the DC negative electrode bus plate so that the gate terminal does not short-circuit with the DC negative electrode bus plate, and the metal film passes through each recess to the gate pad and gate terminal of the power switch element. Connect with.

A 0.2 mm thick insulator is sandwiched between the 0.3 mm thick high side gate signal pin and the 0.3 mm thick high side source signal pin by soldering 0.1 mm thick on one side. The insulator between the side gate signal pin and the DC positive positive bath plate 110 is fixed with a thickness of 0.1 mm by soldering with a thickness of 0.1 mm on one side. As the insulating material, Si ₃ N ₄ having a withstand voltage of 31 kV / mm may be used, or any other material may be used as long as the withstand voltage of 2 kV or more is maintained.

Solder the switch element and FWD so that the phase output side insulating plate 101 shown in FIG. 4a and the DC side insulating plate 102 shown in FIG. 4b on which each component is mounted are parallel to each other, and perform reflow after pressure welding. And join.

Each of the low-side source signal pins 138, 148, and 158 has a shape extended from the DC negative electrode bus plate 120, and protrudes in a direction orthogonal to the current flow direction of the DC negative electrode bus plate 120. There is an appropriate spacing between the low-side gate signal pins 139, 149, 159 ends and the low-side source signal pins 138, 148, 158 ends to provide a female terminal, and in the embodiments shown in the figure. It is 1.7 mm.

Each high-side source signal pin 137, 147, 157 has a shape connected to the side surface of each phase output bus plate 130, 140, 150, respectively, and is integrally shaped when shaping each phase output bus plate. May be good. Each high side gate signal pin 136, 146, 156 is deformed from the point of passing through the side surface of the positive electrode bus plate 110, and each high side gate signal pin 136 corresponding to each high side source signal pin 137, 147, 157 end. , 146, 156 There is an appropriate space between the ends and the female terminals. In the embodiment in the figure, it is 1.7 mm.

The low-side gate signal pin and low-side source signal pin in each phase, and the high-side gate signal pin and high-side source signal pin in each phase are parallel to each other, and the current flowing through the center of the low-side gate signal pin in that phase and the low side in that phase. The current plane generated by the current flowing through the center of the source signal pin is orthogonal to the DC negative electrode bus plate 120 plane, or 90 ± 10 deg. It is desirable that it is within the range of. Similarly, the current flowing through the center of the high-side gate signal pin in a certain phase and the current plane flowing through the center of the high-side source signal pin in that phase are orthogonal to the plane of the DC positive bus plate 110, or 90 ± 10 deg. It is desirable that it is within the range of. This is because the mutual inductance between the current loops is proportional to Cos θ when the face-to-face angle θ is.

The current loop surface of the V-phase high-side gate signal pin 146 and the V-phase high-side source signal pin 147 in FIGS. 1 and 2 of Example 1 and the main current loop through which a current of 200 A flows through the V-phase output bus plate. The angle between the faces is tentatively 0 deg. In the case of the parallel relationship, the voltage derived from the mutual inductance coupling generated in the high side gate voltage reaches 3.79 V. Similarly, it is 4.07 V in the W phase. This face-to-face angle is 90 deg. If, the voltage generated in the V-phase high-side gate signal is 0 V, and the voltage generated in the W-phase gate signal is also 0 V.

At this time, if the angle between the faces is orthogonal to the orthogonal angle, ± 10 deg. When the slope is, the voltage derived from the mutual inductance coupling generated in the V-phase high-side gate voltage corresponding to the sign of the tilt is about ± 0.14 V, and the voltage derived from the mutual inductance coupling generated in the W phase is ± It will be 0.13 V. In the 6-in-1 module 100 shown in FIGS. 1 and 2 of the first embodiment, the time change of the current flowing through the main current loop surface does not affect the gate signal, or the amount of change in the potential on the gate signal is the gate. It is characterized by being within a range that does not pose a problem in terms of drive signal quality.

Each phase output terminal 131, 141, 151 is deformed to one side in order to prevent interference with each gate driver circuit 400, 500 and current detection devices 630, 640, 650. This deformed part exerts the effect of relaxing the stress applied to the contact between the male terminal and the female terminal on the module side due to the expansion when the power module generates heat, and reduces the possibility that the power module and peripheral parts are destroyed.

The 6-in-1 power module shown in FIG. 1 has a parasitic inductance between the DC input terminal 111 and each switch. When the value of the current flowing through this parasitic inductance fluctuates abruptly, a voltage corresponding to the parasitic inductance is generated. In order to suppress this potential fluctuation, a capacitor connected by a P-type terminal is provided inside the power module.

The potential fluctuation due to this parasitic inductance is predicted to be about 20 mV depending on the inductance of the DC positive electrode terminal portion for one phase and about 100 mV depending on the inductance of the phase output terminal when the flowing current is 200 A. Such potential fluctuation is not a monotonous overshoot or undershoot that is observed once for one switching, but vibration is generated by an LCR circuit composed of parasitic elements, and ringing at the time of switching occurs. This ringing causes a loss of the switch element and deteriorates the quality of the output power, so we want to reduce it as much as possible.

Such potential fluctuations can be suppressed by the illustrated P-type terminal capacitors 161a, 161b, 171a, 171b, 181a, 181b. In addition, these capacitors can also suppress the phenomenon that the potential fluctuates out of control due to other factors.

In the 6-in-1 power module shown in FIG. 1, the distance from the DC positive electrode terminal 111 to the U phase is the distance to the W phase, and the distance from the DC negative electrode terminal 121 to the U phase is the distance to the W phase. Are far from each other. Due to this difference in distance, the effects of parasitic inductance, parasitic capacitance, and parasitic resistance on the current supplied to each phase switch when each phase is switched also change.

The effects of the parasitic inductance and the parasitic resistance cannot be reduced by the DC link capacitors (not shown) provided outside the DC positive electrode terminal 111 and the DC negative electrode terminal 121. Capacitors 161a, 161b, 171a, 171b, 181a, 181b provided in each phase shown in FIG. 1 reduce the influence of the interphase parasitic element as described above, reduce the charge shortage immediately after the switch, and unexpected potential. Fluctuations can be reduced.

(Example 2)
FIG. 6 shows an inverter system using the 6-in-1 module 100 described in FIG. The inverter system has a form in which both sides of the 6 in 1 module 100 are sandwiched between the coolers 210 and 220, and the DC input capacitor 300 is connected to the 6 in 1 module 100.

When the DC positive bus plate 110 or the DC negative negative bath plate 120 generates a stress that deforms the DC side insulating plate 102 to the 6 in 1 module due to the heat generated inside the 6 in 1 module, the cooler 220 cancels the stress. It is designed to apply force to the DC side insulating plate 102. Similarly, when the phase output plates 130, 140, 150 generate stress that deforms the phase output side insulating surface 101, the cooler 210 is designed to apply a force that cancels the stress to the phase output side insulating surface 101. To.

The 3-phase low-side gate driver assembly 400 and the 3-phase high-side gate driver assembly 500 are removed and mounted coaxially with the gate signal pin protrusion direction of the 6-in-1 module by the gate driver fixtures 410 and 510.

The phase output current sensors 630, 640, and 650 are attached and detached coaxially with the phase output terminal protrusion direction corresponding to the phase output terminals 131, 141, and 151, respectively. Each phase output current sensor 630, 640, and 650 each has a metal portion bonded to a circuit board, and the metal portion is brought into contact with the side surface of the cooler 220 for cooling.

An exploded view of the inverter system shown in FIG. 6 is shown in FIG. The DC positive electrode input terminal 312 and the DC positive electrode output terminal 311 of the DC input capacitor 300 are connected by the same bus plate, and similarly, the DC negative electrode input terminal 322 and the DC negative electrode output terminal 321 are connected by the same bus plate. Each electrode is configured to be separated into left and right when the capacitor 300 is grasped from the upper surface in the figure.

The U-phase low-side gate driver circuit 430, the V-phase low-side gate driver circuit 440, and the W-phase low-side gate driver circuit 450 are each insulated and fixed to the low-side gate driver circuit fixture 410. Similarly, the U-phase high-side gate driver circuit 530, the V-phase high-side gate driver circuit 540, and the W-phase high-side gate driver circuit 550 are also insulated and fixed to the high-side gate driver circuit fixture 510.

The closer the length of the three-phase low-side gate driver assembly 400 and the three-phase high-side gate driver assembly 500 in the cooler thickness direction to the total value of the power module 100 thickness and the cooler 210 thickness, the higher the volumetric efficiency. Further, if the element mounted inside the 6-in-1 power module 100 and the gate driver circuit having a width close to the width of one phase occupying the DC positive electrode bus plate, the volumetric efficiency is similarly increased and the output density is higher. You can design an inverter.

Since there is a limit to the miniaturization of the floating power supply used in these gate driver circuits, the limit values of the gate driver circuit area and volume are naturally determined according to the characteristics such as the parasitic capacitance of the power switch element to be driven and the specifications of the power conversion device system. .. On the other hand, the fin spacing and flow velocity at which the cooler functions efficiently are limited by the refrigerant, fin length, fin height, and the like.

That is, the fin height and the above-mentioned gate when designing a cooler that can sufficiently cool and functions efficiently with the loss generated in the 6-in-1 module 100 as shown in FIG. 6 and the area for transferring heat thereof. There are not many options for various design values such that the lengths in the fin height direction in the driver circuit area are close to each other. The design example of the inverter system shown in FIG. 6 takes the above-mentioned relationship into consideration as compared with other designs, and is designed to realize an output density of 150 kW / L.

A schematic diagram of the inverter system circuit shown in FIG. 6 is shown in FIG. The high side gate driver and low side gate driver blocks are drawn separately in the circuit schematic diagram. It also shows that the current sensor is connected to the phase output terminals 131, 141, and 151. This current sensor may be a magnetic type or a shunt resistance type.

FIG. 9 shows the orthogonal relationship of the current loops flowing through the inverter system in the second embodiment. The current passed through the DC positive electrode bus plate 110 is output from the W phase output terminal 151 via the W phase output bus plate 150 (not shown in the figure) when the W phase high side MOSFETs 153a and 153b are turned on. Similarly, by turning on the V-phase low-side MOSFETs 145a and 145b, the current returned from the V-phase output terminal passes through the DC negative electrode bus plate 120, and the current returns to the DC input capacitor 300.

Since the flow of electrons is opposite to the current, the originally moving electrons flow in the opposite direction to the above-mentioned flow process. At this time, the loop surface of the current is composed of the current passing through the DC input capacitor 300, the DC positive electrode bus plate 110, the V phase output bus plate 140, and the DC negative electrode bus plate 120, and the magnetic flux radiates from the center of this loop surface. It occurs, passes through the outer circumference of each bus plate, and then becomes a closed path with a path back to the back side of the loop surface.

However, in this embodiment, since the cooler 210 and the cooler 220 are provided on both sides of the 6-in-1 module 100, some of the above-mentioned magnetic flux changes to a current in the metal portion on the bottom surface of each cooler. This proximity effect is observed from each bus plate in the 6 in 1 module as AC resistance to the current flowing through each bus plate.

In FIG. 9, the current loop surface 931, 941, 951 of the main current flowing through such a 6-in-1 module, the U-phase high-side gate signal pin 136, and the U-phase high-side source signal pin 137 pass through. It is shown that the gate signal pin current loop surface 932 and the loop surface 933 of the drive current flowing through the U-phase high side gate driver circuit 530 are all orthogonal to each other.

In the figure, the current loop surface passing through the 6-in-1 module, the current loop surface 933 flowing through the U-phase high-side gate driver circuit, and the current loop passing through the U-phase gate driver signal pin are shown. Although only the relationship with the surface 932 is described, the above-mentioned loop surface orthogonal relationship is described in the gate driver circuit described in FIG. 7 and the gate signal pin and source signal pin described in FIGS. 4a and 4b. It holds for everything between the current loop surface and the flowing current loop surface.

The orthogonal relationship between these current loop planes is shown in the three-axis diagram at the bottom center of Fig. 9. The main current loop plane inside the 6-in-1 module is shown by a broken line, and the gate signal pin current loop plane, which is the current loop between the gate signal pin and the source signal pin, is shown at one point. The chain line shows the current loop surface in the gate driver with a dotted line.

As shown in the three-axis diagram shown in FIG. 9, in the present invention, the inverter main current loop surface, the gate signal pin current loop surface, and the current loop surface in the gate driver circuit board are all orthogonal to each other in such an inverter system. It is characterized by being in a state. This feature is not limited to the three-phase inverter configuration as shown in the embodiment shown in FIG. 9, but is also satisfied in the half-bridge configuration, the full-bridge configuration, and the four-phase configuration of the three-phase inverter + half bridge.

A booster may be configured using this half-bridge configuration or a full-bridge configuration, a step-down transformer may be configured, or a bidirectional chopper circuit may be configured. Due to the features of the present invention, these circuits can be switched at a higher speed than conventional circuits, enabling high-frequency operation, and the circuit constants of passive components such as choke coils and output smoothing capacitors can be made smaller than those of conventional circuits. , The entire circuit can be miniaturized.

Further, the operation of the power module shown in the first and second embodiments may be an inverter operation or a PFC operation. It may function as an inverter for operating a traction motor for EVs and HVs, and also operates as a rectifier or PFC when recovering the counter electromotive voltage obtained from this traction motor to a storage battery or the like.

Conventionally, the improvement of the power density of the power conversion device has been limited from the following two points. The first point is that there is a limit to the miniaturization of the cooler due to the high loss of the power switch element and the problem of thermal resistance per area when transferring heat in the module. The second point is that as the operating frequency is increased, the loss also increases, so that the operating frequency has an upper limit due to the loss, and there is a limit to the miniaturization of passive components.

According to the present invention, the parasitic inductance of each part is reduced. Further, the mutual inductance between the gate driver circuit current loop surface, the gate signal pin current loop surface, and the main current loop surface becomes almost zero. Since the power switch element can be switched at high speed by this inductance reduction, the power modules according to the first and second embodiments have a low loss. Further, the power modules according to the first and second embodiments can be cooled from both sides, the ratio of the mounted element area to the cooling surface area of the module is close, and the area and volume are not wasted. The volume can be reduced. As described above, the power conversion device to which the present invention is applied has lower loss and better heat transfer characteristics than the conventional one, and the cooler can be miniaturized and the operating frequency can be increased, so that the passive components can be miniaturized. Is possible. By combining these characteristics, it has become possible to significantly increase the output density of the power conversion device.

The inverter system shown in Example 2 to which the present invention is applied exhibits an output density significantly exceeding 60 kW / L with respect to the output density of the current power conversion device having the maximum output density of around 60 kW / L. It is possible, and it makes it possible to achieve the output density that has been expected to be realized for some time.

100: 6 in 1 module 101: Phase output side insulating surface 102: DC side insulating surface 110: DC positive electrode bus plate 111: DC positive electrode terminal 120: DC negative electrode bus plate 121: DC negative electrode terminal 130: U phase output bus plate 131: U-phase output terminal 132a: U-phase high side FWD1
132b: U-phase high side FWD2
133a: U-phase high-side MOSFET1
133b: U-phase high-side MOSFET2
134a: U-phase low side FWD1
134b: U-phase low side FWD2
135a: U-phase low-side MOSFET1
135b: U-phase low-side MOSFET2
136: U-phase high-side gate signal pin 137: U-phase high-side source signal pin 138: U-phase low-side source signal pin 139: U-phase low-side gate signal pin 140: V-phase output bus plate 141: V-phase output terminal 142a: V Phase high side FWD1
142b: V-phase high side FWD2
143a: V-phase high-side MOSFET1
143b: V-phase high-side MOSFET2
144a: V-phase low side FWD1
144b: V-phase low side FWD2
145a: V-phase low-side MOSFET1
145b: V-phase low-side MOSFET2
146: V-phase high-side gate signal pin 147: V-phase high-side source signal pin 148: V-phase low-side source signal pin 149: V-phase low-side gate signal pin 150: W-phase output bus plate 1511: W-phase output terminal 152a: W Phase high side FWD1
152b: W phase high side FWD2
153a: W-phase high-side MOSFET1
153b: W-phase high-side MOSFET2
154a: W phase low side FWD1
154b: W phase low side FWD2
155a: W phase low side MOSFET1
155b: W phase low side MOSFET2
156: W-phase high-side gate signal pin 157: W-phase high-side source signal pin 158: W-phase low-side source signal pin 159: W-phase low-side gate signal pin 161a: U-phase capacitor a
161b: U-phase capacitor b
161c: P-shaped terminal 162a of U-phase capacitor a: U-phase gate film a
162b: U-phase gate film b
163: U-phase low-side recess 171a: V-phase capacitor a
171b: V-phase capacitor b
172a: V-phase gate film a
172b: V-phase gate film b
173: V-phase low-side recess 181a: W-phase capacitor a
181b: W-phase capacitor b
182a: W-phase gate film a
182b: W-phase gate film b
183: W phase low side recess 210: Cooler 1
220: Cooler 2
300: DC Input Capacitor 311: DC Positive Output Terminal 312: DC Positive Input Terminal 321: DC Negative Output Terminal 322: DC Negative Input Terminal 400: 3-Phase Low Side Gate Driver Aggregate 410: Low Side Gate Driver Fixture 430: U Phase Low Side Gate driver circuit 440: V-phase low-side gate driver circuit 450: W-phase low-side gate driver circuit 500: 3-phase high-side gate driver assembly 510: High-side gate driver fixture 530: U-phase high-side gate driver circuit 540: V-phase High side gate driver circuit 550: W phase high side gate driver circuit 630: U phase output section current sensor 640: V phase output section current sensor 650: W phase output section current sensor 931: U phase main current loop surface 932: U phase Gate signal Pin current loop surface 933: Drive current loop surface in U-phase driver circuit 941: V-phase main current loop surface 951: W-phase main current loop surface

Claims (18)

A DC positive electrode bus plate on which one or a plurality of positive electrode side power switch elements and one or a plurality of positive electrode side power diode elements are mounted, and one or a plurality of negative electrode side power switch elements and one or a plurality. It is equipped with a DC negative electrode bus plate on which a power diode element on the negative electrode side is mounted.
The one or more positive electrode side power switch elements, the one or more positive electrode side power switch elements, the one or more negative electrode side power switch elements, and the one or more negative electrode side power switches. A half-bridge configuration including a phase output bus plate for connecting each element of the element and a phase output terminal on the phase output bus plate.
In the DC positive electrode bus plate and the DC negative electrode bus plate, the planes on which the elements are mounted are parallel, and the extending directions thereof are parallel.
A high-side gate signal transmission pin for inputting a high-side gate signal in a direction orthogonal to the extending direction of the DC positive bus plate is provided, and a low-side gate signal is input in a direction orthogonal to the extending direction of the DC negative-negative bus plate. Equipped with a low side gate signal transmission pin
The high-side reference potential signal transmission pin to which the reference potential of the high-side gate signal is connected is provided so as to be parallel to the extending direction of the high-side gate signal transmission pin.
A power module including a low-side reference potential signal transmission pin to which a reference potential of the low-side gate signal is connected so as to be parallel to the extending direction of the low-side gate signal transmission pin. A capacitor having a P-type terminal capable of absorbing deformation due to thermal expansion is mounted between the DC positive electrode bus plate and the DC negative electrode bus plate in the half bridge configuration.
The power module according to claim 1, wherein the horizontal bar portion at the center of the P-shape is mounted on each bus plate. The DC positive electrode bus plate and the DC negative electrode bus plate that are part of the half bridge configuration are extended.
The one or more positive electrode side power switch elements, the one or more positive electrode side power diode elements, the one or more negative electrode side power switch elements, and the one or more negative electrode side power diodes. A full bridge with a design in which the element, the high-side gate signal transmission pin, the high-side reference potential signal transmission pin, the low-side gate signal transmission pin, the low-side gate reference potential signal transmission pin, and the phase output bus plate are duplicated by the number of phases. The power module according to claim 1 or 2, which is configured. The DC positive electrode bus plate and the DC negative electrode bus plate that are part of the half bridge configuration are extended.
The one or more positive electrode side power switch elements, the one or more positive electrode side power diode elements, the one or more negative electrode side power switch elements, and the one or more negative electrode side power diodes. A three-phase inverter configuration in which the element, the high-side gate signal transmission pin, the high-side reference potential signal transmission pin, the low-side gate signal transmission pin, the low-side reference potential signal transmission pin, and the phase output bus plate are duplicated by the number of phases. The power module according to claim 1 or 2. The DC positive electrode bus plate and the DC negative electrode bus plate that are part of the half bridge configuration are extended.
The one or more positive electrode side power switch elements, the one or more positive electrode side power diode elements, the one or more negative electrode side power switch elements, and the one or more negative electrode side power diodes. 1. Item 2. The power module according to Item 2. Between the DC positive electrode bus plate and the DC negative electrode bus plate, the one or a plurality of positive electrode side power switch elements, the one or a plurality of positive electrode side power diode elements, and the one or a plurality of negative electrode side power switches. With respect to the main current loop surface generated by connecting the element with the phase output bus plate through the one or more negative electrode side power diode elements.
The high-side current loop surface angle between the high-side gate signal current loop surface generated between the high-side gate signal transmission pin and the high-side reference potential signal transmission pin, and the low side with respect to the main current loop surface. Both angles of the low-side current loop surface-to-plane angle between the low-side gate signal current loop surface generated between the gate signal transmission pin and the low-side reference potential signal transmission pin are 80 deg. From 100 deg. The power module according to any one of claims 1 to 5, which is located between the two. Between the DC positive electrode bus plate and the DC negative electrode bus plate, the one or a plurality of positive electrode side power switch elements, the one or a plurality of positive electrode side power diode elements, and the one or a plurality of negative electrode side power switches. For each phase main current loop surface generated by connecting the element with each phase output bus plate duplicated by the number of phases through the one or a plurality of negative electrode side power diode elements.
With each phase high-side current loop surface-to-plane angle between each phase high-side gate signal current loop surface generated between the high-side gate signal transmission pin and the high-side reference potential signal transmission pin duplicated by the number of each phase. , Each phase between each phase low-side gate signal current loop surface generated between the low-side gate signal transmission pin and the low-side reference potential signal transmission pin duplicated by the number of each phase for each phase main current loop surface. Both angles with the phase low-side current loop face-to-face angle are 80 deg. From 100 deg. The power module according to any one of claims 1 to 5, which is located between the two. A DC positive electrode bus plate on which one or a plurality of positive electrode side power switch elements and one or a plurality of positive electrode side power diode elements are mounted, and one or a plurality of negative electrode side power switch elements and one or a plurality. It is equipped with a DC negative electrode bus plate on which a power diode element on the negative electrode side is mounted.
The one or more positive electrode side power switch elements, the one or more positive electrode side power switch elements, the one or more negative electrode side power switch elements, and the one or more negative electrode side power switches. It is a half-bridge configuration in which a phase output bus plate for connecting each element of the element is provided and the phase output bus plate is provided with a phase output terminal.
The DC positive electrode bus plate and the DC negative electrode bus plate are parallel to each other and their extending directions are parallel to each other on the planes on which the respective elements are mounted.
A high-side gate signal transmission pin for inputting a high-side gate signal in a direction orthogonal to the extending direction of the DC positive bus plate is provided, and a low-side gate signal is input in a direction orthogonal to the extending direction of the DC negative-negative bus plate. Equipped with a low side gate signal transmission pin
The high-side reference potential signal transmission pin to which the reference potential of the high-side gate signal is connected is provided so as to be parallel to the extending direction of the high-side gate signal transmission pin.
A power module including a low-side reference potential signal transmission pin to which a reference potential of the low-side gate signal is connected so as to be parallel to the extending direction of the low-side gate signal transmission pin.
The high side gate driver is on a plane that is orthogonal to the central axis of the high side gate signal transmission pin projecting portion protruding from the outer edge of the power module and is orthogonal to the DC positive electrode bus plate surface and the DC negative electrode bus plate surface direction. A plane provided with a circuit, parallel to the side surface of the DC negative electrode bus plate and orthogonal to the central axis of the low side gate signal transmission pin projecting portion protruding from the outer edge of the power module, and both in the direction of the DC positive electrode bus plate and the DC negative electrode bus plate surface. A power module equipped with a low-side gate driver circuit on a plane that is an orthogonal plane. A capacitor having a P-type terminal capable of absorbing deformation due to thermal expansion is mounted between the DC positive electrode bus plate and the DC negative electrode bus plate in the half-bridge configuration, and the horizontal bar portion at the center of the P-shaped shape is each bus. The power module according to claim 8, which has a form mounted on a plate. The DC positive electrode bus plate and the DC negative electrode bus plate that are part of the half bridge configuration are extended to include the one or more positive electrode side power switch elements and the one or more positive electrode side power diode elements. The one or more negative electrode side power switch elements, the one or more negative electrode side power diode elements, the high side gate signal transmission pin, the high side reference potential signal transmission pin, the low side gate signal transmission pin, and the low side reference. The power module according to claim 8 or 9, wherein the potential signal transmission pin and the phase output bus plate are duplicated by the number of phases to form a full bridge configuration. The DC positive electrode bus plate and the DC negative electrode bus plate that are part of the half bridge configuration are extended to include the one or more positive electrode side power switch elements and the one or more positive electrode side power diode elements. The one or more negative electrode side power switch elements, the one or more negative electrode side power diode elements, the high side gate signal transmission pin, the high side reference potential signal transmission pin, the low side gate signal transmission pin, and the low side reference. The power module according to claim 8 or 9, wherein the potential signal transmission pin and the phase output bus plate are duplicated by the number of phases to form a three-phase inverter configuration. The DC positive electrode bus plate and the DC negative electrode bus plate that are part of the half bridge configuration are extended to include the one or more positive electrode side power switch elements and the one or more positive electrode side power diode elements. The one or more negative electrode side power switch elements, the one or more negative electrode side power diode elements, the high side gate signal transmission pin, the high side reference potential signal transmission pin, the low side gate signal transmission pin, and the low side reference. The power module according to claim 8 or 9, wherein the potential signal transmission pin and the phase output bus plate are duplicated by the number of phases to form a 4-phase inverter configuration. Between the DC positive electrode bus plate and the DC negative electrode bus plate, the one or a plurality of positive electrode side power switch elements, the one or a plurality of positive electrode side power diode elements, and the one or a plurality of negative electrode side power switches. For each phase main current loop surface generated by connecting the element with each phase output bus plate duplicated by the number of phases through the one or a plurality of negative electrode side power diode elements.
The angle between each phase high-side current loop surface between each phase high-side gate signal current loop surface generated between the high-side gate signal transmission pin and the high-side reference potential signal transmission pin duplicated by the number of each phase is 80 deg. From 100 deg. Between
Each phase between each phase low-side gate signal current loop surface generated between the low-side gate signal transmission pin and the low-side reference potential signal transmission pin duplicated by the number of each phase for each phase main current loop surface. The angle between the low-side current loop faces is 80 deg. From 100 deg. Between
The power module according to any one of claims 8 to 12. The total width of the high-side gate driver board, which is the sum of the total value of the phase-to-phase insulation distance of the high-side gate driver circuit and the board width of one phase of the high-side gate driver circuit for the number of phases.
Alternatively, the total width of the low-side gate driver board, which is the total value of the phase-to-phase insulation distance of the low-side gate driver circuit and the board width of one phase of the low-side gate driver circuit, is further summed by the number of phases.
The power module according to any one of claims 8 to 13, which matches the total value of the number of phases of the positive electrode / negative electrode current flow direction width occupied by the half bridge configuration within ± 10 mm. The high-side gate driver circuit aggregate laid out in each phase by the number of phases of the power module with the high-side gate driver circuit separated by the insulation distance, and the number of phases of the power module with the low-side gate driver circuit separated by the insulation distance. The width of the low-side gate driver circuit assembly laid out in each phase is the width of the DC positive electrode bus plate or the width of the DC negative electrode bus plate in the positive electrode current negative electrode current flow direction of the power module that does not include the DC input / output terminal portion. The power module according to any one of claims 8 to 14, which matches within ± 30 mm. The power module thickness direction width of each phase of the high side gate driver circuit, or the power module thickness direction width of each phase of the low side gate driver circuit, and the thickness direction width of the cooler for cooling the power module and the power module. The power module according to any one of claims 8 to 14, wherein the total value with the width in the thickness direction matches within a range of ± 30 mm. Between the DC positive electrode bus plate and the DC negative electrode bus plate, the one or a plurality of positive electrode side power switch elements, the one or a plurality of positive electrode side power diode elements, and the one or a plurality of negative electrode side power switches. The main current loop surface generated by connecting the element and the one or more negative electrode side power diode elements by the phase output bus plate,
The high-side current loop surface-to-plane angle between the high-side gate signal current loop surface generated between the high-side gate signal transmission pin and the high-side reference potential signal transmission pin.
Each of the three types of high-side current generated between the high-side gate driver circuit and the current loop surface in the high-side gate driver circuit passing through the connection portion between the high-side gate signal transmission pin and the high-side reference potential signal transmission pin. The angle between the loop surfaces is 80 deg. From 100 deg. Is within the range of
The main current loop surface and
The angle between the low-side current loop surface and the low-side gate signal current loop surface generated between the low-side gate signal transmission pin and the low-side reference potential signal transmission pin.
The angle between each of the three types of low-side current loop surfaces generated between the low-side gate driver circuit and the current loop surface in the low-side gate driver circuit that passes through the connection portion between the low-side gate signal transmission pin and the low-side reference potential signal transmission pin. Are 80 deg. From 100 deg. Within the range of
The power module according to any one of claims 8 to 16. The phenomenon that the stress toward the outer surface of the power module, which is caused by the expansion of the DC positive electrode bus plate, the DC negative electrode bus plate, and the phase output bus plate due to heat generation, deforms the insulating surface of the power module is sufficiently suppressed. The bottom surface of the cooler in the cooler structure having sufficient strength required to exert the effect of keeping the insulating surface flatness of the power module within the specified value is the DC positive electrode bus plate or the DC negative electrode. A power module arranged in a position parallel to the bus plate or the phase bus plate.

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