JP2021153356A - Power factor enhancement device and power conversion apparatus - Google Patents

Abstract

To reduce common-mode noise of a totem pole type power factor enhancement circuit.SOLUTION: A power factor enhancement device 10 comprises: a first capacitance in parallel with a first inductance; a second capacitance in parallel with a second inductance; a third capacitance between a node N1 and a conductor part GND; a fourth capacitance between a node N2 and the conductor part GND; a fifth capacitance between an output terminal OUT1 and the conductor part GND; and a sixth capacitance between an output terminal OUT2 and the conductor part GND. The first and second inductances and the first to sixth capacitances are set so as to satisfy Z1:Z2=Z3:Z4, wherein Z1 is a combined impedance of the first inductance and the first capacitance where are in parallel with each other, Z2 is a combined impedance of the second inductance and the second capacitance which are in parallel with each other, Z3 is an impedance of the first capacitance and Z4 is a parallel combined impedance of the fourth to sixth capacitances.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a power factor improving device and a power conversion device.

Conventionally, switching power supply devices that operate by receiving the supply of AC power such as commercial power are equipped with a power factor improvement circuit that reduces the harmonic component of the input current and brings the power factor of the power supply device closer to 1. be.

A typical power factor improving circuit includes a diode bridge and a non-isolated boost converter connected to a subsequent stage. However, the conduction loss of the diode bridge is a main factor that lowers the power conversion efficiency of the power factor improving circuit. Therefore, various bridgeless power factor improvement circuits that eliminate the diode bridge have been proposed. As an example of a bridgeless power factor improvement circuit, a pair of switching elements connected in series with each other that switch at the frequency of the input AC power and a pair of switching elements that operate at a frequency higher than the frequency of the input AC power are connected in series with each other. There is a power factor improving circuit including another pair of switching elements, a so-called totem pole type power factor improving circuit. For example, Patent Documents 1 and 2 disclose a totem pole type power factor improving circuit.

Japanese Unexamined Patent Publication No. 2012-070490 JP 2015-192546 Japanese Unexamined Patent Publication No. 2013-149755

The totem pole type power factor improving circuit realizes high power conversion efficiency with a simple circuit configuration as compared with other power factor improving circuits, but on the other hand, it generates a large common mode noise. Therefore, a large noise filter is required to reduce the common mode noise propagating from the power factor improving circuit to the external circuit, which is a factor that hinders the miniaturization of the equipment. Therefore, it is required to reduce the generation of common mode noise in the power factor improving circuit.

Patent Documents 1 and 2 disclose that noise caused by a surge current generated when the polarity of an input AC voltage is reversed is reduced. If the surge current is reduced, it is considered that the common mode noise caused by the surge current is also reduced. However, since the circuits of Patent Documents 1 and 2 require a complicated configuration and control, it is required to reduce common mode noise with a simpler configuration and control.

Patent Document 3 discloses a circuit for reducing common mode noise. According to Patent Document 3, two terminals of a switching element, which is a noise source, are connected to a power supply via wiring of a substrate having inductance, and further, parasiticism generated between the wiring and a metal housing. Each is connected to the housing via capacitance. A bridge circuit is composed of these noise sources, inductance, and parasitic capacitance. Common mode noise is reduced by configuring the substrate so that the inductance and parasitic capacitance satisfy a predetermined relationship.

However, the invention according to Patent Document 3 is premised on a circuit having high symmetry between the circuit portion including the positive electrode bus and the circuit portion including the negative electrode bus, such as a full bridge circuit and an insulated step-down DC / DC converter circuit. It is supposed to be. Therefore, the invention according to Patent Document 3 cannot be applied to a circuit having a strong asymmetry between the circuit portion including the positive electrode bus and the circuit portion including the negative electrode bus, and in such a circuit, common mode noise can be reduced. Can not. In addition, even if the circuit has high symmetry in design, the actual symmetry may be impaired due to the influence of parasitic capacitance generated in the circuit. In this case as well, the common mode noise should be sufficiently reduced. I can't.

An object of the present disclosure is to provide a power factor improving device that operates as a totem pole type power factor improving circuit, which can reduce common mode noise more than before by a simple configuration and control. There is. An object of the present disclosure is to provide a power conversion device including such a power factor improving device.

According to the power factor improving device according to one aspect of the present disclosure.
A power factor improving device that converts AC power supplied to the first and second input terminals into DC power and improves the power factor to output from the first and second output terminals. The device is
An input capacitor connected between the first and second input terminals,
An output capacitor connected between the first and second output terminals,
A first and second switching element connected in series between the first and second output terminals and performing switching operation at a frequency higher than the frequency of the AC power.
With the third and fourth switching elements connected in series between the first and second output terminals and in parallel with the first and second switching elements and switching at the frequency of the AC power. ,
With the first and second inductors,
Equipped with a conductor part
The first inductor is connected between the first input terminal and a first connection point between the first and second switching elements and has a first inductance.
The second inductor is connected between the second input terminal and the second connection point between the third and fourth switching elements and has a second inductance.
The power factor improving device further
A first capacitance parallel to the first inductance,
A second capacitance parallel to the second inductance,
A third capacitance between the first connection point and the conductor portion,
A fourth capacitance between the second connection point and the conductor portion,
A fifth capacitance between the first output terminal and the conductor portion,
It has a sixth capacitance between the second output terminal and the conductor portion.
The first and second inductances and the first to sixth capacitances are
Z1: Z2 = Z3: Z4
Set to meet
Here, Z1 is the combined impedance of the first inductance and the first capacitance parallel to each other, Z2 is the combined impedance of the second inductance and the second capacitance parallel to each other, and Z3. Is the impedance of the third capacitance, and Z4 is the parallel combined impedance of the fourth to sixth capacitances.

According to the power factor improving device according to one aspect of the present disclosure, common mode noise can be reduced as compared with the conventional case by a simple configuration and control while operating as a totem pole type power factor improving circuit.

It is a circuit diagram which shows the structure of the power factor improvement apparatus 10 which concerns on 1st Embodiment. It is a figure explaining the operation of the power factor improving apparatus 10 of FIG. 1, and is the figure which shows the current I1 which flows in the 1st state of operation. It is a figure explaining the operation of the power factor improving apparatus 10 of FIG. 1, and is the figure which shows the current I2 which flows in the 2nd state of operation. It is a figure explaining the operation of the power factor improving apparatus 10 of FIG. 1, and is the figure which shows the current I3 which flows in the 3rd state of operation. It is a figure explaining the operation of the power factor improving apparatus 10 of FIG. 1, and is the figure which shows the current I4 which flows in the 4th state of operation. It is an equivalent circuit diagram of the power factor improving apparatus 10 of FIG. It is a circuit diagram which shows the structure of the evaluation system for measuring the common mode noise generated in the power factor improvement apparatus which concerns on 1st Embodiment. It is a circuit diagram which shows the structure of the power factor improvement apparatus 20 which concerns on a comparative example. It is a graph which shows the frequency characteristic of the common mode voltage Vcm generated in the power factor improving apparatus 20 of FIG. It is a graph which shows the frequency characteristic of the common mode voltage Vcm generated in the power factor improving apparatus 10 of FIG. It is a circuit diagram which shows the structure of the power factor improvement apparatus 10A which concerns on 1st modification of 1st Embodiment. It is an equivalent circuit diagram of the power factor improvement device 10A of FIG. It is a circuit diagram which shows the structure of the power factor improvement apparatus 10B which concerns on the 2nd modification of 1st Embodiment. It is an equivalent circuit diagram of the power factor improvement device 10B of FIG. It is a graph which shows the frequency characteristic of the common mode voltage Vcm generated in the power factor improving apparatus 10B of FIG. It is a circuit diagram which shows the structure of the power factor improvement apparatus 10C which concerns on the 3rd modification of 1st Embodiment. It is an equivalent circuit diagram of the power factor improvement device 10C of FIG. It is a circuit diagram which shows the structure of the power factor improvement apparatus 10D which concerns on the 4th modification of 1st Embodiment. It is an equivalent circuit diagram of the power factor improvement device 10D of FIG. It is a circuit diagram which shows the structure of the power factor improvement apparatus 10E which concerns on 2nd Embodiment. It is an equivalent circuit diagram of the power factor improvement device 10E of FIG. It is a graph which shows the frequency characteristic of the common mode voltage Vcm generated in the power factor improving apparatus 10E of FIG. It is a circuit diagram which shows the structure of the power factor improvement apparatus 10F which concerns on 3rd Embodiment. It is an equivalent circuit diagram of the power factor improvement device 10F of FIG. 23. It is a graph which shows the frequency characteristic of the common mode voltage Vcm generated in the power factor improving apparatus 10F of FIG. It is a circuit diagram which shows the structure of the power factor improvement apparatus 10G which concerns on 4th Embodiment. It is a block diagram which shows the structure of the power conversion apparatus 100 which concerns on 5th Embodiment. It is a block diagram which shows the structure of the power conversion apparatus 100A which concerns on the modification of 5th Embodiment.

Hereinafter, each embodiment according to the present disclosure will be described with reference to the drawings. In each of the following embodiments, the same reference numerals are given to the same components.

[First Embodiment]
[Structure of power factor improving device]
FIG. 1 is a circuit diagram showing the configuration of the power factor improving device 10 according to the first embodiment. The power factor improving device 10 converts the AC power supplied to the input terminals IN1 and IN2 into DC power, improves the power factor, and outputs the power factor from the output terminals OUT1 and OUT2. The input terminals IN1 and IN2 are connected to, for example, an AC power supply that supplies AC power of 50 Hz or 60 Hz. The output terminals OUT1 and OUT2 are connected to, for example, a load device that operates with DC power, or a voltage converter such as a DC / DC converter or an inverter. The power factor improving device 10 operates as a totem pole type power factor improving circuit.

In the present specification, the input terminals IN1 and IN2 are also referred to as "first and second input terminals", respectively, and the output terminals OUT1 and OUT2 are also referred to as "first and second output terminals", respectively.

The power factor improving device 10 includes a control circuit 1, an input capacitor Cin, an output capacitor Cout, transistors Q1 and Q2, diodes D1 and D2, inductors L1 and L2, and a conductor portion GND.

The input capacitor Cin is connected between the input terminals IN1 and IN2. The output capacitor Cout is connected between the output terminals OUT1 and OUT2 to smooth the output power.

The transistors Q1 and Q2 are connected in series between the output terminals OUT1 and OUT2. The transistors Q1 and Q2 are switching elements that turn on / off at a frequency higher than the frequency of AC power, for example, several hundred kHz, under the control of the control circuit 1. The transistors Q1 and Q2 are, for example, a GaN-based HEMT (high electron mobility transistor) or a MOSFET having sufficient switching characteristics (for example, reverse recovery characteristics) to operate at the above-mentioned switching frequency. May be good.

The diodes D1 and D2 are connected in series between the output terminals OUT1 and OUT2 and in parallel with the transistors Q1 and Q2. During the positive time period of the AC voltage applied to the input terminals IN1 and IN2, no current flows through the diode D1 and a current flows through the diode D2. In other words, at this time, the diode D1 is turned off and the diode D2 is turned on. During the negative time period of the AC voltage applied to the input terminals IN1 and IN2, a current flows through the diode D1 and no current flows through the diode D2. In other words, at this time, the diode D1 is turned on and the diode D2 is turned off. Therefore, the diodes D1 and D2 are switching elements that turn on / off at the frequency of AC power.

In the present specification, the transistors Q1 and Q2 are also referred to as "first and second switching elements", respectively, and the diodes D1 and D2 are also referred to as "third and fourth switching elements", respectively. Further, in the present specification, the connection point N1 between the transistors Q1 and Q2 is also referred to as a "first connection point", and the connection point N2 between the diodes D1 and D2 is also referred to as a "second connection point". ..

The control circuit 1 controls the on / off of the transistors Q1 and Q2 so as to reduce the harmonic component of the input current and bring the power factor of the power factor improving device 10 closer to 1.

The inductor L1 is connected between the input terminal IN1 and the connection point N1 and has a predetermined inductance. The inductor L2 is connected between the input terminal IN2 and the connection point N2 and has a predetermined inductance.

In the present specification, the inductor L1 is also referred to as a "first inductor", and its inductance is also referred to as a "first inductance". Further, in the present specification, the inductor L2 is also referred to as a "second inductor", and the inductance thereof is also referred to as a "second inductance".

The conductor section GND is, for example, a ground conductor of a circuit, a shield, a metal housing, a heat sink, and / or other metal parts.

The power factor improving device 10 further includes a first capacitance parallel to the inductance of the inductor L1, a second capacitance parallel to the inductance of the inductor L2, and a third capacitance between the connection point N1 and the conductor portion GND. , A fourth capacitance between the connection point N2 and the conductor portion GND, a fifth capacitance between the output terminal OUT1 and the conductor portion GND, and a sixth capacitance between the output terminal OUT2 and the conductor portion GND. And have. In the example of FIG. 1, the first to sixth capacitances include parasitic capacitances C1 to C6, respectively.

The parasitic capacitance C1 is, for example, a capacitance generated between the windings of the inductor L1.

The parasitic capacitance C2 is, for example, a capacitance generated between the windings of the inductor L2.

The parasitic capacitance C3 is, for example, a capacitance generated between the drain of the transistor Q2 and the conductor portion GND when the transistor Q2 is a GaN-based HEMT.

The parasitic capacitance C4 is, for example, a capacitance generated between the cathode of the diode D2 and the conductor portion GND.

The parasitic capacitance C5 is, for example, a capacitance generated between the drain of the transistor Q1 and the conductor portion GND when the transistor Q1 is a GaN-based HEMT. Further, the parasitic capacitance C5 is, for example, a capacitance generated between the cathode of the diode D1 and the conductor portion GND. Further, the parasitic capacitance C5 is, for example, a capacitance generated between the conductor pattern of the output positive electrode bus on the substrate and the conductor portion GND. Further, the parasitic capacitance C5 may be, for example, a synthetic capacitance thereof.

The parasitic capacitance C6 is, for example, a capacitance generated between the conductor pattern of the output negative electrode bus on the substrate and the conductor portion GND.

In the present specification, the parasitic capacitances C1 to C6 are also referred to as "first to sixth parasitic capacitances", respectively.

[Operation of totem pole type power factor improvement circuit]
Here, the operation of the power factor improving device 10 as a totem pole type power factor improving circuit will be described with reference to FIGS. 2 to 5.

FIG. 2 is a diagram for explaining the operation of the power factor improving device 10 of FIG. 1, and is a diagram showing a current I1 flowing in the first state of the operation. FIG. 3 is a diagram for explaining the operation of the power factor improving device 10 of FIG. 1, and is a diagram showing a current I2 flowing in the second state of the operation. FIG. 4 is a diagram for explaining the operation of the power factor improving device 10 of FIG. 1, and is a diagram showing a current I3 flowing in a third state of operation. FIG. 5 is a diagram for explaining the operation of the power factor improving device 10 of FIG. 1, and is a diagram showing a current I4 flowing in a fourth state of operation. In the examples of FIGS. 2 to 5, the AC power supply 11 is connected to the input terminals IN1 and IN2 of the power factor improving device 10.

2 and 3 show the operation of the power factor improving device 10 during a positive time period of the AC voltage applied to the input terminals IN1 and IN2. As shown in FIGS. 2 and 3, during the positive time period of the AC voltage, the diode D1 is always off and the diode D2 is always on, while the transistors Q1 and Q2 are pre-installed above the frequency of the AC voltage. It is switched at a fixed frequency. In the case of FIG. 2, magnetic energy is accumulated in the inductors L1 and L2 by turning off the transistor Q1 and turning on the transistor Q2. In the case of FIG. 3, by turning on the transistor Q1 and turning off the transistor Q2, the magnetic energy stored in the inductors L1 and L2 is transmitted to the output capacitor Cout as electrical energy.

4 and 5 show the operation of the power factor improving device 10 during the negative time period of the AC voltage applied to the input terminals IN1 and IN2. As shown in FIGS. 4 and 5, during the negative time period of the AC voltage, the diode D1 is always on and the diode D2 is always off, while the transistors Q1 and Q2 are pre-installed above the frequency of the AC voltage. It is switched at a fixed frequency. In the case of FIG. 4, magnetic energy is accumulated in the inductors L1 and L2 by turning on the transistor Q1 and turning off the transistor Q2. In the case of FIG. 5, by turning off the transistor Q1 and turning on the transistor Q2, the magnetic energy stored in the inductors L1 and L2 is transmitted to the output capacitor Cout as electrical energy.

The control circuit 1 monitors at least one of the input voltage, input current, output voltage, and output current, and reduces the harmonic component of the input current based on the monitored voltage and / or current to reduce the power factor. The on / off of the transistors Q1 and Q2 is controlled so that the power factor of the rate improving device 10 approaches 1.

According to the operating principle described with reference to FIGS. 2 to 5, the switching operation of the transistors Q1 and Q2 is performed for each positive / negative time period of the AC voltage applied to the input terminals IN1 and IN2, that is, the AC voltage. It changes every half cycle. As a result, the power factor improving device 10 can convert AC power into DC power without using a diode bridge, and can improve the power factor.

[Reduction of common mode noise]
Next, with reference to FIG. 6, reduction of common mode noise by the power factor improving device 10 according to the embodiment will be described.

FIG. 6 is an equivalent circuit diagram of the power factor improving device 10 of FIG. FIG. 6 shows an equivalent circuit of the power factor improving device 10 in a high frequency band including the switching frequencies of the transistors Q1 and Q2.

The input capacitor Cin and the output capacitor Cout have, for example, a capacitance of several hundred nF to several hundred μF. Therefore, in the high frequency band, as shown in FIG. 6, the input terminals IN1 and IN2 can be regarded as the same node, and the output terminals OUT1 and OUT2 can also be regarded as the same node.

Further, as described with reference to FIGS. 2 and 3, the diode D2 is always on (that is, short-circuited) during the positive time period of the AC voltage applied to the input terminals IN1 and IN2, so that the diode D2 is connected. The point N2 and the output terminal OUT2 can be regarded as the same node. Further, as described with reference to FIGS. 4 and 5, the diode D1 is always on (that is, short-circuited) during the negative time period of the AC voltage applied to the input terminals IN1 and IN2, so that the diode D1 is connected. The point N2 and the output terminal OUT1 can be regarded as the same node. Therefore, in the high frequency band, as shown in FIG. 6, the connection point N2 and the output terminals OUT1 and OUT2 can be regarded as the same node regardless of whether the input voltage is positive or negative.

As described above, the switching operation of the transistors Q1 and Q2 is switched every positive / negative time period of the AC voltage applied to the input terminals IN1 and IN2. However, since the connection point N2 and the output terminals OUT1 and OUT2 can be regarded as the same node in the high frequency band, the power factor improving device 10 of FIG. 1 is shown in FIG. 6 regardless of whether the input voltage is positive or negative. It can be represented by the same equivalent circuit.

The power factor improving device 10 of FIG. 1 includes four circuit portions each having impedances Z1 to Z4. Z1 is the combined impedance of the inductance of the inductor L1 and the first capacitance in parallel with it. Z2 is the combined impedance of the inductance of the inductor L2 and the second capacitance in parallel with it. Z3 is the impedance of the third capacitance. Z4 is a parallel combined impedance of the fourth to sixth capacitances.

In the examples of FIGS. 1 and 6, Z1 is the impedance of the parallel circuit including the inductor L1 and its parasitic capacitance C1. Further, Z2 is the impedance of the parallel circuit including the inductor L2 and its parasitic capacitance C2. Further, Z3 is the impedance of the parasitic capacitance C3. Further, Z4 is the impedance of the parallel circuit including the parasitic capacitances C4 to C6. Therefore, in the examples of FIGS. 1 and 6, the impedances Z1 to Z4 at the frequency f (that is, the angular frequency ω) are represented by the following equations.

Z1 = {(ω ・ L1) ‖ (1 / (ω ・ C1))} (1)
Z2 = {(ω ・ L2) ‖ (1 / (ω ・ C2))} (2)
Z3 = 1 / (ω ・ C3) (3)
Z4 = 1 / (ω (C4 + C5 + C6)) (4)

Here, {A‖B} indicates the impedance A × B / (A + B) of a parallel circuit composed of two circuit portions having impedances A and B, respectively.

In FIG. 6, Vsw indicates a voltage generated between the connection points N1 and N2 according to the operation of the transistors Q1 and Q2. Further, Vcm indicates the potential of the input terminal IN1 or IN2 with respect to the conductor portion GND. The common mode noise of the power factor improving device 10 is derived from this potential Vcm if the mode conversion outside the circuit is ignored. Hereinafter, the potential Vcm is referred to as "common mode voltage".

Since the equivalent circuit of FIG. 6 has a Wheatstone bridge configuration, the voltage transfer coefficient Vcm / Vsw from Vsw to Vcm can ideally be set to zero when the impedances Z1 to Z4 satisfy the following equations.

Z1: Z2 = Z3: Z4 (5)

At this time, it is possible to reduce the common mode noise generated due to the operation of the transistors Q1 and Q2 and propagated from the input terminals IN1 and IN2 to the circuit in the previous stage.

Equation (5) may be expressed as the following equation by substituting equations (1) to (4).

{(Ω ・ L1) ‖ (1 / (ω ・ C1))} / {(ω ・ L2) ‖ (1 / (ω ・ C2))}
= (1 / (ω ・ C3)) / (1 / (ω (C4 + C5 + C6))) (6)

In the present specification, the condition of the formula (5) or the formula (6) is referred to as an “impedance balance condition”.

The size of the parasitic capacitances C3 to C6 depends on the routing of the conductor pattern of the wiring, the positional relationship between the switching element and the heat sink, the structure of the housing, etc., but it should be derived by, for example, three-dimensional electromagnetic field analysis or impedance measurement. Can be done. Therefore, the right side of the equation (6) is uniquely determined. Therefore, by setting the inductance of the inductors L1 and L2 and the parasitic capacitances C1 and C2 so as to satisfy the equation (6), the voltage transfer coefficient Vcm / Vsw from Vsw to Vcm is ideally set to zero and is common. Mode noise can be reduced. By using the parasitic capacitances C1 and C2 instead of the capacitors of the discrete elements, it is possible to provide the power factor improving device 10 having a small number of parts, a small mounting area, and a low cost.

When the inductance of the inductors L1 and L2 and the parasitic capacitances C1 and C2 are known, the parasitic capacitances C3 to C6 may be set so as to satisfy the equation (6). In other words, in this case, the conductor pattern of the wiring, the positional relationship between the switching element and the heat sink, the structure of the housing, and the like may be designed so that the parasitic capacitances C3 to C6 satisfying the equation (6) are generated. ..

A parallel circuit consisting of an inductance and a capacitance has a predetermined resonance frequency. Here, it is assumed that the resonance frequencies of the inductors L1 and the parasitic capacitance C1 parallel to each other and the resonance frequencies of the inductors L2 and the parasitic capacitance C2 parallel to each other are set to be equal to each other. In the impedance of the parallel circuit including the inductance and the capacitance, the inductance becomes dominant in the frequency band lower than the resonance frequency, and the capacitance becomes dominant in the frequency band higher than the resonance frequency. Therefore, in the frequency band lower than the resonance frequency, the impedances Z1 and Z2 are simply expressed by the following equations.

Z1 = ω ・ L1 (1a)
Z2 = ω ・ L2 (2a)

When the impedances Z1 and Z2 are expressed by the equations (1a) and (2a), the impedance balance condition is expressed by the following equation.

(Ω ・ L1) / (ω ・ L2)
= (1 / (ω ・ C3)) / (1 / (ω (C4 + C5 + C6))) (7)

On the other hand, in the frequency band higher than the resonance frequency, the impedances Z1 and Z2 are simply expressed by the following equations.

Z1 = 1 / (ω ・ C1)) (1b)
Z2 = 1 / (ω ・ C2)) (2b)

When the impedances Z1 and Z2 are expressed by the equations (1b) and (2b), the impedance balance condition is expressed by the following equation.

(1 / (ω ・ C1)) / (1 / (ω ・ C2))
= (1 / (ω ・ C3)) / (1 / (ω (C4 + C5 + C6))) (8)

Therefore, the common mode noise can be reduced by setting the inductances of the inductors L1 and L2 so as to satisfy the equation (7) and setting the parasitic capacitances C1 and C2 so as to satisfy the equation (8). At this time, since the angular frequencies ω are canceled on both sides of the equations (7) and (8), the impedance balance condition can be satisfied regardless of the frequency. Therefore, according to the power factor improving device 10 according to the embodiment, the common mode noise can be reduced in a wide frequency range.

[Example of the first embodiment]
A circuit simulation was performed to verify the substantive configuration and effect of the power factor improving device 10 according to the first embodiment.

FIG. 7 is a circuit diagram showing a configuration of an evaluation system for measuring common mode noise generated in the power factor improving device according to the first embodiment. The system of FIG. 7 includes an AC power supply 11, a pseudo power supply network 12, a power factor improving device 10, and a load resistance Rload. The pseudo power supply network 12 includes capacitors C21 to C24, inductors L21 and L22, and resistors R21 to R24. The pseudo power supply network 12 is connected between the AC power supply 11 and the power factor improving device 10, and stabilizes the impedance of the AC power supply 11 when the AC power supply 11 is viewed from the power factor improving device 10. The power factor improving device 10 of FIG. 7 is configured in the same manner as the power factor improving device 10 of FIG.

An equivalent circuit model of the evaluation system shown in FIG. 7 was created, and transient analysis was performed using a circuit simulator. The frequency characteristics of the common mode voltage Vcm are calculated by calculating the common mode voltage Vcm = (V22 + V24) / 2 based on the voltages V22 and V24 induced in the resistors R22 and R24 of the pseudo power supply network 12, respectively, and performing a fast Fourier transform. Was calculated.

In the circuit simulation, the parameters shown in Tables 1 to 4 below were used.

[Table 1]
――――――――――――――――――――
Element setting value ――――――――――――――――――――
C3 20pF
C4 2pF
C5 25pF
C6 3pF
――――――――――――――――――――

[Table 2]
――――――――――――――――――――
Element setting value ――――――――――――――――――――
L1 180 μH
L2 120 μH
C1 32pF
C2 48pF
――――――――――――――――――――

[Table 3]
――――――――――――――――――――
Element setting value ――――――――――――――――――――
Cin 440nF
Cout 600μF
Rload 50Ω
C21, C23 1μF
C22, C24 100nF
L21, L22 50μH
R21, R23 1kΩ
R22, R24 50Ω
――――――――――――――――――――

[Table 4]
――――――――――――――――――――――――――――――
Input AC voltage 100Vac, 50Hz
Switching frequency of transistors Q1 and Q2
200kHz
Output DC voltage 400Vdc
――――――――――――――――――――――――――――――

Table 2 shows the inductances of the inductors L1 and L2 set to satisfy the equation (7) and the parasitics set to satisfy the equation (8) when the parasitic capacitances C3 to C6 of Table 1 are set. The capacitances C1 and C2 are shown. Table 3 shows the set values of other elements, and Table 4 shows the driving conditions.

FIG. 8 is a circuit diagram showing the configuration of the power factor improving device 20 according to the comparative example. The power factor improving device 20 has a configuration in which the inductor L2 and the parasitic capacitance C2 are removed from the power factor improving device 10 of FIG. Therefore, the power factor improving device 20 does not satisfy the impedance balance conditions of the equations (6) to (8). In the system of FIG. 7, a power factor improving device 20 was connected instead of the power factor improving device 10, and a circuit simulation was performed in the same manner as in the case of the power factor improving device 10 to calculate the frequency characteristics of the common mode voltage Vcm. In the circuit simulation of the power factor improving device 20, the inductance of the inductor L1 was set to 300 μH, the parasitic capacitance C1 was set to 40 pF, and the same parameters as in Tables 1, 3 and 4 were used for other elements. ..

By comparing the common mode voltage Vcm of the power factor improving device 10 according to the embodiment with the common mode voltage Vcm of the power factor improving device 20 according to the comparative example, the power factor improving device 10 according to the embodiment has common mode noise. We verified the effect of reducing.

FIG. 9 is a graph showing the frequency characteristics of the common mode voltage Vcm generated in the power factor improving device 20 of FIG. According to FIG. 9, it can be seen that a large common mode voltage Vcm is generated at a frequency that is an integral multiple of the switching frequency (200 kHz). This means the generation of large common mode noise.

FIG. 10 is a graph showing the frequency characteristics of the common mode voltage Vcm generated in the power factor improving device 10 of FIG. As described above, the inductances of the inductors L1 and L2 were set so as to satisfy the equation (7), and the parasitic capacitances C1 and C2 were set so as to satisfy the equation (8). In this case, according to FIG. 10, it can be seen that the common mode voltage Vcm is reduced by about 30 dB in a wide frequency range as compared with the case of FIG.

In FIG. 10, a steep peak remains near 1.6 MHz. This is due to the resonance of the inductor L1 and the parasitic capacitance C1 parallel to each other, or the resonance of the inductor L2 and the parasitic capacitance C2 parallel to each other. Impedance diverges infinitely at resonant frequencies of inductance and capacitance parallel to each other. In this case, the power factor improving device 10 does not satisfy the impedance balance conditions of the equations (7) and (8), and the effect of reducing the common mode noise is impaired, so that the above-mentioned peak occurs.

[Modified example of the first embodiment]
FIG. 11 is a circuit diagram showing the configuration of the power factor improving device 10A according to the first modification of the first embodiment. The power factor improving device 10A includes, in addition to each component of the power factor improving device 10 of FIG. 1, capacitors C11 and C12 of discrete elements connected in parallel to the inductors L1 and L2, respectively. Therefore, the power factor improving device 10A has a sum of the parasitic capacitance C1 and the capacitance of the capacitor C11 as a capacitance (“first capacitance”) parallel to the inductance of the inductor L1. Further, the power factor improving device 10A has a sum of the parasitic capacitance C2 and the capacitance of the capacitor C12 as a capacitance (“second capacitance”) parallel to the inductance of the inductor L2.

In the present specification, the capacitors C11 and C12 are also referred to as "first and second capacitors", respectively.

FIG. 12 is an equivalent circuit diagram of the power factor improving device 10A of FIG. In the examples of FIGS. 11 and 12, the impedances Z1 and Z2 at the angular frequency ω are represented by the following equations.

Z1 = {(ω ・ L1) ‖ (1 / (ω (C1 + C11)))} (1A)
Z2 = {(ω ・ L2) ‖ (1 / (ω (C2 + C12)))} (2A)

When the impedances Z1 and Z2 are expressed by the equations (1A) and (2A), the impedance balance condition is expressed by the following equation.

{(Ω ・ L1) ‖ (1 / (ω (C1 + C11)))} / {(ω ・ L2) ‖ (1 / (ω (C2 + C12)))}
= (1 / (ω ・ C3)) / (1 / (ω (C4 + C5 + C6))) (9)

Common mode noise can be reduced by setting the inductance of the inductors L1 and L2, the parasitic capacitances C1 and C2, and the capacitances of the capacitors C11 and C12 so as to satisfy the equation (9).

FIG. 13 is a circuit diagram showing the configuration of the power factor improving device 10B according to the second modification of the first embodiment. The power factor improving device 10B includes, in addition to each component of the power factor improving device 10 of FIG. 1, a capacitor C13 of a discrete element connected between the connection point N1 and the conductor portion GND. Therefore, the power factor improving device 10B has a sum of the parasitic capacitance C3 and the capacitance of the capacitor C13 as the capacitance (“third capacitance”) between the connection point N1 and the conductor portion GND.

In the present specification, the capacitor C13 is also referred to as a "third capacitor".

FIG. 14 is an equivalent circuit diagram of the power factor improving device 10B of FIG. In the examples of FIGS. 13 and 14, the impedance Z3 at the angular frequency ω is expressed by the following equation.

Z3 = 1 / (ω (C3 + C13)) (3B)

When the impedance Z3 is expressed by the equation (3B), the impedance balance condition is expressed by the following equation.

{(Ω ・ L1) ‖ (1 / (ω ・ C1))} / {(ω ・ L2) ‖ (1 / (ω ・ C2))}
= (1 / (ω (C3 + C13))) / (1 / (ω (C4 + C5 + C6)))
(10)

Common mode noise can be reduced by setting the capacitance of the capacitor C13 so as to satisfy the equation (10). For example, consider the case where inductors L1 and L2 having the same magnitudes of parasitic capacitances C3 to C6 and having the same inductance and the same parasitic capacitance are used. In this case, the impedances Z1 and Z2 are equal to each other, and the left side of the equation (10) is 1. At this time, in order to satisfy the impedance balance condition of the equation (10), the capacitance of the capacitor C13 is set so as to satisfy the following equation.

C13 = C4 + C5 + C6-C3 (11)

A circuit simulation was performed to verify the substantive configuration and effect of the power factor improving device 10B.

In the circuit simulation, the parameters in Tables 1, 3 and 4 described above were used. For the inductors L1 and L2 and the parasitic capacitances C1 and C2, the parameters shown in Table 5 below were used.

[Table 5]
――――――――――――――――――――
Element setting value ――――――――――――――――――――
L1 150 μH
L2 150μH
C1 40pF
C2 40pF
――――――――――――――――――――

At this time, the capacitance of the capacitor C13 was set to 10 pF from the equation (11).

FIG. 15 is a graph showing the frequency characteristics of the common mode voltage Vcm generated in the power factor improving device 10B of FIG. According to FIG. 15, it can be seen that the common mode voltage Vcm was reduced in a wide frequency range as in the case of FIG. However, according to FIG. 15, as in the case of FIG. 10, a peak due to the resonance of the inductor L1 and the parasitic capacitance C1 parallel to each other or the resonance of the inductor L2 and the parasitic capacitance C2 parallel to each other remains. ..

FIG. 16 is a circuit diagram showing the configuration of the power factor improving device 10C according to the third modification of the first embodiment. The power factor improving device 10C includes, in addition to each component of the power factor improving device 10 of FIG. 1, a capacitor C14 of a discrete element connected between the connection point N2 and the conductor portion GND. Therefore, the power factor improving device 10C has the sum of the parasitic capacitance C4 and the capacitance of the capacitor C14 as the capacitance (“fourth capacitance”) between the connection point N2 and the conductor portion GND.

In the present specification, the capacitor C14 is also referred to as a "fourth capacitor".

FIG. 17 is an equivalent circuit diagram of the power factor improving device 10C of FIG. In the examples of FIGS. 16 and 17, the impedance Z4 at the angular frequency ω is expressed by the following equation.

Z4 = 1 / (ω (C4 + C5 + C6 + C14)) (4C)

When the impedance Z4 is expressed by the equation (4C), the impedance balance condition is expressed by the following equation.

{(Ω ・ L1) ‖ (1 / (ω ・ C1))} / {(ω ・ L2) ‖ (1 / (ω ・ C2))}
= (1 / (ω ・ C3)) / (1 / (ω (C4 + C5 + C6 + C14))) (12)

Common mode noise can be reduced by setting the capacitance of the capacitor C14 so as to satisfy the equation (12).

FIG. 18 is a circuit diagram showing the configuration of the power factor improving device 10D according to the fourth modification of the first embodiment. The power factor improving device 10D includes, in addition to each component of the power factor improving device 10 of FIG. 1, discrete element capacitors C15 and C16 connected between the output terminals OUT1 and OUT2 and the conductor portion GND, respectively. The capacitors C15 and C16 are, for example, Y capacitors on the output side. Therefore, the power factor improving device 10D has a sum of the parasitic capacitance C5 and the capacitance of the capacitor C15 as the capacitance (“fifth capacitance”) between the output terminal OUT1 and the conductor portion GND. Further, the power factor improving device 10D has a sum of the parasitic capacitance C6 and the capacitance of the capacitor C16 as the capacitance (“sixth capacitance”) between the output terminal OUT2 and the conductor portion GND.

In the present specification, the capacitors C15 and C16 are also referred to as "fifth and sixth capacitors", respectively.

FIG. 19 is an equivalent circuit diagram of the power factor improving device 10D of FIG. In the examples of FIGS. 18 and 19, the impedance Z4 at the angular frequency ω is expressed by the following equation.

Z4 = 1 / (ω (C4 + C5 + C6 + C15 + C16)) (4D)

When the impedance Z4 is expressed by the equation (4D), the impedance balance condition is expressed by the following equation.

{(Ω ・ L1) ‖ (1 / (ω ・ C1))} / {(ω ・ L2) ‖ (1 / (ω ・ C2))}
= (1 / (ω ・ C3)) / (1 / (ω (C4 + C5 + C6 + C15 + C16)))
(13)

Common mode noise can be reduced by setting the capacitances of the capacitors C15 and C16 so as to satisfy the equation (13).

According to the power factor improving devices 10A to 10D according to the first to fourth modifications of the first embodiment, the degree of freedom in design is improved by combining the parasitic capacitance and the capacitor of the discrete element. Can be done. Further, when the capacitance of the capacitor is significantly larger than the parasitic capacitance, the magnitude of the first to sixth capacitances is substantially determined by the capacitance of the capacitor, and the parasitic capacitance may be ignored. Since the capacitor has a known capacitance, it becomes easy to design the capacitance value of each circuit portion of the power factor improving device, and it becomes easy to realize the impedance balance condition.

[Effect of the first embodiment]
According to the power factor improving device according to the first embodiment, common mode noise can be reduced as compared with the conventional case by a simple configuration and control while operating as a totem pole type power factor improving circuit.

According to the power factor improving device according to the first embodiment, the first and second inductances and the first to sixth capacitances are set so as to satisfy the impedance balance condition of the equation (5) and the like. Common mode noise can be reduced.

According to the power factor improving device according to the first embodiment, the first and second inductances and the first to sixth capacitances are set so as to satisfy the impedance balance conditions of the equations (7) and (8). By doing so, common mode noise can be reduced in a wide frequency range.

Conventionally, a common mode choke coil and a Y capacitor may be used as countermeasure components for suppressing common mode noise. However, in the power electronics circuit, the capacity of the Y capacitor is limited by the regulation on the leakage current, and the size of the common mode choke coil is increased in order to avoid magnetic saturation and reduce copper loss. According to the power factor improving device according to the first embodiment, the impedance balance condition can be satisfied by changing the circuit constant or adding a small number of parts without requiring a common mode choke coil and a Y capacitor, and thus the size of the device. And the cost can be reduced as compared with the conventional case.

[Second Embodiment]
FIG. 20 is a circuit diagram showing the configuration of the power factor improving device 10E according to the second embodiment. The power factor improving device 10E includes resistors R1 and R2 connected in parallel to the inductors L1 and L2, respectively, in addition to the components of the power factor improving device 10 of FIG.

In the present specification, the resistors R1 and R2 are also referred to as "first and second resistors", respectively.

As described above, in the frequency characteristic of the common mode voltage Vcm in FIG. 10, a steep peak due to resonance of inductance and capacitance in parallel with each other remains. In the second embodiment, resistors R1 and R2 are added in order to reduce common mode noise in the vicinity of the resonant frequencies of the inductances and capacitances parallel to each other. The resistors R1 and R2 are so-called damping resistors. The resistor R1 attenuates the current flowing through the inductor L1 and the parasitic capacitance C1 when the inductor L1 and the parasitic capacitance C1 in parallel with each other resonate. Similarly, the resistor R2 attenuates the current flowing through the inductor L2 and the parasitic capacitance C2 when the inductor L2 and the parasitic capacitance C2 in parallel with each other resonate. The resistors R1 and R2 have a resistance value of, for example, several kΩ or more in order to ensure the insulating property at both ends of the inductors L1 and L2.

FIG. 21 is an equivalent circuit diagram of the power factor improving device 10E of FIG. In the examples of FIGS. 20 and 21, only the resistors R1 and R2 dominate at the resonance frequencies of the inductances and capacitances parallel to each other, and the impedances Z1 and Z2 at the resonance frequencies are expressed by the following equations.

Z1 = R1 (1E)
Z2 = R2 (2E)

In the frequency band lower than the resonance frequency, the impedance balance condition is expressed by the equation (7), and in the frequency band higher than the resonance frequency, the impedance balance condition is expressed by the equation (8). On the other hand, at the resonance frequency, the impedance balance condition is expressed by the following equation.

R1 / R2
= (1 / (ω ・ C3)) / (1 / (ω (C4 + C5 + C6))) (14)

By setting the resistance values of the resistors R1 and R2 so as to satisfy the equation (14), the common mode noise can be reduced even at the resonance frequency.

A circuit simulation was performed to verify the substantive configuration and effect of the power factor improving device 10E.

In the circuit simulation, the parameters shown in Tables 1 to 4 above were used. The resistance values of the resistors R1 and R2 were set as follows in order to satisfy the impedance balance condition of the equation (14).

[Table 6]
――――――――――――――――――――
Element setting value ――――――――――――――――――――
R1 1.5kΩ
R2 1kΩ
――――――――――――――――――――

FIG. 22 is a graph showing the frequency characteristics of the common mode voltage Vcm generated in the power factor improving device 10E of FIG. 20. According to FIG. 22, since the impedance balance condition can be satisfied even at the resonance frequencies of the inductances and capacitances parallel to each other, it can be seen that the peak at the resonance frequency disappears and the common mode voltage Vcm is reduced over the entire frequency range.

According to the power factor improving device 10E according to the second embodiment, common mode noise can be reduced even at resonance frequencies of inductance and capacitance parallel to each other.

The resistors R1 and R2 may be applied to the power factor improving devices 10A to 10D according to another modification of the first embodiment.

[Third Embodiment]
FIG. 23 is a circuit diagram showing the configuration of the power factor improving device 10F according to the third embodiment. The power factor improving device 10F includes each component of the power factor improving device 10 of FIG. 1, and the inductors L1 and L2 are electromagnetically oriented from each other so that the magnetic flux generated by the common mode current flowing through the inductors L1 and L2 cancels each other out. Combined with.

As described above, in the frequency characteristic of the common mode voltage Vcm in FIG. 10, a steep peak due to resonance of inductance and capacitance in parallel with each other remains. In the third embodiment, the inductors L1 and L2 are coupled with opposite polarities in order to reduce common mode noise in the vicinity of the resonant frequencies of the inductances and capacitances parallel to each other.

In the basic operation (normal mode) of the power factor improving device 10F, the normal mode current flows through the inductors L1 and L2, and the magnetic flux is generated in the same direction by the electromagnetic induction of the inductors L1 and L2, and the magnetic fluxes strengthen each other. , L2 impedance increases. On the other hand, when a common mode current flows through the inductors L1 and L2, a magnetic flux in the opposite direction is generated to cancel the magnetic flux, and the inductance of the inductors L1 and L2 is reduced. Therefore, by coupling the inductors L1 and L2 with opposite polarities, the impedance of the inductors L1 and L2 is reduced when the common mode current flows through the inductors L1 and L2, and resonance of inductance and capacitance in parallel with each other is less likely to occur. ..

FIG. 24 is an equivalent circuit diagram of the power factor improving device 10F of FIG. 23.

In FIG. 24, M indicates the mutual inductance of the inductors L1 and L2, and is represented by the following equation.

M = k × √ (L1 × L2) (15)

Here, k indicates the coupling coefficient of the inductors L1 and L2.

The power factor improving device 10F has the sum of the self-inductance of the inductor L1 and the mutual inductance M as the inductance (“first inductance”) of the inductor L1 connected between the input terminal IN1 and the connection point N1. .. Further, in the power factor improving device 10F, the sum of the self-inductance of the inductor L2 and the mutual inductance M as the inductance (“second inductance”) of the inductor L2 connected between the input terminal IN2 and the connection point N2. Has. In the examples of FIGS. 23 and 24, the impedances Z1 and Z2 at the angular frequency ω are represented by the following equations.

Z1 = {(ω (L1 + M)) ‖ (1 / (ω ・ C1))} (1F)
Z2 = {(ω (L2 + M)) ‖ (1 / (ω ・ C2))} (2F)

In the frequency band lower than the resonance frequency, the impedances Z1 and Z2 may be simply expressed by the following equations.

Z1 = ω (L1 + M) (1Fa)
Z2 = ω (L2 + M) (2Fa)

When the impedances Z1 and Z2 are expressed by the equations (1Fa) and (2Fa), the impedance balance condition is expressed by the following equation.

(Ω (L1 + M)) / (ω (L2 + M))
= (1 / (ω ・ C3)) / (1 / (ω (C4 + C5 + C6))) (16)

Common mode noise can be reduced by setting the self-inductance and mutual inductance M of the inductors L1 and L2 so as to satisfy the equation (16).

A circuit simulation was performed to verify the substantive configuration and effect of the power factor improving device 10F.

In the circuit simulation, the parameters in Tables 1, 3 and 4 described above were used. For the inductors L1 and L2 and the parasitic capacitances C1 and C2, the parameters shown in Table 7 below were used.

[Table 7]
――――――――――――――――――――
Element setting value ――――――――――――――――――――
L1 207.7 μH
L2 92.3 μH
C1 32pF
C2 48pF
――――――――――――――――――――

Table 7 shows the inductances of the inductors L1 and L2 set to satisfy the equation (16) and the parasitics set to satisfy the equation (8) when the parasitic capacitances C3 to C6 of Table 1 are set. The capacitances C1 and C2 are shown. The coupling coefficient k of the inductor was set to 0.997.

FIG. 25 is a graph showing the frequency characteristics of the common mode voltage Vcm generated in the power factor improving device 10F of FIG. 23. According to FIG. 25, it can be seen that the peak generated near 1.6 MHz in the case of FIG. 10 is removed.

Further, according to FIG. 25, the common mode voltage Vcm is large at 20 MHz or higher. This is because, as a result of setting the coupling coefficient k = 0.997, the impedance balance condition is not satisfied due to the resonance of the leakage inductance and the parasitic capacitance. By bringing the coupling coefficient k close to 1, the common mode voltage Vcm at 20 MHz or higher is reduced. However, it is difficult to completely set the coupling coefficient k to 1 for an actual inductor. It can be said that the common mode noise is sufficiently reduced even when the coupling coefficient k = 0.997 as in this simulation.

According to the power factor improving device 10F according to the third embodiment, common mode noise can be reduced even at resonance frequencies of inductance and capacitance parallel to each other.

Further, by coupling the inductors L1 and L2 with opposite polarities, the inductance of the inductors L1 and L2 in the normal mode can be increased by the amount of the mutual inductance M. Therefore, the effect that the ripple current flowing through the inductors L1 and L2 can be reduced can also be obtained.

Even if the coupling of the inductors L1 and L2 with opposite polarities is applied to the power factor improving devices 10A to 10D according to another modification of the first embodiment and the power factor improving device 10E according to the second embodiment. good.

[Fourth Embodiment]
FIG. 26 is a circuit diagram showing the configuration of the power factor improving device 10G according to the fourth embodiment. The power factor improving device 10G includes transistors Q3 and Q4 and a control circuit 1G in place of the diodes D1 and D2 and the control circuit 1 of FIG.

The third and fourth switching elements are not limited to diodes, and may be transistors such as MOSFETs. In this case, the control circuit 1G turns off the transistor Q3 and turns on the transistor Q4 during the positive time period of the AC voltage applied to the input terminals IN1 and IN2. Further, the control circuit 1G turns on the transistor Q3 and turns off the transistor Q4 during the negative time period of the AC voltage applied to the input terminals IN1 and IN2. Therefore, the transistors Q3 and Q4 are switching elements that are turned on / off at the frequency of AC power.

Like the power factor improving device 10 of FIG. 1, the power factor improving device 10G also operates as a totem pole type power factor improving circuit, and can reduce common mode noise more than before by a simple configuration and control. can.

[Fifth Embodiment]
FIG. 27 is a block diagram showing the configuration of the power conversion device 100 according to the fifth embodiment. The power conversion device 100 includes a noise filter 13, a power factor improving device 10, and a DC / DC converter 14. The noise filter 13 is inserted between the AC power supply 11 and the power factor improving device 10 to remove normal mode noise. The power factor improving device 10 of FIG. 27 is configured in the same manner as the power factor improving device 10 of FIG. The DC / DC converter 14 is a voltage converter that converts the DC power output from the power factor improving device 10 into DC power having a predetermined voltage. The load device 15 operates with the DC power supplied from the DC / DC converter 14.

FIG. 28 is a block diagram showing the configuration of the power conversion device 100A according to the modified example of the fifth embodiment. The power conversion device 100 includes a noise filter 13, a power factor improving device 10, and an inverter 16. The inverter 16 is a voltage converter that converts the DC power output from the power factor improving device 10 into AC power having a predetermined voltage. The load device 17 operates with AC power supplied from the inverter 16.

The power factor improving devices 10, 10A to 10F according to the first to fourth embodiments have no effect of reducing normal mode noise. Therefore, as shown in FIGS. 27 and 28, both the common mode noise and the normal mode noise can be reduced by using the power factor improving device 10 and the noise filter 13 together.

The power conversion device 100 of FIG. 27 and the power conversion device 100A of FIG. 28 may include power factor improving devices 10A to 10F according to other modifications and embodiments in place of the power factor improving device 10 of FIG. ..

The output terminals OUT1 and OUT2 of the power factor improving devices 10 and 10A to 10F may be directly connected to the load device 15 without going through the DC / DC converter 14 or the inverter 16.

The power factor improving device according to one aspect of the present disclosure is a power factor improving device that operates as a totem pole type power factor improving circuit that converts AC power into DC power and outputs the power factor after improving the power factor. It is useful for realizing at low cost.

1,1G control circuit 10,10A-10G Power factor improvement device 11 AC power supply 12 Pseudo power supply network 13 Noise filter 14 DC / DC converter 15 Load device 16 Inverter 17 Load device 100, 100A Power conversion device Cin input capacitor Cout output capacitor C1 to C6 Parasitic capacitance C11 to C16 Capacitor D1, D2 Diode GND Conductor IN1, IN2 Input terminal L1, L2 Inductor N1, N2 Connection point OUT1, OUT2 Output terminal Q1 to Q4 Transistor

Claims (13)

A power factor improving device that converts AC power supplied to the first and second input terminals into DC power and improves the power factor to output from the first and second output terminals. The device is
An input capacitor connected between the first and second input terminals,
An output capacitor connected between the first and second output terminals,
A first and second switching element connected in series between the first and second output terminals and performing switching operation at a frequency higher than the frequency of the AC power.
With the third and fourth switching elements connected in series between the first and second output terminals and in parallel with the first and second switching elements and switching at the frequency of the AC power. ,
With the first and second inductors,
Equipped with a conductor part
The first inductor is connected between the first input terminal and a first connection point between the first and second switching elements and has a first inductance.
The second inductor is connected between the second input terminal and the second connection point between the third and fourth switching elements and has a second inductance.
The power factor improving device further
A first capacitance parallel to the first inductance,
A second capacitance parallel to the second inductance,
A third capacitance between the first connection point and the conductor portion,
A fourth capacitance between the second connection point and the conductor portion,
A fifth capacitance between the first output terminal and the conductor portion,
It has a sixth capacitance between the second output terminal and the conductor portion.
The first and second inductances and the first to sixth capacitances are
Z1: Z2 = Z3: Z4
Set to meet
Here, Z1 is the combined impedance of the first inductance and the first capacitance parallel to each other, Z2 is the combined impedance of the second inductance and the second capacitance parallel to each other, and Z3. Is the impedance of the third capacitance, and Z4 is the combined impedance of the fourth to sixth capacitances in parallel with each other.
Power factor improving device. The first capacitance includes a first parasitic capacitance generated between the windings of the first inductor.
The second capacitance includes a second parasitic capacitance generated between the windings of the second inductor.
The first and second parasitic capacitances are
Z1: Z2 = Z3: Z4
Set to meet,
The power factor improving device according to claim 1. The first capacitance includes the capacitance of the first capacitor connected in parallel with the first inductor.
The second capacitance includes the capacitance of the second capacitor connected in parallel with the second inductor.
The capacities of the first and second capacitors are
Z1: Z2 = Z3: Z4
Set to meet,
The power factor improving device according to claim 1 or 2. The third capacitance includes a third parasitic capacitance between the first connection point and the conductor portion.
The fourth capacitance includes a fourth parasitic capacitance between the second connection point and the conductor portion.
The fifth capacitance includes a fifth parasitic capacitance between the first output terminal and the conductor portion.
The sixth capacitance includes a sixth parasitic capacitance between the second output terminal and the conductor portion.
The third to sixth parasitic capacitances are
Z1: Z2 = Z3: Z4
Set to meet,
The power factor improving device according to any one of claims 1 to 3. The third capacitance includes the capacitance of the third capacitor connected between the first connection point and the conductor portion.
The capacity of the third capacitor is
Z1: Z2 = Z3: Z4
Set to meet,
The power factor improving device according to one of claims 1 to 4. The fourth capacitance includes the capacitance of the fourth capacitor connected between the second connection point and the conductor portion.
The capacity of the fourth capacitor is
Z1: Z2 = Z3: Z4
Set to meet,
The power factor improving device according to any one of claims 1 to 5. The fifth capacitance includes the capacitance of the fifth capacitor connected between the connection point of the first output terminal and the conductor portion.
The sixth capacitance includes the capacitance of the sixth capacitor connected between the connection point of the first output terminal and the conductor portion.
The capacities of the fifth and sixth capacitors are
Z1: Z2 = Z3: Z4
Set to meet,
The power factor improving device according to one of claims 1 to 6. A first resistor connected in parallel to the first inductor and
Further provided with a second resistor connected in parallel to the second inductor.
The power factor improving device according to any one of claims 1 to 7. The first and second inductors are electromagnetically coupled to each other so that the magnetic flux generated by the common mode currents flowing through the first and second inductors cancel each other out.
The first inductance includes the sum of the self-inductance of the first inductor and the mutual inductance of the first and second inductors.
The second inductance includes the sum of the self-inductance of the second inductor and the mutual inductance.
The first and second inductances and the mutual inductance are
Z1: Z2 = Z3: Z4
Set to meet,
The power factor improving device according to any one of claims 1 to 8. The first and second switching elements are transistors and
The third and fourth switching elements are diodes.
The power factor improving device according to one of claims 1 to 9. The first to fourth switching elements are transistors.
The power factor improving device according to one of claims 1 to 9. The power factor improving device according to one of claims 1 to 11.
Equipped with a noise filter that removes normal mode noise,
Power converter. The power factor improving device according to one of claims 1 to 11.
A voltage converter for converting DC power output from the power factor improving device into DC power or AC power having a predetermined voltage is provided.
Power converter.

Images