JP2021097514A - Control system of power conversion device - Google Patents

Abstract

To stably estimate a phase of an AC power source both in operation and non-operation of a power conversion device.SOLUTION: In a power conversion device configured to charge a battery by chopper operating a semiconductor switching element within one leg in a three phase inverter connected between positive and negative electrodes of a battery, a control block includes a current control block which calculates an output voltage instruction value V* by controlling a detection current Ichp under a chopper operation becomes a current amplitude instruction value Ichp*, a PLL block 50 which calculates a phase signal θ synchronized with a voltage of the AC power source on the basis of a detection signal (Vds) of the voltage of the semiconductor switching element within one leg during non-operation of the device, and on the basis of the output voltage instruction value V* before one calculation cycle during operation of the device, and a PWM block 60 which generates a gate signal for the semiconductor switching element of one leg on the basis of the phase signal θ, output voltage instruction value V*, and a carrier signal.SELECTED DRAWING: Figure 2

Description

The present invention relates to a control system of a power converter, for example, one leg of a three-phase inverter for driving a motor of an electric vehicle (a set of semiconductor switching elements for one phase of a semiconductor switching element connected by a three-phase bridge). The present invention relates to a technique for estimating the phase of an AC power supply for battery charging and applying PLL (Phase Locked Loop) without using a separate PT (Pontential Transformer, instrument transformer) or an insulating amplifier in a circuit that also serves as a battery charging circuit.

In electric vehicles, the space for mounting parts is limited, so it is necessary to reduce the number of parts as much as possible. In addition, since the weight greatly affects the cruising range, it is required to reduce the weight as much as possible.

FIG. 1 shows a circuit in which one leg of a three-phase inverter for driving a motor, which is proposed in Non-Patent Document 1, is also used as a battery charging circuit, and a diode is added to form a single-phase AC chopper for battery charging.

In FIG. 1, 10 is for driving a motor provided with semiconductor switching elements (FETs, IGBTs, etc., represented by FETs in the example of FIG. 1) Sa to Sf connected by a three-phase bridge between the positive and negative ends of the battery 11. It is a 3-phase inverter.

The AC output side of each of the three phases of the three-phase inverter 10 for driving the motor is connected to the motor 12.

Of the three-phase inverter 10 for driving a motor, one leg that outputs alternating current of any one phase, for example, semiconductor switching elements Sa and Sb connected in series, is used as a dual-purpose leg 10U as a part of the charging circuit of the battery 11. Also used.

A series circuit of diodes 13a and 13b is connected in parallel to the combined leg 10U. Reference numeral 14 denotes a single-phase AC power supply, and the output side of the single-phase AC power supply 14 is connected to the primary winding of the transformer 15.

The common connection point of the semiconductor switching elements Sa and Sb of the dual-purpose leg 10U is connected to one end of the secondary winding of the transformer 15 via the reactor 16, and the other end of the secondary winding of the transformer 15 is the diodes 13a and 13b. It is connected to a common connection point.

However, if the leakage inductance of the transformer 15 is sufficient, the common connection point of the semiconductor switching element Sa and Sb of the dual-purpose leg 10U is connected to one end of the secondary winding of the transformer 15 without providing the reactor 16. There is.

Therefore, the charging circuit of the battery 11 (single-phase AC chopper for battery charging) is composed of the single-phase AC power supply 14, the transformer 15, the reactor 16, the diodes 13a and 13b, and the combined leg 10U.

Resistors 17 and 18 acting as a semiconductor switching element voltage detection circuit are connected in series between both ends (drain and source) of the semiconductor switching element Sb of the lower arm of the combined leg 10U. The voltage divided by these resistors 17 and 18 is output as a Vds detection signal.

The current flowing through the reactor 16 is detected by the current transformer (CT) 19 and is output as a reactor current Ichp detection signal.

In the device configured as described above, the DC power of the battery 11 is converted into AC power by controlling the semiconductor switching elements Sa to Sf of the three-phase inverter 10 on and off by a control circuit (not shown). It is supplied to the motor 12.

Further, by controlling the on / off control of the semiconductor switching elements Sa and Sb of the dual-purpose leg 10U to operate the chopper, the battery 11 is operated from the single-phase AC power supply 14 via the transformer 15, the reactor 16, the diodes 13a and 13b and the dual-purpose leg 10U. Is charged.

In order to normally perform the charging operation using the circuit of FIG. 1, it is necessary to detect the phase of the single-phase AC power supply 14 and appropriately switch the dual-purpose leg 10U accordingly. However, when the phase is detected on the AC power supply side of the transformer 15, insulation is required, and additional parts such as a PT and an isolated amplifier are required. Since PTs and insulated amplifiers use magnetic materials, they lead to an increase in weight.

If voltage detection is performed on the AC chopper side of the transformer 15, insulation is not required. However, since large ripples and noise are superimposed on the detected voltage signal due to switching, it is difficult to detect the phase using this. A method of removing ripples by a filter can be considered, but it is necessary to compensate for the delay caused by the filter. Since the appropriate delay compensation amount varies depending on the frequency and it is necessary to use the phase to detect the frequency, for example, it is erroneously detected that the delay compensation amount is excessive and the phase is advanced, and as a result, the frequency is increased. Judging, the higher the frequency, the larger the delay, so the phase is further advanced by compensation, and as a result, the frequency is further increased, and the operation may become unstable.

Non-Patent Document 1 introduces a technique for estimating an AC power supply phase without using a voltage detector. In Non-Patent Document 1, the voltage command value output from the current controller is used instead of the voltage detection signal, and the AC power supply phase is estimated in consideration of the voltage drop in the power supply impedance. In this method, the device operates normally when it is in operation, but the phase cannot be estimated because the current control is stopped when the device is stopped. Therefore, the difference between the AC power supply voltage and the device output voltage becomes large immediately after the start of operation, and a large current may flow.

Further, Patent Document 2 proposes a method for estimating the phase of an AC power supply while the device is stopped. In Patent Document 2, since the stopped device is equivalent to a diode rectifier, the phase of the AC power supply is estimated based on the fact that the sign of the AC side current matches the sign of the AC voltage.

Takaharu Takeshita, Nobuyuki Matsui, "Single-Phase High Power Factor PWM Converter with Power Supply Phase Angle and Voltage Detector Removed", Institute of Electrical Engineers of Japan D, Vol. 113, No. 10, 1993, p1209 to p1215

Japanese Unexamined Patent Publication No. 2011-211889 Japanese Unexamined Patent Publication No. 2000-32760

In Patent Document 2, the condition for the AC side current to flow is limited to the case where the peak of the AC power supply voltage is larger than the battery voltage. If this condition is not met, such as when there is a certain amount of remaining battery power, the current becomes zero while the device is stopped, and the AC power supply phase cannot be estimated.

As a countermeasure, a method of connecting a resistor in parallel to any of the four arms constituting the AC chopper for charging the battery can be considered. However, when an HCT (Hall CT; Hall current detector) is used for current detection, an offset is likely to be superimposed on the HCT, and a change due to temperature also occurs. A current of about several A is required to accurately detect the current code, but if the value of the parallel resistance is reduced for that purpose, the loss increases.

On the other hand, when the three-phase inverter for driving the motor is equipped with a drain-source voltage Vds detector as shown in the resistors 17 and 18 in FIG. 1 for short-circuit failure detection of the switching element and dead time compensation. There is. As described above, the Vds detection signal during operation of the device is superposed with extremely large ripples and noise, which is inappropriate for phase detection.

The present invention solves the above problems, and an object of the present invention is to provide a control system for a power conversion device capable of stably estimating an AC power supply phase while the power conversion device is operating or stopped. It is in.

The control system for the power conversion device according to claim 1 for solving the above problems is
A semiconductor switching element is connected to the positive and negative ends of the battery in a three-phase bridge to form a three-phase inverter for driving the motor.
A set of semiconductor switching elements in one leg that outputs AC of any one phase of the three-phase inverter is also used as a part of the charging circuit of the battery, and is used as a set of semiconductor switching elements in the one leg. A single phase connected between a series circuit of a set of diodes connected in parallel, a common connection point of a set of diodes in the series circuit, and a common connection point of a set of semiconductor switching elements in the one leg. It is a power conversion device that constitutes a battery charging circuit with an AC power supply.
A semiconductor switching element voltage detection circuit that detects the voltage between both ends of the semiconductor switching element connected to the lower arm of the set of semiconductor switching elements in the one leg of the three-phase inverter.
A current control block that detects the current flowing through the reactor, controls the current to be the current amplitude command value, and calculates the output voltage command value.
One calculation calculated by the current control block during operation of the power conversion device based on a signal obtained by multiplying the detection voltage of the semiconductor switching element voltage detection circuit by the set gain G while the power conversion device is stopped. Based on the output voltage command value before the cycle, the PLL block that calculates the phase signal synchronized with the voltage of the single-phase AC power supply, and
Based on the output voltage command value calculated by the current control block, the carrier signal, and the phase signal calculated by the PLL block, the gate signal of a set of semiconductor switching elements in the one leg of the three-phase inverter is generated. The PWM block to be generated and
It is characterized by being equipped with.

The control system for the power conversion device according to claim 2 is claimed in claim 1.
The single-phase AC power supply is characterized in that it is connected via a reactor.

The control system of the power conversion device according to claim 3 is connected to the semiconductor switching element of the lower arm in the one leg of the three-phase inverter in the series circuit of the diode in claim 1 or 2. The feature is that a resistor is connected in parallel to the diode on the side.

The control system for the power conversion device according to claim 4 is the control system according to any one of claims 1 to 3.
An analog voltage detection signal is output from the semiconductor switching element voltage detection circuit, and the gain G in the PLL block is set to G = 2.

The control system for the power conversion device according to claim 5 is the control system according to any one of claims 1 to 3.
An analog voltage detection signal is output from the semiconductor switching element voltage detection circuit, and the gain G in the PLL block is set to G> 2.

The control system for the power conversion device according to claim 6 is the control system of the power conversion device according to any one of claims 1 to 3.
From the semiconductor switching element voltage detection circuit, a digital voltage detection signal is output, which is 1 when the voltage between both ends when the maximum current assumed when the semiconductor switching element is turned on is exceeded, and 0 when the voltage is less than that. The gain G in the PLL block is set to G = 2 / π.

The control system for the power conversion device according to claim 7 is the control system according to any one of claims 1 to 3.
From the semiconductor switching element voltage detection circuit, a digital voltage detection signal is output, which is 1 when the voltage between both ends when the maximum current assumed when the semiconductor switching element is turned on is exceeded, and 0 when the voltage is less than that. The gain G in the PLL block is set to G> 2 / π.

(1) According to the inventions of claims 1 to 7, when the power conversion device is stopped, the phase of the AC power supply voltage is detected from the detection signal of the semiconductor switching element voltage detection circuit, and therefore immediately after the operation. Overcurrent can be prevented. Since the output voltage command value calculated by the current control block is used during the operation of the power converter, it is not affected by the switching ripple, unlike the case where the detection signal of the semiconductor switching element voltage detection circuit is used. The AC power supply voltage phase can be estimated.

In addition, parts such as additional PTs (instrument transformers) and insulated amplifiers can be reduced, and the impact on cost and cruising range can be suppressed.
(2) According to the invention of claim 3, noise superposition on the detection signal can be suppressed. Further, as compared with the configurations of claims 1 and 2, the resistance value of the semiconductor switching element voltage detection circuit, for example, the resistance value of the voltage dividing resistor can be increased, so that loss can be suppressed and efficiency and cruising range can be improved. be able to.
(3) According to the inventions of claims 4 and 6, the PLL response speed of the PLL block can be made substantially equal between the operation and the stop of the power conversion device.
(4) According to the inventions of claims 5 and 7, the response speed of the PLL is improved only when the power converter is stopped while maintaining the stability of the PLL during operation, and the operation preparation is completed after the AC power is turned on. It is possible to shorten the time until. Further, the same effect as that of claims 1, 2 and 3 can be obtained by the same calculation load as those of claims 1, 2 and 3.

The block diagram of the power conversion apparatus to which this invention is applied. The block diagram of the control block according to the Example of Embodiment of this invention. The block diagram of the PLL block according to the Example of Embodiment of this invention. The main circuit block diagram of Example 3 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following examples of embodiments. The Vds detection signal output from the voltage dividing points of the resistors 17 and 18 acting as the semiconductor switching element voltage detection circuit in FIG. 1 is not suitable for phase detection because large ripples and noise are superimposed during device operation. However, if the device is stopped, switching is not performed and ripples and noise are very small.

Therefore, in the present invention, the phase of the AC power supply voltage is detected from the Vds detection signal while the device is stopped, and the phase of the AC power supply voltage is estimated based on the voltage command value output from the current control block during the operation of the device. It was configured as follows.

FIG. 2 shows the configuration of the control block according to the embodiment of the control system of the power conversion device of the present invention. The control block of FIG. 2 is applied to the main circuit configuration shown in FIG. 1 and the main circuit configuration of the third embodiment shown in FIG. 4 described later in the power conversion device.

In FIG. 2, FIG. 21 is an LPF (low-pass filter) that takes the reactor current Ichp detection signal output from the current transformer 19 of FIG. 1 as an input and removes noise, switching ripple, and the like from the Ichp.

Reference numeral 22 denotes a multiplier that multiplies the cosine value (cosθ) corresponding to the phase θ synchronized with the voltage of the single-phase AC power supply 14 calculated by the PLL block 50 described later with the set current amplitude command value Ichp ^*. is there. However, the cosine value (cosθ) is obtained by referring to the cosine value table 31 prepared in advance.

Reference numeral 23 denotes a subtractor that subtracts the output of the LPF 21 from the ^{instantaneous current amplitude command value Ichp *} cos θ, which is the output of the multiplier 22.

Reference numeral 24 denotes a P amplifier that inputs the output of the subtractor 23, applies a gain, and outputs a proportional value. The P amplifier 24 may be used in combination with a resonance amplifier whose gain becomes infinite with respect to the fundamental wave frequency.

Reference numeral 32 denotes a multiplier for obtaining the reference sine wave cosθ / Vdc by multiplying 1 / Vdc obtained by the reciprocal 33 from the battery voltage detection signal Vdc that detected the voltage of the battery 11 in FIG. 1 by the cosθ. Is.

^{Reference numeral 25 denotes a subtractor that outputs an output voltage command value V *} by subtracting the output of the P amplifier 24 from the reference sine wave cosθ / Vdc which is the output of the multiplier 32.

Reference numeral 34 denotes a buffer ^{that temporarily stores the output voltage command value V *} , which is the output of the subtractor 25, and outputs the output voltage command value V ^{* ′ one calculation cycle before.}

The LPF 21, multiplier 22, subtractors 23, 25 and P amplifier 24 control the reactor current detection signal Ichp so that it becomes the ^{instantaneous current amplitude command value Ichp *} cos θ, and calculate the ^{output voltage command V *.} It constitutes a block, and the output voltage command value V ^* is obtained by general current control.

That is, the deviation between the instantaneous current amplitude command value Ichp ^* cosθ and the reactor current detection value Ichp through the LPF 21 is amplified by the P amplifier 24, and the reference sine wave cosθ / Vdc (cosθ × battery detection voltage) is amplified by the subtractor 25. Subtract from the reciprocal 1 / Vdc).

Since the reactor current detection value Ichp is positive in the direction of input to the chopper, if the Ichp is insufficient, the chopper output voltage is lowered to promote an increase in Ichp.

Reference numeral 60 denotes a PWM block (PWM modulator), and 61b is a comparator that detects that cosθ, which is the output of the cosine value table 31, is positive. Only is compared with a value greater than zero (0.001).

Reference numeral 62 denotes a carrier generation unit that outputs a carrier triangular wave 1 that changes between 0 and 1. The carrier triangular wave 1 is subtracted from the ^{output voltage command value V * in the subtractor 63.}

The 64b is a comparator that outputs 1 if the subtraction output of the subtractor 63 is positive, that is, if the output voltage command value V ^* is larger than the carrier triangle wave 1.

Reference numeral 65 denotes an AND element for obtaining the logical product of the signal obtained by inverting the output of the comparator 64b and the output signal of the comparator 61b. The output of the AND element 65 becomes 1 when cos θ is positive and the output voltage command value V ^* is smaller than the carrier triangle wave 1, and is supplied as a gate command to the semiconductor switching element Sb of the lower arm of the combined leg 10U of FIG. ..

Reference numeral 61pa is a comparator that detects that cosθ, which is the output of the cosine value table 31, is negative. In the example of FIG. 2, the value is slightly smaller than zero (-0.001) for the purpose of adding a dead time. I'm comparing.

Reference numeral 66 denotes a carrier generation unit that outputs a carrier triangular wave 2 that changes between 0 and -1, and the carrier triangular wave 2 is subtracted ^{from the output voltage command value V *} by the subtractor 67.

The 64a is a comparator that outputs 1 if the subtraction output of the subtractor 67 is positive, that is, if the output voltage command value V ^* is larger than the carrier triangle wave 2.

Reference numeral 68 denotes an AND element for obtaining the logical product of the output signals of the comparator 64a and the comparator 61a. The output of the AND element 68 becomes 1 when cos θ is negative and the output voltage command value V ^* is larger than the carrier triangle wave 2, and is supplied as a gate command to the semiconductor switching element Sa of the upper arm of the combined leg 10U of FIG. ..

In the device of FIG. 1, when the AC power supply voltage of the single-phase AC power supply 14 is positive, it is necessary to switch the semiconductor switching element Sb of the lower arm of the dual-purpose leg 10U, and when it is negative, it is necessary to switch the semiconductor switching element Sa of the upper arm. .. Therefore, in the PWM block 60 of FIG. 2, when cosθ is positive, the output voltage command value V ^* is compared with the carrier triangle wave 1 to obtain the gate command (Sb), and when cosθ is negative, the output voltage command value V ^{* is obtained.} And the carrier triangle wave 2 are compared to obtain a gate command (Sa), which is input to the corresponding semiconductor switching element.

The PLL block 50 of FIG. 2 is configured as shown in FIG. The PLL block 50 is used from the Vds detection signal (the signal that detects the voltage between both ends (drain and source) of the semiconductor switching element Sb) detected by the voltage division of the resistors 17 and 18 in FIG. 1 and the buffer 34 in FIG. One of the output voltage command values V ^* ´ one calculation cycle before the output is input, and the phase signal θ synchronized with the voltage of the single-phase AC power supply 14 in FIG. 1 is calculated and output.

Reference numeral 51 denotes a multiplier for multiplying the Vds detection signal by the set gain G, and is set to G = 2 in the first embodiment.

^{52 selects 2Vds, which is the output of the multiplier 51, when the power converter is stopped, and V *} ′, which is the output of the buffer 34 in FIG. 2 when the power converter is in operation, one calculation cycle before. It is a switch that outputs.

Reference numeral 53 denotes a multiplier for obtaining the product of the output of the switch 52 and the sine wave sin θ output from the sine value table 58 described later, which is delayed by 90 deg with respect to the AC power supply voltage.

Reference numeral 54 denotes an LPF that extracts a DC component from the output of the multiplier 53.

Reference numeral 55 denotes a subtractor for obtaining the deviation between the output of the LPF 54 and the phase command value (set to zero).

Reference numeral 56 denotes a PI amplifier that inputs the output of the subtractor 55, multiplies the gain, adds the proportional value and the integrated value, and outputs the output. The output of the PI amplifier 56 corresponds to the angular frequency ω of the AC power supply voltage. ..

Reference numeral 57 denotes an integrator that integrates the angular frequency ω, which is the output of the PI amplifier 56, to obtain the phase signal θ. The phase signal θ output from the integrator 57 is input to the cosine value table 31 of FIG. 2 and input to the sine value table 58, and the sine value corresponding to the phase θ prepared in the sine value table 58 is obtained. Referenced, a sine wave sin θ delayed by 90 deg with respect to the AC power supply voltage is generated.

In the PLL block 50, the Vds detection signal is input while the device is stopped, and the output voltage command value V ^* ′ one calculation cycle before is input during operation, and the sine wave sinθ (output of the sine value table 58) deviated by 90 deg. Find the product. If the input is exactly 90 deg offset with respect to sin θ, then the DC component extracted by the LPF 54 from the output of the multiplier 53 is zero.

However, when the input is delayed with respect to θ and the phase shift from sin θ is less than 90 deg, the input contains an in-phase component with sin θ, so that the DC component becomes positive. Similarly, if the input advances, the output of the LPF 54 becomes negative. The deviation between the output of the LPF 54 and 0, which is the phase command value, is amplified by the PI amplifier 56. If the input is delayed, the angular frequency ω, which is the output of the PI amplifier 56, decreases, and the phase θ is also delayed. Synchronize with.

During operation of the apparatus, the output voltage command value V ^* ′ one calculation cycle before is used as the input signal of the PLL block 50. This is the same operation as in Patent Document 1. However, while Patent Document 1 estimates the phase of the power supply voltage with high accuracy, in the present invention, it is sufficient that the phase is accurate enough to prevent an abnormal current from flowing. Therefore, the PLL block 50 is simply simplified by ignoring the voltage drop of impedance. The configuration was made.

Further, in order to obtain a current waveform with small distortion, it is determined whether to switch the semiconductor switching element Sa or Sb in the dual-purpose leg 10U, not with the voltage phase of the single-phase AC power supply 14, but with the semiconductor switching element Sa. It is better to use the voltage phase at the common connection point of Sb. For that purpose, it is better to ignore the impedance voltage drop of the transformer 15 and the reactor 16, and in the present invention, the PLL having a simple configuration shown in FIG. 3 is suitable as compared with Patent Document 1.

When θ, which is the output phase of the PLL block 50, and the AC power supply phase deviate significantly, an abnormal current normally flows, but the abnormal current is suppressed by the control of the current control block, that is, the power supply voltage phase and the device. ^{The output voltage command value V *} is corrected so that the output voltage phases are aligned. By inputting the result to the PLL block 50 via the buffer 34, the phase signal θ can be synchronized with the AC power supply phase.

While the device is stopped, the Vds detection signal is used as the input signal of the PLL block 50. A multiplier 51 that doubles the gain G by G = 2 is added to the Vds detection signal, but when the AC power supply voltage is positive, the current is the Vds voltage dividing resistor (resistors 17 and 18) and the diode lower arm (diode). After passing through 13b), the Vds detection signal becomes a value proportional to the AC power supply voltage. When the AC power supply voltage is negative, there is no path through which the current flows, and the Vds detection signal is zero.

Therefore, the Vds detection signal has a half-wave rectified waveform, and the output of the LPF 54 is halved. On the other hand, since the output voltage command value V ^* ′ one calculation cycle before is a sinusoidal waveform, the output of the LPF 54 has a double difference. In order to remove this difference, Vds is doubled in advance in the multiplier 51 and input to the PLL block (50).

As described above, according to the first embodiment, since the AC power supply phase is detected from the Vds detection signal while the device is stopped, it is possible to prevent an overcurrent immediately after the operation. ^{During operation of the device, the output voltage command value V *} , which is the output of the current control block, is used instead of the Vds detection signal on which a very large switching ripple is superimposed, so that the AC is not affected by the switching ripple. The power supply phase can be estimated.

In addition, parts such as additional PTs and insulated amplifiers can be reduced, and the impact on cost and cruising range can be suppressed.

In the second embodiment, the gain G of the multiplier 51 of FIG. 3 (PLL block 50) is set to a value exceeding 2. In FIG. 3, since the phase command value input to the subtractor 55 is zero, setting the gain G of the multiplier 51 to G> 2 is equivalent to multiplying the gain of the PI amplifier 56 by G / 2.

As a result, the response speed of the PLL block 50 is improved only when the device is stopped, the synchronization with the AC power supply phase is completed quickly, and the time from when the AC power supply is turned on until the operation preparation is completed can be shortened. During the operation of the apparatus, the response speed of the PLL block 50 is reduced, and the stability can be maintained. Since the only change to the first embodiment is the value of the gain G, the effect of the second embodiment can be obtained with exactly the same calculation load as that of the first embodiment.

In the first embodiment, when the AC power supply voltage is positive, the current flows through the Vds voltage dividing resistor (resistors 17 and 18) and the lower arm (diode 13b) of the diode leg (series circuit of the diodes 13a and 13b), and the diode leg Since the lower arm is turned on, the potential on the AC side with respect to the negative terminal of the battery 11 is stable, and it is not easily affected by noise.

However, when the AC power supply voltage is negative, no current flows and all semiconductor switching elements are turned off. Therefore, the stability of the AC side potential with respect to the negative terminal of the battery 11 depends on the voltage dividing resistors 17 and 18 of Vds. When the potential fluctuates due to noise, noise is also superimposed on the Vds detection signal.

To stabilize the potential, the value of the Vds voltage dividing resistor (17, 18) may be reduced, but every time the semiconductor switching element Sa is turned on, a current flows through the voltage dividing resistor (17, 18) and a loss occurs. However, not only the efficiency during battery charging is reduced, but also the cruising range is affected.

Therefore, in the third embodiment, in order to stabilize the AC side potential when the AC power supply voltage is negative, a resistor 70 is added in parallel to the lower arm (diode 13b) of the diode leg as shown in FIG. In FIG. 4, the same parts as those in FIG. 1 are indicated by the same reference numerals.

With the configuration shown in FIG. 4, when the AC power supply voltage is negative, the current flows through the added resistor 70 and the antiparallel diode of the semiconductor switching element Sb, and the antiparallel diode of the semiconductor switching element Sb is turned on. The AC side potential is stable.

Therefore, the Vds detection signal is less susceptible to noise. In the third embodiment, the number of parts increases by one resistor as compared with the first embodiment, but it is sufficient that a current of several mA flows through the resistor, and a parallel resistor added to the diode leg lower arm (diode 13b). Both the 70 and the Vds voltage dividing resistance (17, 18) can increase the resistance value, reduce the loss, and suppress the influence on the cruising range.

In the above configuration, it is assumed that the Vds detection signal is analog. However, even if Vds detection is digital and the voltage between the drain and source when the maximum current assumed when the semiconductor switching element Sb is turned on is exceeded, it is input as 1, and if it is less than that, it is input as 0. Can be applied.

At this time, the Vds detection signal when the device is stopped has a rectangular wave-like waveform of 1 if the AC power supply voltage is positive, and 0 otherwise, and the amplitude of the fundamental wave component is π / 2. Since the output voltage command value V ^* ´ before one calculation cycle is a sine wave with a maximum amplitude of 1, if the gain G of the multiplier 51 is set to G = 2 / π, the PLL response speeds during operation and stop are almost equal. be able to.

When Vds detection is digital and Example 2 is applied, the gain G of the multiplier 51 is specified as G> 2 / π.

10 ... 3-phase inverter 10U ... Combined leg 11 ... Battery 12 ... Motor 13a, 13b ... Diode 14 ... Single-phase AC power supply 15 ... Transformer 16 ... Reactor 17, 18, 70 ... Resistor 19 ... Current transformer 21, 54 ... LPF
22, 32, 51, 53 ... Multiplier 23, 25, 55, 63, 67 ... Subtractor 24 ... P amplifier 31 ... Cosine value table 33 ... Divider 34 ... Buffer 50 ... PLL block 52 ... Switch 56 ... PI amplifier 57 ... Integrator 58 ... Sine value table 60 ... PWM block 61a, 61b, 64a, 64b ... Comparator 62, 66 ... Carrier generator 65, 68 ... AND element Sa to Sf ... Semiconductor switching element

Claims (7)

A semiconductor switching element is connected to the positive and negative ends of the battery in a three-phase bridge to form a three-phase inverter for driving the motor.
A set of semiconductor switching elements in one leg that outputs AC of any one phase of the three-phase inverter is also used as a part of the charging circuit of the battery, and is used as a set of semiconductor switching elements in the one leg. A single phase connected between a series circuit of a set of diodes connected in parallel, a common connection point of a set of diodes in the series circuit, and a common connection point of a set of semiconductor switching elements in the one leg. It is a power conversion device that constitutes a battery charging circuit with an AC power supply.
A semiconductor switching element voltage detection circuit that detects the voltage between both ends of the semiconductor switching element connected to the lower arm of the set of semiconductor switching elements in the one leg of the three-phase inverter.
A current control block that detects the current flowing through the reactor, controls the current to be the current amplitude command value, and calculates the output voltage command value.
One calculation calculated by the current control block during operation of the power conversion device based on a signal obtained by multiplying the detection voltage of the semiconductor switching element voltage detection circuit by the set gain G while the power conversion device is stopped. Based on the output voltage command value before the cycle, the PLL block that calculates the phase signal synchronized with the voltage of the single-phase AC power supply, and
Based on the output voltage command value calculated by the current control block, the carrier signal, and the phase signal calculated by the PLL block, the gate signal of a set of semiconductor switching elements in the one leg of the three-phase inverter is generated. The PWM block to be generated and
A control system for a power converter, which is characterized by being equipped with. The control system for a power conversion device according to claim 1, wherein the single-phase AC power supply is connected via a reactor. Claim 1 or 2 of the series circuit of the diodes, wherein a resistor is connected in parallel to the diode on the side connected to the semiconductor switching element of the lower arm in the one leg of the three-phase inverter. The control system of the power converter described in. The invention according to any one of claims 1 to 3, wherein an analog voltage detection signal is output from the semiconductor switching element voltage detection circuit, and the gain G in the PLL block is set to G = 2. Power converter control system. The invention according to any one of claims 1 to 3, wherein an analog voltage detection signal is output from the semiconductor switching element voltage detection circuit, and the gain G in the PLL block is set to G> 2. Power converter control system. From the semiconductor switching element voltage detection circuit, a digital voltage detection signal is output, which is 1 when the voltage between both ends when the maximum current assumed when the semiconductor switching element is turned on is exceeded, and 0 when the voltage is less than that. The control system for a power conversion device according to any one of claims 1 to 3, wherein the gain G in the PLL block is set to G = 2 / π. From the semiconductor switching element voltage detection circuit, a digital voltage detection signal is output, which is 1 when the voltage between both ends when the maximum current assumed when the semiconductor switching element is turned on is exceeded, and 0 when the voltage is less than that. The control system for a power conversion device according to any one of claims 1 to 3, wherein the gain G in the PLL block is set to G> 2 / π.

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