JP2018133892A - Gate driving device and gate driving method of power semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide means for suppressing deterioration of a power semiconductor to prolong life of the power semiconductor, and preventing size increase of a device while maintaining reliability by controlling time for applying voltage lower than a source potential to a gate of the power semiconductor.SOLUTION: A signal for fixed time is output to a gate output circuit 102 by controlling gate voltage 113 to be applied to a gate of a power semiconductor 32 to first voltage when an on command of the gate is received, controlling the gate voltage to second voltage when an off command of the gate is received by the gate output circuit 102, monitoring the gate voltage to determine on/off states of the power semiconductor 32 by an on/off state determination circuit 103, and detecting determination of the off state to be output by the on/off state determination circuit 103 by a timer circuit 104. The gate output circuit 102 controls the gate voltage to third voltage lower than the second voltage while the signal for fixed time is input.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power semiconductor gate driving device and a gate driving method used in a power conversion device such as an inverter, a converter, or a DC chopper circuit.

  Power semiconductor devices such as IGBTs are widely used in power converters such as inverters that convert DC power into AC power, converters that convert AC power into DC power, or DC chopper circuits that boost or reduce DC voltage. . This power semiconductor element is driven by an on / off signal from a gate driving device. The gate driving device is controlled by a signal from a control logic unit that is a controller of the power conversion device.

As an example of using a gate drive device, FIG. 2 shows the overall configuration of a two-level inverter used as a railway vehicle power converter.
The power conversion device 4 includes a control logic unit 11, gate drive devices 21 to 26, a signal line 12 that connects the control logic unit 11 and the gate drive devices 21 to 26, and power semiconductors 31 to 36. The positive power line is connected to the overhead line via the pantograph 1, and the negative power line is connected to the rail via the wheel 6. The filter reactor 2 and the filter capacitor 3 are provided so that a track circuit (not shown) that operates at several tens of Hz does not malfunction due to an induction failure caused by the operation of the power converter 4. Moreover, the circuit breaker 7 is provided in order to interrupt the power source and protect the power converter 4 when an overcurrent and an overvoltage occur.

  Next, operation | movement of the power converter device 4 is demonstrated. Based on the on / off command of the power semiconductors 31 to 36 transmitted from the control logic unit 11, the gate driving devices 21 to 26 apply a positive voltage to the gate with respect to the source in the case of an on command, Outputs a negative voltage to the gate relative to the source. The power semiconductors 31 to 36 repeat conduction / non-conduction in accordance with the voltage output from the gate drive devices 21 to 26 to convert the DC power supplied from the overhead line into AC power of a pulse train, and thus the AC motor 5 is driven.

  In recent years, the demand for higher efficiency and lower loss of power conversion devices has increased in the great social trend of reducing environmental impact. As a method to meet this demand, power converters using power semiconductors composed of silicon carbide (SiC) or gallium nitride (GaN) with a large band cap are becoming popular in place of conventional silicon power semiconductor elements. . In these power semiconductors with a large band gap, the withstand voltage is about 10 times that of a silicon power semiconductor, so that the thickness of the semiconductor chip can be reduced to about 1/10. For this reason, the resistance during conduction is reduced to about 1/10, and the conduction loss can be reduced.

JP 2013-219874 A

  In order to satisfy the demand for higher efficiency and lower loss of the power converter, when using the above-described power semiconductor composed of SiC, the SiC MOS gate type power semiconductor is in an off state in which a negative voltage is output to the gate. When a voltage lower than a predetermined voltage is applied for a long time, there is a problem that the threshold value is shifted to the negative side. For example, in the case of a SiC MOSFET having a threshold value of 4V, the threshold value is reduced by 1V to 3V due to a long negative bias. When the threshold value shifts to the negative side, the diode of the arm that forms a pair of inverters also changes the gate voltage due to the steep fluctuation of the drain voltage when reverse recovery is performed, and the MOSFET is turned on incorrectly, so that the SiC power semiconductors of the upper and lower arms There is a risk of the element shorting the arm (a phenomenon that turns on simultaneously). Since the shift of the gate voltage increases depending on the magnitude of the negative bias of the gate, it is desirable to use the negative bias as small as possible. However, if the negative bias is small, the risk of erroneous turn-on increases when the gate voltage fluctuates during the above-described recovery, so it cannot be simply reduced. As a countermeasure against this, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2013-219874) discloses a technique for reducing the above-described threshold shift problem by reducing the negative bias voltage only during recovery.

  Also, when the voltage to be converted is as high as 600 to 3000 V, such as a railway power converter, it operates by connecting it to a control logic unit that operates at a low voltage and a high-voltage main circuit in order to ensure device reliability. Signal transmission between the gate driving devices to be operated and between the gate driving devices paired by the upper and lower arms needs to be performed through an insulating element such as an optical fiber or a photocoupler.

  In the technique disclosed in Patent Document 1 described above, the negative bias voltage is made lower than usual by using an ON command of one of the upper and lower arms as a trigger. However, in this method, in addition to the on / off command transmitted between the control logic unit and the gate drive device, the gate drive of the arm paired with the control logic unit and the gate drive device or one of the gate drive devices is performed. A new means for transmitting an on / off command between apparatuses is required. For this reason, it is necessary to newly provide a signal transmission / reception circuit composed of a signal line, an insulating element, and the like, and there is a problem that the apparatus becomes large.

  The gate output circuit controls the gate voltage applied to the gate of the power semiconductor to the first voltage when receiving a gate on command, and to the second voltage when receiving a gate off command, and an on / off state determination circuit. Thus, the gate voltage is monitored to determine the on / off state of the power semiconductor, and the timer circuit detects the off state determination output from the on / off state determination circuit, thereby outputting a signal for a predetermined time to the gate output circuit. The gate output circuit controls the gate voltage to a third voltage lower than the second voltage while inputting a signal for a predetermined time.

  According to the present invention, the negative bias is applied only at the time of recovery without newly adding a signal transmission path through the insulating element between the control logic unit and the gate driving device and between the gate driving device of the arm paired with the gate driving device. Therefore, it is possible to provide a highly reliable and small-sized power conversion device that does not increase the size of the device while suppressing deterioration of the power semiconductor element.

FIG. 1 is a block diagram showing a configuration of a first embodiment of a gate driving apparatus according to the present invention. FIG. 2 is a diagram showing an overall configuration diagram of a two-level inverter used as a railway vehicle power converter. FIG. 3 is a diagram illustrating a specific configuration example of the gate output circuit according to the first embodiment. FIG. 4 is a time chart illustrating an operation mode during recovery according to the first embodiment. FIG. 5 is a diagram showing the configuration of a second embodiment of the gate driving apparatus according to the present invention. FIG. 6 is a time chart illustrating an operation mode during recovery according to the second embodiment. FIG. 7 is a diagram showing a configuration of a third embodiment of the gate driving apparatus according to the present invention. FIG. 8 is a time chart when the gate voltage is lowered to Vss2b after turn-off in the third embodiment. FIG. 9 is a time chart when the gate voltage is not lowered to Vss2b after the turn-off in the third embodiment. FIG. 10 is a diagram showing a configuration of a fourth embodiment of the gate driving apparatus according to the present invention. FIG. 11 is a diagram illustrating a current detection circuit that is a component of the fourth embodiment. FIG. 12 is a diagram illustrating a time chart when the gate voltage is lowered to Vss2b after the turn-off in the fourth embodiment. FIG. 13 is a time chart when the gate voltage is not lowered to Vss2b after the turn-off in the fourth embodiment. FIG. 14 is a diagram showing a time chart in the case where the turn-on time of the pair arm is predicted after the turn-off and the gate voltage is lowered to Vss2b only for the necessary minimum time.

  As modes for carrying out the present invention, first to fourth embodiments of a gate driving device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a first embodiment of a gate driving apparatus according to the present invention. The first embodiment has a function of reducing the negative bias voltage only at the time of recovery.
The gate drive device 22 receives the gate command level conversion circuit 101 for converting the level of the gate on / off command 111, the gate on / off command LIN (112) level-converted by the gate command level conversion circuit 101, and the output of the timer circuit 104. A gate output circuit 102 for outputting the gate output voltage LO1 (113) to the gate of the power semiconductor element; an on / off state determination circuit 103 for determining the state of the gate of the power semiconductor element from the gate voltage monitoring signal 114 by the gate output circuit 102; The timer circuit 104 is configured to drive the timer circuit output N1 (117) for a predetermined time by the feedback signal LFB (115) which is the output of the on / off state determination circuit 103.

  In the gate driving device 22, the gate on / off command 111 output from the control logic unit 11 is input to the gate command level conversion circuit 101 via an insulating element (not shown). The on / off command 111 is a gate on / off command LIN (112) level-converted to an amplitude level that can drive the SiC power semiconductor 32 by the gate command level conversion circuit 101. The gate output circuit (102) outputs the gate voltage LO1 (113) based on the received gate on / off command LIN (112) to the base of the SiC power semiconductor 32.

  The gate voltage monitoring signal 114 output from the gate output circuit 102 is compared with the reference voltage by the on / off state determination circuit (103). If the reference voltage is equal to or higher than the reference voltage, the feedback signal LFB (115) is output as the on signal. If it is below the reference voltage, the feedback signal LFB (115) is output as an off signal. The feedback signal 116 whose level has been converted by the gate command level conversion circuit (101) is transmitted to the control logic unit (11).

  When the control logic unit 11 and the gate driving device 22 are connected by an optical fiber, the gate command level conversion circuit 101 only converts the amplitudes of the gate command 111 and the feedback signal 115. On the other hand, when the control logic unit 11 and the gate drive device 22 are connected by an electric wire, the control logic unit 11 driven at a low voltage is insulated from the SiC power semiconductor 32 driven at a high voltage and the gate output circuit 102. The gate command level conversion circuit 101 is provided.

  A feature of the first embodiment is that the feedback signal LFB (115) is used as a trigger to lower the negative bias voltage at the time of recovery from the normal off voltage and return the negative bias voltage to the normal off voltage after the recovery ends. It is in. This makes it possible to reduce the negative bias of the gate only at the time of recovery without the on / off information from the pair arm.

  FIG. 3 is a diagram illustrating a specific configuration example of the gate voltage output circuit 102 according to the first embodiment. The gate voltage output circuit 102 includes three MOS transistors 121, 122 and 123, gate resistors 131 and 132 for controlling the switching characteristics of the SiC power semiconductor 32, bias resistors 133 and 134 for turning on the MOS transistor 123, In addition, a negative bias switching comparator 141 that compares the output N1 (117) of the timer circuit 104 with the reference voltage Vref is configured.

  When the gate command 112 is on, the MOS transistor 121 is turned on and the gate output voltage LO1 (113) becomes the positive bias voltage VDD2, and when the gate command 112 is off, the MOS transistor 122 is turned on and the gate output The voltage LO1 (113) becomes the negative bias voltage VSS2a. In FIG. 3, the transistors 121 to 123 are MOS transistors. However, it is obvious that the same effect can be obtained even when the transistors are bipolar transistors.

  Next, the operation mode at the time of recovery will be described using the time chart of FIG. FIG. 4 is a diagram showing operation waveforms of respective parts in a state where current flows from the inverter side to the load side. As signals shown for the first time in FIG. 4, HIN is the upper arm gate on / off command, VgsH is the upper arm gate voltage, HFB is the upper arm feedback signal, VdsL is the lower arm drain-source voltage, and IdL is the lower arm signal. The drain current is shown, and the case where the current flows from the drain to the source is positive.

  When the lower arm gate on / off command LIN (112) becomes L level by the gate off command, the gate voltage VgsL (113) changes from the positive bias voltage VDD2 to the negative bias voltage VSS2a, but constitutes a power semiconductor. Since the current flows through the free wheel diode connected in reverse parallel with the MOSFET, the drain voltage VdsL and the drain current IdL of the lower arm do not change. In this state, a motor current flows from the power conversion device 4 toward the AC motor 5, and in the SiC power semiconductor 32 of the lower arm, a current flows in a freewheel diode that is antiparallel, not a MOSFET that constitutes the power semiconductor. It is. However, when the gate voltage VgsL (113) becomes the negative bias voltage VSS2a, it is determined that the on / off state determination circuit 103 in the gate driver 22 is turned off, and the feedback signal LFB (115) is in the H level of the turn-off state. The signal changes. When the feedback signal LFB (115) changes to H level, the timer circuit 104 operates and outputs a signal N1 (117) that becomes H level for a certain time Td.

  When the H level of the signal N1 (117) becomes higher than Vref, the output of the comparator 141 (FIG. 3) changes from the L level to the H level, and the MOS transistor 123 is turned on. As a result, the negative bias voltage of the gate output voltage LO1 (113) decreases from VSS2a to VSS2b. When the SiC power semiconductor 31 of the upper arm is turned on, the SiC power semiconductor 32 of the lower arm is reverse-recovered, and the gate voltage VgsL (113) of the lower arm rises momentarily due to a sudden change in the drain voltage VdsL. However, since the gate voltage VgsL is lowered to VSS2b, it does not reach the threshold value of the MOSFET constituting the power semiconductor, and the MOSFET constituting the power semiconductor is not erroneously turned on. When the recovery operation is completed and a time Td when the output N1 (117) of the timer circuit 104 is at the H level has elapsed, the output of N1 (117) becomes the L level and becomes lower than Vref. As a result, the comparator 141 is turned off, and the negative bias voltage of the gate output voltage LO1 (113) returns to VSS2a.

  According to the first embodiment, as described above, a simple system configuration prevents erroneous firing at the time of recovery, prevents shift of the threshold value Vth, suppresses deterioration of the power semiconductor element, and reduces the lifetime of the element. Makes it possible to extend Thereby, the enlargement of the gate driving device can be prevented while maintaining reliability.

  In the above-described configuration, for example, the normal off-time voltage VSS2a is -5V, and the time Td for the timer circuit 104 to output the H level is the output of the gate output circuit 102 of the counter arm after the output of the gate output circuit 102 changes. It is about 5 μs to 10 μs determined by the sum of the dead time and the recovery time until the change. Only during this period, the negative bias voltage VSS2b is lowered to -10V. However, in an environment where the influence of noise is extremely small, degradation of the SiC power semiconductor element can be further suppressed by setting VSS2a to 0V and VSS2b to -3V.

  In the above description, the SiC power semiconductor has been described as an example. However, when a negative bias is applied for a long time, the threshold voltage Vth of the power semiconductor element shifts to the negative side and is effective for all power semiconductor elements that deteriorate.

  FIG. 5 is a diagram showing the configuration of a second embodiment of the gate driving apparatus according to the present invention. The difference from the configuration of the first embodiment shown in FIG. 1 is that the gate drive device 22 is not provided with the on / off state determination circuit 103 and does not have a function of transmitting the on / off state feedback signal 116 to the control logic unit 11. is there. For this reason, as shown in the time chart of FIG. 6, when detecting that the lower arm gate on / off command LIN (112) is turned off, the timer circuit 104 unconditionally becomes the signal N1 (117) that is at the H level for a certain time Td. ) Is output.

  The feature of the second embodiment is that the negative bias voltage is lowered only at the time of recovery only by the signal of the gate driving device 22 even in the simple system configuration in which the feedback signal 116 is not transmitted to the control logic unit 11 which is the host controller. It is possible to do.

  FIG. 7 is a diagram showing a configuration of a third embodiment of the gate driving apparatus according to the present invention. The difference from the configuration of the first embodiment shown in FIG. 1 is that a function for monitoring the drain voltage is added to the gate driving device 22, and a drain voltage determination circuit 105 and a timer measurement start circuit 106 using an AND function are added as components. It is a point. The operation mode of the third embodiment will be described below with reference to the time charts of FIGS.

  FIG. 8 is a time chart when the SiC power semiconductor 32 of the lower arm recovers. When the lower arm gate on / off command LIN (112) from the control logic unit 11 is turned off, the gate output voltage LO1 (113) decreases to VSS2a, but the drain-source voltage VdsL and the drain current IdL do not change. In this state, a motor current flows from the power conversion device 4 toward the AC motor 5, and in the SiC power semiconductor 32 of the lower arm, a current flows in a freewheel diode that is antiparallel, not a MOSFET that constitutes the power semiconductor. It is. Therefore, even if the gate output voltage changes from the positive bias voltage VDD2 to the negative bias voltage VSS2a, the operation mode (drain-source voltage VdsL and drain current IdL) does not change.

  In this mode, the drain voltage determination circuit 105 detects that the drain-source voltage VdsL (118) does not change even if the feedback signal LFB (115) detects the turn-off state. As a result, the drain voltage determination circuit 105 outputs the H level drain voltage Low level detection signal 119, and the timer measurement start circuit 106 performs an AND operation with the feedback signal LFB (115) and inputs it to the timer circuit 104. An H level signal is output from the timer circuit 104 for a predetermined time Td, and the negative bias voltage of the gate output voltage LO1 (113) is lowered to VSS2b.

  Next, FIG. 9 is a diagram showing a time chart when the SiC power semiconductor 32 of the lower arm is not recovered. The difference from the time chart of FIG. 8 is that the motor current flows from the AC motor 5 toward the power converter 4 in FIG. 2 (regenerative mode). In this mode, when the lower arm gate command is turned off, the gate output voltage LO1 (113) decreases to VSS2a, the drain-source voltage VdsL increases, and the drain current IdL decreases. At this time, the drain voltage determination circuit 105 detects an increase in VdsL, outputs an L level drain voltage Low level detection signal 119, and does not operate the timer circuit 104. For this reason, the gate output voltage LO1 (113) remains VSS2a.

  As described above, the feature of the third embodiment is that the negative bias voltage that causes the threshold shift is not lowered to VSS2b in the mode in which the recovery operation is not performed, so that the power semiconductor element can be further prevented from deteriorating.

  In the above time chart, it is assumed that the change in the feedback signal LFB (115) is slower than the change in VdsL, but the reverse case may be possible. In this case, the drain voltage determination circuit 105 determines the state of the drain-source voltage VdsL after a fixed time has elapsed from the change of the feedback signal LFB (115), and outputs the drain voltage Low level detection signal 119, and the timer circuit The operation of 104 is determined. Thereby, even when the change of the feedback signal LFB (115) is faster than the change of VdsL, the gate output voltage LO1 (113) can be controlled as described above, and the deterioration of the power semiconductor element can be further prevented. it can.

  FIG. 10 is a diagram showing a configuration of a fourth embodiment of the gate driving apparatus according to the present invention. A difference from the configuration of the first embodiment shown in FIG. 1 is that a function for monitoring an electromotive voltage generated in the source parasitic inductance 151 when a current flows through the SiC power semiconductor is added to the gate driving device 22. A current measurement circuit 150 and a timer measurement start circuit 106 using an AND function are added.

  In the fourth embodiment, the source current IsL of the SiC power semiconductor 32 can be monitored by detecting the electromotive voltage generated in the source parasitic inductance 151 by the current detection circuit 150. When the current detection circuit 150 detects a change in the source current IsL, the current detection circuit 150 outputs a turn-off detection signal 153, ANDs the feedback measurement signal LFB (115) by the timer measurement start circuit 106, and outputs a negative bias voltage switching command 120 to the timer circuit 104. To enter.

  As shown in the time chart of FIG. 12, after the SiC power semiconductor 32 of the lower arm receives the turn-off command by the gate-off command from the control logic unit 11, it is determined that recovery occurs when the source current IsL does not change. The negative bias VSS2b is applied for a certain period. Thereby, the gate voltage of SiC power semiconductor 32 is prevented from being raised and erroneously ignited.

  On the other hand, as shown in the time chart of FIG. 13, after the SiC power semiconductor 32 of the lower arm receives the turn-off command by the gate-off command from the control logic unit 11, the source current IsL changes (the AC motor 5 of FIG. 2). When the motor current flows from the power converter 4 toward the power converter 4 (regeneration mode), it is determined that no recovery occurs, and the SiC power semiconductor 32 functions so as not to apply the negative bias VSS2b. Thereby, deterioration of SiC power semiconductor 32 can be suppressed.

  FIG. 11 is a diagram illustrating a basic configuration example of the current detection circuit 150. The current detection circuit 150 detects a current by utilizing an electromotive voltage of V = Ldi / dt (V is a voltage, L is an inductance, and i is a current) due to a current change. The circuit configuration shown in FIG. 11 suppresses the influence of noise and prevents malfunction.

As described above, in the fourth embodiment, when the electromotive voltage generated in the source parasitic inductance is used, the negative bias time can be controlled by the same mechanism even if the electromotive voltage generated in the drain parasitic inductance is used.
Also, the negative bias time can be controlled by a similar mechanism by using a method of capturing a current change of the SiC power semiconductor 32 by using an insulated current / voltage conversion component such as a current transformer or a Rogowski coil. Since the current transformer, the Rogowski coil, etc. are insulated, the size of the gate driving device is not greatly affected.

  Next, a method for further suppressing the deterioration of the SiC power semiconductor will be described with reference to FIG. The shorter the time during which the negative bias VSS2b is applied to the gate voltage, the more the threshold voltage change that leads to deterioration of the SiC power semiconductor can be suppressed. For this purpose, it is desirable to make the negative bias time as short as possible. In order to realize this, the time (dead time) during which the on / off command HIN to the gate of the upper arm changes after the on / off command LIN (102) to the gate of the lower arm changes is made constant. Thus, the gate driving device 22 can predict the timing at which recovery occurs. That is, the negative bias is not applied after the feedback signal LFB (115) is changed, but the negative bias is applied for a shorter time by adjusting the timing by the timer circuit 104 to the timing when recovery occurs. To. This method can be applied to all the first to fourth embodiments described above.

1 ... pantograph, 2 ... filter reactor, 3 ... filter capacitor,
4 ... Power converter, 5 ... AC motor, 6 ... Wheel,
11: Control logic unit, 12 ... Control command signal line,
21 ... U layer upper arm gate driver, 22 ... U layer lower arm gate driver,
23 ... V layer upper arm gate driver, 24 ... V layer lower arm gate driver,
25 ... W layer upper arm gate driver, 26 ... W layer lower arm gate driver,
31 ... U-layer upper arm SiC power semiconductor, 32 ... U-layer lower arm SiC power semiconductor,
33 ... V layer upper arm SiC power semiconductor, 34 ... V layer lower arm SiC power semiconductor,
35 ... W layer upper arm SiC power semiconductor, 36 ... W layer lower arm SiC power semiconductor,
101 ... Gate command level conversion circuit, 102 ... Gate voltage output circuit,
103 ... ON / OFF state determination circuit, 104 ... Timer circuit,
105 ... Drain voltage determination circuit, 106 ... Timer measurement start circuit,
111 ... ON / OFF command received from the control logic unit,
112... Level-converted gate on / off command LIN,
113: Gate output voltage LO1, 114: Gate voltage monitoring signal,
115 ... feedback signal LFB, 116 ... feedback signal to be transmitted to the control logic unit,
117: Timer circuit output N1, 118 ... Drain-source voltage detection signal,
119: Drain voltage low level detection signal, 120: Negative bias voltage switching command,
121, 122, 123 ... MOS transistor, 131, 132 ... gate resistance,
133, 134: bias resistor, 141 negative bias switching comparator 150: current detection circuit, 151: source parasitic inductance,
152 ... Electromotive voltage detection signal due to source parasitic inductance, 153 ... Turn-off detection signal

Claims (12)

A gate driving device that controls a gate voltage of a power semiconductor in response to a gate on command or a gate off command from a control logic unit,
The gate voltage applied to the gate of the power semiconductor is controlled to a first voltage when the on command is received, and is controlled to a second voltage when the off command is received;
A timer circuit that outputs a signal of a predetermined time to the gate output circuit by detecting the off command;
The gate output device, wherein the gate output circuit controls the gate voltage to a third voltage lower than the second voltage while the signal of the predetermined time is input. The gate driving device according to claim 1,
An on / off state determination circuit for monitoring the gate voltage and determining an on / off state of the power semiconductor;
The timer circuit outputs a signal of the predetermined time to the gate output circuit by detecting a determination of an off state output from the on / off state determination circuit instead of the off command. apparatus. The gate driving device according to claim 2,
A main terminal voltage determining circuit that detects a voltage of one main terminal from a pair of main terminals of the power semiconductor and determines whether the detected voltage changes after the power semiconductor is turned off;
The timer circuit detects the OFF state determination output from the ON / OFF state determination circuit and the determination that the detection voltage output from the main terminal voltage determination circuit does not change, thereby generating a signal for the predetermined time. A gate driving device for outputting to the gate output circuit. The gate driving device according to claim 2,
A voltage generated between one main terminal and one auxiliary terminal on the one main terminal side is detected from a pair of main terminals and a pair of auxiliary terminals of the power semiconductor, and a change in the main current of the power semiconductor is detected. A current determination circuit for determining presence or absence;
The timer circuit detects the off state determination output from the on / off state determination circuit and the determination that the main current output from the current determination circuit does not change, and thereby outputs the signal for the predetermined time to the gate. A gate driving device that outputs to an output circuit. The gate drive device according to any one of claims 1 to 4,
The gate driving device drives a power conversion device configured to include the power semiconductor in an upper arm and a lower arm,
The timer circuit adjusts the timing of outputting the signal of the predetermined time to the gate output circuit in a state where the dead time associated with on / off of each power semiconductor included in the upper arm and the lower arm is constant. A gate driving device characterized by that. A gate driving device according to any one of claims 1 to 5,
The gate driving device, wherein the power semiconductor is a semiconductor made of silicon carbide (SiC). A gate driving method for controlling a gate voltage of a power semiconductor,
When an ON command is applied to the gate of the power semiconductor, the gate voltage of the power semiconductor is controlled to a first voltage,
When an off command is applied to the gate of the power semiconductor, the gate voltage is controlled to a second voltage, and when the off command is detected, the gate voltage is lower than the second voltage for a certain time. A gate driving method characterized by controlling to three voltages. The gate driving method according to claim 7, wherein
Monitoring the gate voltage to determine the on / off state of the power semiconductor;
When the on / off off state is determined instead of detecting the off command, the gate voltage is controlled to the third voltage lower than the second voltage for the predetermined time. A gate driving method characterized by the above. The gate driving method according to claim 8, wherein
By detecting the voltage of one main terminal from a pair of main terminals possessed by the power semiconductor, it is determined whether the detected voltage changes after the power semiconductor is turned off,
The gate voltage is controlled to the third voltage lower than the second voltage for the certain period of time by determining the off state and determining that the detection voltage does not change. To drive the gate. The gate driving method according to claim 8, wherein
The main current of the power semiconductor changes by detecting a voltage generated between one main terminal and the auxiliary terminal on the one main terminal side from a pair of main terminals and a pair of auxiliary terminals included in the power semiconductor. Whether or not
The gate voltage is controlled to the third voltage lower than the second voltage for the certain time by determining the off state and determining that the main current does not change. To drive the gate. A gate driving method according to any one of claims 7 to 10, wherein
By the gate driving method, driving a power conversion device configured to include the power semiconductor in an upper arm and a lower arm,
A gate driving method, characterized in that a timing for setting the predetermined time is adjusted in a state in which a dead time accompanying ON / OFF of each power semiconductor included in the upper arm and the lower arm is fixed. The gate driving method according to any one of claims 7 to 11,
A gate driving method characterized by targeting a semiconductor made of silicon carbide (SiC) as the power semiconductor.

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