JP2017097478A - Arithmetic processing unit and control method of arithmetic processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a processing completion time of a task by a logic circuit of a programmable logic device.SOLUTION: An arithmetic processing unit comprises: a processor for executing plural tasks; a programmable logic circuit for forming a logic circuit corresponding to at least a part of plural tasks, in which the constituted logic circuit executes processing of the task; and a constitution control part for, according to processing request of the task, based on a total processing end time of a first logic circuit which has been constituted or whose constitution has been reserved, in the programmable logic circuit and an area of the first logic circuit. calculating a constitution possible time until constitution of plural kinds of second logic circuits corresponding to the task for which processing is required, is allowed, then calculating plural total processing times in which, the constitution possible time is added to a constitution time required for constitution of each of the plural kinds of second logic circuit and a processing time required for each processing, then selecting the second logic circuit requiring a shorter total processing time, then, constituting the selected second logic circuit in the programmable logic circuit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an arithmetic processing device and a control method for the arithmetic processing device.

  There has been proposed an arithmetic processing device (CPU chip) in which a processor circuit such as an arithmetic processing circuit or a CPU (Central Processing Unit) and a programmable logic circuit (PLD) are mixedly mounted. The CPU fetches and executes program instructions. In contrast, the PLD reconfigures the internal logic circuit with configuration data (configuration data or setting values for configuring the logic circuit), and some instructions or tasks in the program (for example, arithmetic functions, etc.) A logic circuit for processing (hereinafter referred to as a task or the like) is configured. As a result, a logic circuit configured in the PLD processes tasks and the like at high speed. For example, if a programmer sets a part of tasks in the program to be processed by the PLD, some tasks are executed by the PLD, and the remaining tasks are executed by the CPU. As a result, data processing by the CPU chip can be speeded up and power consumption can be reduced.

  On the other hand, the PLD forms a desired logic circuit based on the configuration data. In order to execute tasks in the program with PLD, the task code is synthesized at a high level and converted into a hardware description language (HDL), and the HDL is logically synthesized and converted into a netlist. Convert the configuration data to realize the list. PLDs include, for example, FPGAs (Field Programmable Gate Arrays) and reconfigurable LSIs.

  The instruction code can be converted to HDL corresponding to a plurality of types of logic circuits that are highly abstract and depend on the constraints. A PLD for selecting one of a plurality of logic circuits is described in the following patent documents.

JP 2000-252814 A JP 2007-179358 A

  In a conventional arithmetic processing unit in which a CPU and a PLD are mixedly mounted, a logic circuit corresponding to one task or the like is configured in the PLD, and the task or the like is executed. In other words, a conventional PLD configures a logic circuit such as one task (configuration) and executes a process. After the process is completed, the logic circuit such as a new task is reconfigured (reconfigured). : Reconfiguration) and execute the process, the logic circuit is reconfigured and the process is executed synchronously.

  However, in recent years, even with PLDs, due to the high integration and high performance of FPGAs, it is possible to execute a process by partially reconfiguring a plurality of tasks and the like asynchronously with one PLD. In this case, the plurality of tasks and the like are tasks in different programs, and the different programs are not dependent on each other. In the case of a plurality of tasks that are independent of each other, a partial reconfiguration in which a new logic circuit is configured is performed before the processing of the logic circuit that is already configured and being executed in the PLD is completed. Therefore, when a newly configured logic circuit is selected according to the size of the reconfigurable space in the PDL at that time, a logic circuit with a small area but a low processing speed is selected. This causes a problem that the processing completion time is delayed.

  Accordingly, an object of the first aspect of the embodiment is to provide an arithmetic processing device and a control method for the arithmetic processing device that can shorten the processing completion time of an instruction or a task.

  A first aspect of the disclosure includes a processor that executes a plurality of tasks and a logic circuit corresponding to at least a part of the plurality of tasks, and the configured logic circuit executes processing of the tasks Based on the logic circuit and the total processing end time of the configured or reserved configuration of the first logic circuit in the programmable logic circuit and the area of the first logic circuit according to the processing request of the task, The configurable time until each of the plurality of types of second logic circuits corresponding to the task requested to be processed is calculated, and the configuration time required for the configuration of each of the plurality of types of second logic circuits, respectively. A plurality of total processing times obtained by adding the configurable time to the processing time required for the processing of And a configuration control unit constituting the second logic circuit selected by said selecting the second logic circuit in said programmable logic circuit, an arithmetic processing unit.

  According to the first aspect, the processing completion time of an instruction or task can be shortened.

It is a figure which shows the structure of the arithmetic processing unit in this Embodiment. It is a figure explaining that a programmable logic circuit (PLD) comprises a plurality of logic circuits asynchronously. It is a figure explaining the performance and area of a logic circuit arranged (configured) in an FPGA. It is a figure which shows the processing time of three logic circuits of FIG. It is a figure explaining the problem in the case of arranging (composing) the logic circuit of a new task asynchronously. It is a figure which shows the execution time and processing amount of two logic circuits. It is a figure which shows the example which selects the logic circuit of the new task by the configuration control program in this Embodiment. It is a figure which shows the case where the task X is processed with two logic circuits, and three execution plans processed with CPU. It is a flowchart figure of the configuration control program in this Embodiment. It is a flowchart figure of the processing time prediction process of a configuration control program. It is a flowchart figure of calculation of configurable time. FIG. 12 is a flowchart of processing for determining whether or not the circuit candidate C # in FIG. 11 can be configured (arranged) in the FPGA. It is a figure which shows the example 1 of a structure (arrangement | positioning) of the logic circuit of each task by a structure control program. It is a figure which shows the example 2 of a structure (arrangement | positioning) of the logic circuit of each task by a structure control program.

  FIG. 1 is a diagram illustrating a configuration of an arithmetic processing device according to the present embodiment. An arithmetic processing unit (CPU chip) 10 fetches and executes an instruction or task in a program, a processor (or CPU) 11, an I / O processing circuit 14 that performs external input / output processing, and an external main memory A memory access control circuit (MAC) 17 that controls access to the bus and a bus BUS connecting them. Further, the arithmetic processing unit 10 is a programmable logic circuit that is reconfigured into a logic circuit corresponding to at least some instructions or tasks (hereinafter referred to as “tasks”) of a plurality of instructions or tasks in a program executed by the processor 11. (PLD) 16, a configuration information memory 12 that stores configuration information (Configuration Data) for reconfiguring PLD 16, and a configuration control program that controls the configuration, deletion, and execution of the logic circuit corresponding to the tasks of PLD 16, etc. And a memory 15. Further, the PLD 16 has a memory 13 for storing a processing time database for storing actual values of processing times of logic circuits configured in the PLD 16.

  The PLD 16 in FIG. 1 is, for example, a field programmable gate array (FPGA) or a reconfigurable circuit, and any of them can configure a desired logic circuit based on configuration data.

  The PLD 16 responds to the processor with a response indicating that the request has been accepted without performing the configuration and execution of the logic circuit corresponding to the requested task in response to the processing request for the task or the like (function or the like) from the processor. Send back. Then, the configuration control unit configured by the processor 10 executing the configuration control program 15 configures and executes a logic circuit in the PLD 16, and deletes the logic circuit after the execution is completed.

  Compared with the case where the processor 10 executes all the tasks in the program, the processing can be speeded up and the power consumption can be reduced when the dedicated logic circuit is used.

  Hereinafter, “instructions, tasks, tasks, etc.” are simply referred to as “tasks” for the sake of simplicity.

  The PLD 16 further configures and executes a plurality of tasks asynchronously. In other words, the PLD can dynamically perform partial reconfiguration (dynamic / partial reconfiguration), and without stopping the operation of the logic circuit of a certain task configured in the PLD, a new task can be created. Configure and execute the corresponding logic circuit. In this case, the plurality of tasks are not dependent on each other, and the order of execution of the plurality of tasks by the logic circuit does not have a relationship dependent on each other.

  FIG. 2 is a diagram for explaining that a programmable logic circuit (PLD) configures a plurality of logic circuits asynchronously. Among the PLDs, the FPGA, as illustrated, includes a plurality of reconfigurable logic blocks CLB arranged in a matrix, wiring channels (not shown) arranged between the logic blocks CLB, and IO pads ( (Not shown). Then, by downloading the configuration data (configuration data) into the PLD and setting it, for example, the connection configuration between the logic block CLB and the wiring channel is set to a configuration corresponding to the configuration data.

  In the example illustrated in FIG. 2, the FPGA includes a 4 × 4 logical block CLB. First, in the initial state S1, no configuration data is set, and all logical blocks are in an unconfigured state. Therefore, when a processing request for task A occurs, the configuration control program generates configuration data of the logic circuit corresponding to task A and stores it in the configuration information memory 12. Specifically, the configuration control program performs high-level synthesis of the task A instruction code and converts it to HDL (Hardware Description Language) such as RTL (Register Transfer Level), and then synthesizes HDL into a netlist by logical synthesis. Then, configuration data for realizing a netlist logic circuit is generated. Then, by writing (setting) the configuration data stored in the configuration information memory 12 to the latch circuit in the FPGA, a desired logic circuit is configured in the FPGA (S2). As a result, the FPGA configures a logic circuit corresponding to task A by two logic blocks. The FPGA inputs an input parameter for the task A of the program, starts the operation of the newly configured logic circuit of the task A based on the input parameter, and outputs the output data to the processor 11.

  In FIG. 2, when the processing request for task B is next generated, the configuration control program sets the task B configuration data in the FPGA and waits for task B without waiting for the operation of the logic circuit of task A to end. The corresponding logic circuit is configured and the operation is started (S3). As shown in the figure, in step S3, the logic circuit corresponding to task B is composed of six logic blocks adjacent to the logic circuit of task A.

  In step S4, a processing request for task C is further generated, and the configuration control program sets configuration data for task C in the FPGA to configure a logic circuit corresponding to task C.

  Next, in step S5, the processing of the logic circuit of task B is completed, and the configuration control program deletes the logic circuit of task B. Specifically, the configuration control program clears the configuration data setting of the logic circuit of task B. As a result, the area of unconfigured logic blocks has increased.

  In step S6, a task D processing request is newly generated, and the configuration control program sets the task D configuration data in the FPGA to configure the task D logic circuit. At this stage, the processing of the logic circuits of tasks A and C is incomplete, and the logic circuits of tasks A, C, and D are configured in the FPGA and operate simultaneously.

  As described above, since a logic circuit for a task of a new processing request is asynchronously configured and executed in the FPGA, a logic block in the highly integrated FPGA is effectively used to enable high-speed processing. In addition, the availability of logical blocks, which are computing resources in the FPGA, changes one by one.

  FIG. 3 is a diagram for explaining the performance and area of the logic circuit arranged (configured) in the FPGA. Since instructions and tasks in a program in a high-level language such as C language have a high level of abstraction, the same instructions and tasks can be converted into multiple types of logic circuits. For example, a logic circuit with a small circuit area that operates at a low clock frequency and a long processing time (low processing speed) and a circuit area that operates at a high clock frequency and a short processing time (high processing speed) have a large circuit area. For example, a logic circuit.

  Conversion to these different logic circuits is based on the constraints set when high-level synthesis of instructions and tasks (speed priority (priority for high-speed processing) or circuit area priority (small area, power saving priority)). It becomes possible by converting to.

  FIG. 3 shows three logic circuits CIR_1, 2, 3 that can execute the operation X corresponding to the same task. The logic circuit CIR_1 has a circuit configuration that is not pipelined, but has the smallest circuit area. The logic circuit CIR_2 is a pipelined circuit having three stages, and the circuit area is larger than that of the logic circuit CIR_1. The logic circuit CIR_3 is a pipelined circuit having 10 stages and has the largest circuit area. The larger the circuit area, the larger the circuit scale, and accordingly, the power consumption per unit time also increases.

  FIG. 4 is a diagram illustrating processing times of the three logic circuits of FIG. The horizontal axis in FIG. 4 indicates the area of each circuit, and the vertical axis indicates the task processing time by each circuit. As shown in the drawing, the first logic circuit CIR_1 cannot perform parallel processing because it does not have a pipeline configuration, so that the task processing time for processing a plurality of inputs becomes long. On the other hand, since the second and third logic circuits CIR_2 and CIR_3 have a pipeline configuration, they can perform parallel processing. Therefore, when processing a plurality of inputs, the task processing time of the second logic circuit CIR_2 is shorter than that of the first logic circuit CIR_1, and the third logic circuit CIR_3 is further shortened. In this way, parallel processing is possible as the number of pipeline stages in the logic circuit increases, and therefore processing time is shortened by parallel processing.

  As described above, the larger the circuit area, the larger the circuit scale and the greater the power consumption per unit time. However, the parallel processing reduces the total processing time, and the power consumption required to complete the entire process. Can be lower.

  In addition, the third logic circuit CIR_3 is smaller in circuit scale in each pipeline stage than the second logic circuit CIR_2, and its delay time is shorter. Therefore, the third logic circuit CIR_3 can be operated with a higher-speed clock than the second logic circuit CIR_2. It can be understood from this point that the power consumption per unit time is large.

  FIG. 5 is a diagram for explaining a problem when the logic circuit of a new task is asynchronously arranged (configured). As described with reference to FIG. 3, the same task can be processed by a plurality of types of logic circuits. Therefore, the processing performance of the arithmetic processing device can be improved by selecting an optimal logic circuit from among a plurality of types of logic circuits.

  However, when a logic circuit for a new task is arranged (configured) in the FPGA, as shown in FIG. 2, the free area in the FPGA changes each time. Therefore, if the free area is small, the processing speed is high. A logic circuit having a large circuit area cannot be arranged (configured). Therefore, a logic circuit having a low processing speed but a small circuit area must be arranged.

  FIG. 5 shows a processing example in which one of two logic circuits CIR_1 and CIR_2 capable of processing a new task X is arranged (configured) in the FPGA in the state S10. As illustrated, the logic circuit CIR_1 has a low processing speed but a small circuit area, and the logic circuit CIR_2 has a high processing speed but a large circuit area. In the FPGA in the state S10, since six logic circuits have already been arranged (configured and used), there are four empty logical blocks, and the empty area is not a single rectangular shape.

  Therefore, the logic circuit that can be arranged (configured) in the FPGA in the state S10 is the circuit CIR_1 having the smaller area. Therefore, in the state S11, the logic circuit CIR_1 is arranged (configured), and the processing time of the task X becomes longer than when the logic circuit CIR_2 can be arranged.

  FIG. 6 is a diagram illustrating the execution time and the processing amount of the two logic circuits. When the next circuit to be arranged (configured) for the new task X in the state S10 is selected as the logic circuit CIR_1 as in the example of FIG. 5, as shown by CIR_1 in FIG. The logic circuit CIR_1 can be reconfigured in the FPGA by downloading the configuration data, but since the processing speed is slow, the time until the processing amount of the task X is reached becomes long.

  On the other hand, when the circuit to be arranged (configured) for task X in state S10 is selected as logic circuit CIR_2, as shown by CIR_2 in FIG. Therefore, the total of the waiting time until the logic circuit CIR_2 is arranged (configured) and the time required for reconfiguration is longer than that of the logic circuit CIR_1. However, since the processing speed of the logic circuit CIR_2 is high, the total time until the processing amount of the task X is reached is shorter than that of the logic circuit CIR_1.

[Method for selecting logic circuit of this embodiment]
The configuration control program according to the present embodiment performs the following processing, selects a logic circuit that finishes processing earlier, and places (configures) it in the PLD.

  That is, the configuration control program, in response to a new task processing request, determines the total processing end time of the logic circuit of the accepted task that has already been configured in the PLD or reserved to be configured and the logic circuit Based on the area, a configurable time T # wait (# represents a plurality of types of numbers) until each of a plurality of types of logic circuits corresponding to a new task can be generated is generated (or calculated). In other words, since the logic circuit is erased at each total processing end time of the logic circuit of the accepted task and a free area is formed, it is arranged at each time of the total processing end time among the plural types of logic circuits of the new task. A (configurable) logic circuit is detected, and a configurable time T # wait is obtained, which is waited until it can be arranged (configurable). This is obtained for each of all logic circuits.

  Next, the configuration control program adds the configurable time T # wait to the configuration time T # conf required for the placement (configuration) of each of the multiple types of logic circuits of the new task and the processing time T # exe required for each processing. Is generated (or calculated). Then, the configuration control program selects a logic circuit with a shorter total processing time and places (configures) the selected logic circuit in the PLD. Preferably, the logic circuit with the shortest total processing time is selected.

  Thereby, it is possible to select a logic circuit having the earliest time for completing the processing of a new task.

  FIG. 7 is a diagram showing an example of selecting a logic circuit for a new task by the configuration control program in the present embodiment. The example of FIG. 7 assumes a case where a processing request for a new task X is made to the FPGA in the state S10, as in FIG. Then, it is assumed that the configuration control program performs high-level synthesis of task X, converts it into HDL, further performs logic synthesis, converts it into a net list, and further generates configuration data for configuring a logic circuit of the net list. That is, it is assumed that configuration data of two types of logic circuits CIR_1 and CIR_2 that process task X is generated. In the state S10, six logic circuits have already been configured and are being executed in the FPGA, and the predicted total processing end time at which the processing of these logic circuits ends is as illustrated.

  In the above case, the configuration control program configures the configurable time T # wait that is waited until placement (configuration) is possible for each of the two candidate logic circuits, and the configuration required to download and set the configuration data to the FPGA. The time T # conf and the processing time T # exe required for each process are calculated or extracted from the database. Then, the configuration control program selects one of the two candidate logic circuits having a shorter total processing time T # total obtained by adding the above times.

  FIG. 8 is a diagram illustrating a case where task X is processed by two logic circuits and three execution plans processed by the CPU. In FIG. 8, when task X is processed by the logic circuit CIR_1, A is processed by the logic circuit CIR_2, B is executed by the CPU, and C is configurable time, configuration time, processing time, and total processing time. It is shown.

  Depending on the state of the six logic circuits that have been arranged (configured) and are being executed in the FPGA shown in state S10 when the processing request for task X in FIG. 7 occurs, and the total processing end time of each logic circuit For example, since the area is small in the case of the logic circuit CIR_1, the configurable time (waiting time until configuration) is 0 sec. The configuration time, processing time, and total processing time of the logic circuit CIR_1 are as shown in FIG.

  On the other hand, since the logic circuit CIR_2 has a large area, the logic circuit CIR_2 has a configurable time of 500 ns because it can be configured by waiting until the logic circuit with the predicted total processing end time of 500 ns finishes the processing. The configuration time, processing time, and total processing time of the logic circuit CIR_2 are as shown in FIG. The logic circuit CIR_2 has a longer area because it has a larger area than the logic circuit CIR_1, but the processing time is shorter and the total processing time is shorter.

  Further, when the task X is executed by the CPU rather than being processed by the logic circuit in the FPGA, both the configurable time and the configuration time are 0 sec. However, the processing time is longer than the two logic circuits due to execution by the CPU, and the total processing time is also longer.

  Therefore, the configuration control program selects a logic circuit CIR_2 with a shorter total processing time based on the total processing time of the logic circuits CIR_1 and CIR_2 shown in the table of FIG. 8, and places (configures) the reservation in the FPGA. Register to state.

  FIG. 9 is a flowchart of the configuration control program in the present embodiment. When receiving a new task processing request from the CPU (YES in S20), the control configuration program performs new task configuration / execution processing (S21).

  The new task configuration / execution process S21 is shown on the right side of FIG. First, the configuration control program performs high-level synthesis or the like on the new task, generates configuration data of a plurality of logic circuits C # (# = 1 to n) that can process the new task, and writes the configuration data to the configuration information memory 12 (S30). ).

  Next, the configuration control program calculates a circuit configuration time T # conf and a logic circuit processing time T # exe required to configure the logic circuit by setting the configuration data in the PLD for each logic circuit ( S31). These times are calculated based on the performance of circuits configured in the FPGA in the past. A specific calculation example will be described later.

  Further, the configuration control program calculates a configurable time T # wait, which is a time waited until it becomes configurable for each logic circuit (S32). The configurable time T # wait is calculated based on the predicted total processing end time of the logic circuits configured or reserved for configuration in the FPGA and the areas and positions of the logic circuits. A specific calculation example will be described later.

Then, the configuration control program calculates the total processing time T # total of each logic circuit as follows (S33)
Total processing time T # total = T # wait + T # conf + T # exe

Further, the configuration control program selects the one having the minimum total processing time T # total for the plurality of logic circuits. Then, the selected minimum total processing time T # total is added to the current time as follows to calculate the total processing end time (predicted total processing end time) T # total_end and store it in the memory (S34).
Total processing end time T # total_end = current time + T # total (minimum value)
Since this total processing end time T # total_end is referred to later when the configurable time T # wait is calculated, it is stored in the memory.

  The logic circuit that processes a new task is selected by the above processing, the time (current time + T # wait) at which the logic circuit is arranged (configured) in the FPGA is determined, and the time when the processing of the logic circuit is completed ( Total processing end time) T # total_end is calculated.

  Next, the configuration control program determines whether or not the selected logic circuit Cx can be configured (arranged) at the present time (S35). In this determination, it is determined that configuration is possible when the configurable time Tx_wait = 0. If configurable (YES in S35), the logic circuit Cx is configured in the FPGA (S37). On the other hand, when the configuration is not possible (when the configurable time Tx_wait is not 0) (NO in S35), the configuration of the logic circuit Cx is reserved (S36). In the configuration reservation, the logic circuit Cx is stored in the reservation matrix together with the information on the configuration position and area, the configuration reservation time, and the like.

  The configuration control program determines whether or not the logic circuit reserved to be configured can be configured (arranged) at every timing when processing of the logic circuit in the FPGA is completed (S35). In this determination, it is determined whether or not the configurable time Tx_wait has elapsed and the logic circuit can be configured as a PLD. When the reserved logic circuit becomes configurable (YES in S35), the configuration control program configures the reserved logic circuit Cx in the reserved position in the FPGA (S37).

  When the logic circuit Cx is configured in the FPGA, the configuration control program updates the total processing end time Tx_total_end stored in step S34 to a time obtained by adding the logic circuit processing time Tx_exe to the current time (S37). This update process may be performed in order to improve the accuracy of the total process end time of the logic circuit Cx because the predicted configurable time Tx_wait and the actually waited time may be different when the configuration is reserved. Is called.

  When the configured logic circuit Cx executes the process and the execution is completed, the configuration control program stores the actual value of the processing time Tx_exe in the memory 13 of the processing time database (S38). The actual processing time value is referred to when the processing time of the logic circuit is estimated.

  As described above, every time a processing request for a new task is received, the configuration control program selects a logic circuit having the shortest total processing time T # total from among a plurality of logic circuits capable of processing the new task, The possible time (current time + configurable time T # wait) and the total processing end time T # total_end are stored in the memory. Further, the actual value of the processing time T # exe actually required when the logic circuit is completed is also stored in the processing time database.

[Calculation method of processing time]
FIG. 10 is a flowchart of the processing time prediction process of the configuration control program. The configuration control program calculates the average processing time μ of the logic circuit that processes the task as follows (S40).
μ = Tconst + L (argument value)
Here, Tconst is a fixed processing time, which is a time predicted according to the content of the task at the time of high-level synthesis or an average value of processing times of the same task in the past. L (x) corresponds to a change in processing time according to the task argument x. Since the processing amount varies depending on the task argument x, it corresponds to the variation time.

For example, an example of an argument that affects the processing amount is a function F (x, y), a single loop whose number of iterations is an argument x, and a double loop whose number of iterations is an argument x and an argument y The following delay time occurs.
L (x, y) = c0 * x + c1 * x * y
C0 and C1 are coefficients.

In addition, when the memory access priority is set according to the importance of processing, the above average processing time μ may be modified as follows by multiplying by the coefficient of the importance Cimp.
μ ＝ Cimp * {Tconst + L (argument value)}

  Further, the configuration control program obtains a standard deviation σ, which is a degree of dispersion of processing time, from the execution result of the same task in the past (S41).

Next, the configuration control program calculates the shake value Env of the processing time due to disturbance as follows (S42).
Env = T_fpga * E0 + P_fpga * E1
T_fpga is a fluctuation value of the processing time depending on the temperature T of the FPGA, and P_fpga is a fluctuation value of the processing time depending on the power consumption P of the FPGA. Since the processing speed changes as the FPGA temperature rises, and the processing speed changes as the power consumption increases, it is desirable to reflect the shake value in the processing time. E0 and E1 are coefficients or weight values.

  In addition to the above, a shake value F_fpga depending on the operating frequency F of the FPGA may be added. If the operating frequency F is increased, the processing time is shortened. Further, a shake value S_fpga depending on the circuit area S may be added. The larger the circuit area S, the shorter the processing time for parallel processing.

For example, it is desirable to adjust the processing time up and down depending on how high or low the FPGA operating frequency F_fpga is relative to the reference frequency F_ref. For example, it is as follows.
Env = μ * {(F_ref-F_fpga) / F_ref} * Ct
Here, Ct is a conversion coefficient or a weight value. When F_fpga> F_ref, Evn becomes a negative value and the processing time is shortened. In the opposite case, Evn becomes a positive value and the processing time becomes longer. The processing time becomes longer or shorter by the average value μ multiplied by the ratio of the difference between both frequencies.

Finally, the configuration control program calculates the processing time T # exe of the logic circuit that processes the task as follows (S43).
T # exe = μ + W0 * σ * rand + W1 * Env
Here, W0 and W1 are weighting coefficients (W0, W1 = 0 to 1), and rand is a standard normal random number. In other words, the standard normal random number rand is a random number whose distribution is a normal distribution. By multiplying the standard normal random number rand by the standard deviation σ, which is the degree of dispersion of the past processing time, random fluctuations in the processing time of the logic circuit each time Can be added.

[Processing time calculation example 1]
The first example is a function send () for transmitting a fixed packet, and the history of past processing times is as follows.
1st: Processing time 1105 ns
Second time: Processing time 1320 ns
3rd: Processing time 1190 ns

Therefore, the processing time derivation method is as follows. First, assuming that the processing time is random from the history of past processing times, the average value Tconst and the standard deviation σ are calculated as follows.
Tconst = 1205 ns
σ = 88.4 ns

Since random factors are dominant, the coefficient of random factors is set to W0 = 1.0. Since there is no argument, L (argument value) = 0. Further, the noises Env and W1 due to disturbance are assumed as follows.
Env = Tconst * {(250MHx-F_fpga) / 250MHx}
= 1205 ns * {(250MHx-F_fpga) / 250MHx}
W1 = 0.7

As a result, the processing time T # exe of the first example is calculated as follows.
T # exe = Tconst + W0 * σ * rand + W1 * Env
= 1205 ns + W1 * 1205 ns * {(250MHx-F_fpga) / 250MHx} + W0 * σ * rand
= 1205 ns [1 + 0.7 {(250-F_fpga) / 250}] + 88.4 ns * rand

[Processing time calculation example 2]
The second example is a function var (sizex, sizey, * image). This function is a function for outputting a variance value of pixel values for every 4 × 4 pixels to the memory RAM for an input image having the number of pixels of sizex * sizey, and the processing amount is proportional to the argument sizex * sizey. * image means the pointer of the image filter for obtaining the variance value.

Therefore, it is assumed that the history of past processing is as follows.
1st: Argument (256, 256, * ptr), processing time 1200 ps
2nd: Argument (64, 64, * ptr), processing time 900 ps

  The method for deriving the processing time in the above case is as follows. That is, since this function has no random factor, the coefficient W0 of the random term is set to W0 = 0.

Further, it is assumed that a portion μ = Tconst + L (*) corresponding to the average value is a linear function as follows.
μ = A * sizex * sizey + Tconst
That is, L (*) = A * sizex * sizey is considered. A is a coefficient.

Substituting the above history values into this linear function and solving the simultaneous equations, A and Tconst are obtained as follows.
A = 0.184 [ps / pel]
Tconst = 146.2 ps
Here, pel means a pixel.

Also, assume that the fluctuation factor Env and its coefficient W1 due to disturbance are as follows.
Env = F (RAM usage)
W1 = 0.1
Here, as the RAM usage amount increases, the RAM free space decreases and the processing time increases, and the variation factor is reflected in the above-described Env.

As a result, the processing time T # exe is as follows.
T # exe = (sizex * sizey * 0.184) + 146.2 + 0.1 * F (RAM usage)

[Calculation method of configurable time]
FIG. 11 is a flowchart of the configurable time calculation. Hereinafter, a method for calculating the configurable time T # wait will be described. The configurable time T # wait is the time that each of the plurality of logic circuit candidates C # can be configured (arranged) in the FPGA earliest. In addition, since the free space in the FPGA changes every time when the logic circuit of the task that has occurred finishes the operation (total processing end time T # total_end), the configuration control program is based on the changing free space. It is determined whether or not the candidate C # can be configured (arranged).

  First, Steps S50 to S56 are repeated for each of all logic circuit candidates C # for processing a new task.

  Further, for each logic circuit candidate C #, steps S51 to S55 are repeated in order from the earliest of the total processing end time T # _total_end of the generated logic circuits of all tasks. More specifically, steps S51 to S55 are repeated starting with the current time (T # _total_end = 0) first, and starting with the earliest total processing end time T # _total_end (S51).

  As described above, the status of the logic circuit configured in the FPGA changes at each of these total processing end times, so the area of the logic circuit of all the tasks being executed in the FPGA is changed at all timings that change. It is determined whether or not the circuit candidate C # of the new task can be configured (arranged) in the empty area based on the position (S52). For this determination, both the free space in the FPGA at each total processing end time and the free space in the FPGA during the period in which the circuit candidate C # is configured (arranged) (T # conf + T # exe) The area needs to be larger than the area of the circuit candidate C #.

When the circuit candidate C # can be configured (arranged), the configurable time T # wait that the circuit candidate C # waits until the configuration is the difference between the total processing end time to be determined and the current time. It is calculated as follows.
T # wait = total processing end time T # _total_end-current time

  The above steps S51 to S55 are repeated until the circuit candidate C # can be configured (S55), and further repeated for all circuit candidates C # (S56).

  FIG. 12 is a flowchart of a process for determining whether or not the circuit candidate C # in FIG. 11 can be configured (arranged) in the FPGA. FIG. 12 shows step S53 of FIG. 11 as two steps S53_1 and S53_2. The configuration control program determines whether or not a new candidate C # can be configured (arranged) in an empty area in the FPGA at the total processing end time T # total_end (S53_1). In this determination, the configuration control program considers the deletion of the logic circuit that ends at the total processing end time T # total_end and the addition of the reserved logic circuit that is newly configured at the same total processing end time T # total_end. Then, the empty area and its shape are calculated, and it is determined whether or not a new candidate C # can be configured in the empty area.

  Furthermore, if YES in S53_1, the configuration control program assumes that the reserved circuit C has been configured (arranged) during the total time T # cnf + T # exe of the configuration time and processing time of the new circuit candidate C #. Also, it is determined whether or not a new circuit candidate C # can be configured (S53_2). That is, it is necessary to maintain the configuration state of the new candidate C # even if the reserved circuit C is arranged in the future.

[Logic circuit configuration (arrangement) example 1]
FIG. 13 is a diagram showing a configuration (arrangement) example 1 of the logic circuit of each task by the above-described configuration control program. In Example 1, four new tasks TA0 to TA3 are requested in order from the processor. In FIG. 13, the horizontal axis indicates time.

First, a new task TA0 is requested at time 450ns. Since no logic circuit is configured in the FPGA, the configuration control program selects the optimal circuit C0 (the fastest total processing time T # total) from among the circuit candidates C # for the new task TA0, and the FPGA The circuit operation is started. The total processing time and total processing end time of the circuit C0 are as follows.
Total processing time T0_total = 1950ns
Total processing end time T0_total_end = 2400ns

Next, a new task TA1 is requested at time 720ns. The configuration control program selects the optimum circuit C1 (the fastest total processing time T # total) from among the circuit candidates C # of the new task TA1 that can be placed in an empty area in the FPGA. Since the selected circuit C1 can be configured at this time 720 ns, the configuration control program configures (arranges) the FPGA and starts its circuit operation. The total processing time and total processing end time of the circuit C1 are as follows.
Total processing time T1_total = 2680ns
Total processing end time T1_total_end = 3400ns

Next, a new task TA2 is requested at time 1500ns. The configuration control program selected the optimal circuit C2 from among the circuit candidates C # of the new task TA2 that can be placed in an empty area in the FPGA. Since it becomes configurable after completion, it is in a configuration reservation state. The configurable time, total processing time, and total processing end time of the circuit C2 are as follows.
Configurable time T2wait = 900ns
Total processing time t2_total = 500ns
Total processing end time T2_total_end = 2900ns

Finally, a new task TA3 is requested at time 2100ns. The configuration control program selected the optimal circuit C3 from among the circuit candidates C # for the new task TA3 that can be placed in an empty area in the FPGA. Since it becomes configurable later, the configuration reservation state is set. The configurable time, total processing time, and total processing end time of the circuit C3 are as follows.
Configurable time T2wait = 800ns
Total processing time t2_total = 1000ns
Total processing end time T2_total_end = 3900ns

  The circuit C2 of the task TA2 is configured in the FPGA at the time 2400ns when the circuit C1 ends, and the circuit C3 of the task TA3 is configured in the FPGA at the time 2900ns when the circuit C2 ends. In Example 1, circuits are configured in the FPGA in the order of task generation.

[Logic circuit configuration (arrangement) example 2]
FIG. 14 is a diagram showing a configuration (arrangement) example 2 of the logic circuit of each task by the above-described configuration control program. Also in this example 2, four new tasks TA0-TA3 are requested in order. In Example 2, the configurations (arrangements) of the circuits C0, C1, C2 of the new tasks T0, T1, T2 are the same as in Example 1, but the timing of configuring (arranging) the circuit C3 of the new task TA3 is Example 1. And different.

  New tasks TA0, TA1, and TA2 are the same as in Example 1.

  Finally, a new task TA3 is requested at time 2100ns. The configuration control program has selected the optimum circuit C3 from among the circuit candidates C # of the new task TA3 that can be placed in an empty area in the FPGA, but the circuit C3 of Example 2 has a smaller area than the circuit C3 of Example 1. .

The configuration control program can be placed in the FPGA for the circuit C3 at the request time 2100ns of the new task TA3, and even if the reserved circuit C2 is placed during the total processing time T3_total of the circuit C3 Determine that it is possible. As a result, the configuration control program places the circuit C3 in the FPGA and executes it. Therefore, the configurable time, total processing time, and total processing end time of the circuit C3 are as follows.
Configurable time T2wait = 0ns
Total processing time t2_total = 1000ns
Total processing end time T2_total_end = 3100ns

  The circuit C2 of the task TA2 is configured in the FPGA at time 2400ns, and the circuit C3 of the task TA3 is configured in the FPGA at time 2100ns before the circuit C2 of the task TA2 requested earlier. In Example 2, the order in which tasks are generated differs from the order in which circuits are configured in the FPGA. Since each task is requested from a different program that does not depend on each other, the configuration control program can independently determine the configuration of the circuit corresponding to the task and the order of execution.

  As described above, in the present embodiment, when the programmable logic device PLD processes a plurality of tasks asynchronously, an optimal logic circuit for processing each task is configured in the PLD to increase the processing efficiency of each task. Can do.

  The above embodiment is summarized as follows.

(Appendix 1)
A processor that performs multiple tasks;
A logic circuit corresponding to at least some tasks of the plurality of tasks is configured, and the configured logic circuit executes processing of the task; and
In response to the processing request of the task, the processing request is made based on the total processing end time of the first logic circuit configured or reserved in the programmable logic circuit and the area of the first logic circuit. The configurable time until each of the plurality of types of second logic circuits corresponding to the task is calculated is calculated, and the configuration time required for the configuration of each of the plurality of types of second logic circuits and each processing are calculated. A plurality of total processing times obtained by adding the configurable time to the processing time are calculated, a second logic circuit having a shorter total processing time is selected, and the selected second logic circuit is placed in the programmable logic circuit. An arithmetic processing unit having a configuration control unit configured.

(Appendix 2)
The configuration control unit
The arithmetic processing apparatus according to appendix 1, wherein in selecting the second logic circuit, the second logic circuit corresponding to the shortest total processing time among the plurality of total processing times is selected.

(Appendix 3)
The configuration control unit
In response to the task processing request, the second logic circuit corresponding to the task requested to be processed without synchronizing with the end of the task processing of the first logic circuit already configured in the programmable logic circuit. The arithmetic processing unit according to appendix 1 or 2, wherein the programmable logic circuit is configured.

(Appendix 4)
The configuration control unit
When processing the task, the total processing end time is calculated from the total processing time and the current time of the selected second logic circuit, and stored.
Further, when the selected second logic circuit is configured in the programmable logic circuit, the total processing end time is calculated from the processing time and the current time, and the stored total processing end time is updated. The arithmetic processing apparatus according to appendix 1 or 2.

(Appendix 5)
The configuration control unit
Storing the actual value of the processing time of the second logic circuit corresponding to the task;
The processing time of the second logic circuit corresponding to the new task is predicted based on the actual value of the processing time of the task corresponding to the new task when the processing request for the new task is requested Or the arithmetic processing apparatus of 2.

(Appendix 6)
The configuration control unit
When calculating the configurable time, it is determined whether the logic circuit corresponding to the new task can be configured in the programmable logic circuit in the order of the total processing end time of the generated task logic circuit. The arithmetic processing apparatus according to appendix 1 or 2, wherein a time from the current time to the configurable total processing end time is calculated as the configurable time.

(Appendix 7)
The configuration control unit
It is determined whether or not a logic circuit corresponding to the new task can be configured in the programmable logic circuit. In a period from the configuration of the logic circuit to the end of execution, the logic circuit is stored in the programmable logic circuit. The arithmetic processing device according to attachment 6, wherein it is determined whether or not the configuration is possible.

(Appendix 8)
The configuration control unit
The logic circuit corresponding to the new task is configured in the programmable logic circuit before the logic circuit corresponding to the task generated prior to the new task is configured in the programmable logic circuit. The arithmetic processing apparatus according to appendix 7.

(Appendix 9)
The configuration control unit
After the processing of the logic circuit is completed, the actual processing time of the selected second logic circuit is stored in association with the corresponding task,
The arithmetic processing device according to appendix 1 or 2, wherein a processing time required for processing of each of the plurality of types of second logic circuits is predicted based on the stored actual processing time.

(Appendix 10)
The plurality of second logic circuits include at least a first circuit having a first area and a first processing speed, a second area wider than the first area, and faster than the first processing speed. The arithmetic processing apparatus according to attachment 1, further comprising: a second circuit having a second processing speed.

(Appendix 11)
The arithmetic processing device according to attachment 1, wherein the programmable logic circuit is either a field programmable gate array or a reconfigurable circuit.

(Appendix 12)
A processor that performs multiple tasks;
A logic circuit corresponding to at least a part of the plurality of tasks is configured, and the configured logic circuit executes a process of the task.
In response to the processing request of the task, the processing request is made based on the total processing end time of the first logic circuit configured or reserved in the programmable logic circuit and the area of the first logic circuit. The configurable time until each of a plurality of types of second logic circuits corresponding to each task becomes configurable,
A plurality of total processing times obtained by adding the configurable time to the configuration time required for the configuration of each of the plurality of types of second logic circuits and the processing time required for each processing;
Select a second logic circuit with a shorter total processing time;
A method for controlling an arithmetic processing unit, wherein the selected second logic circuit is configured in the programmable logic circuit.

CPU: Processor
PLD: Programmable logic device 15: Configuration control program
C #: Candidate logic circuit
T # wait: Configurable time
T # conf: Configuration time
T # exe: Processing time
T # total: Total processing time
T # total_end: Total processing end time

Claims (10)

A processor that performs multiple tasks;
A logic circuit corresponding to at least some tasks of the plurality of tasks is configured, and the configured logic circuit executes processing of the task; and
In response to the processing request of the task, the processing request is made based on the total processing end time of the first logic circuit configured or reserved in the programmable logic circuit and the area of the first logic circuit. The configurable time until each of the plurality of types of second logic circuits corresponding to the task is calculated is calculated, and the configuration time required for the configuration of each of the plurality of types of second logic circuits and each processing are calculated. A plurality of total processing times obtained by adding the configurable time to the processing time are calculated, a second logic circuit having a shorter total processing time is selected, and the selected second logic circuit is placed in the programmable logic circuit. An arithmetic processing unit having a configuration control unit configured. The configuration control unit
2. The arithmetic processing apparatus according to claim 1, wherein, in selecting the second logic circuit, a second logic circuit corresponding to a shortest total processing time is selected from the plurality of total processing times. The configuration control unit
In response to the task processing request, the second logic circuit corresponding to the task requested to be processed without synchronizing with the end of the task processing of the first logic circuit already configured in the programmable logic circuit. The arithmetic processing unit according to claim 1 or 2, wherein the programmable logic circuit is configured. The configuration control unit
When processing the task, the total processing end time is calculated from the total processing time and the current time of the selected second logic circuit, and stored.
Further, when the selected second logic circuit is configured in the programmable logic circuit, the total processing end time is calculated from the processing time and the current time, and the stored total processing end time is updated. The arithmetic processing apparatus according to claim 1 or 2. The configuration control unit
Storing the actual value of the processing time of the second logic circuit corresponding to the task;
The processing time of the second logic circuit corresponding to the new task is predicted based on the actual value of the processing time of the task corresponding to the new task when a processing request for the new task is requested. The arithmetic processing apparatus according to 1 or 2. The configuration control unit
When calculating the configurable time, it is determined whether the logic circuit corresponding to the new task can be configured in the programmable logic circuit in the order of the total processing end time of the generated task logic circuit. The arithmetic processing apparatus according to claim 1, wherein a time from the current time to the configurable total processing end time is calculated as the configurable time. The configuration control unit
It is determined whether or not a logic circuit corresponding to the new task can be configured in the programmable logic circuit. In a period from the configuration of the logic circuit to the end of execution, the logic circuit is stored in the programmable logic circuit. The arithmetic processing device according to claim 6, wherein it is determined whether the configuration is possible. The configuration control unit
The logic circuit corresponding to the new task is configured in the programmable logic circuit before the logic circuit corresponding to the task generated prior to the new task is configured in the programmable logic circuit. The arithmetic processing device according to claim 7. The configuration control unit
After the processing of the logic circuit is completed, the actual processing time of the selected second logic circuit is stored in association with the corresponding task,
The arithmetic processing device according to claim 1, wherein a processing time required for processing of each of the plurality of types of second logic circuits is predicted based on the stored actual processing time. A processor that performs multiple tasks;
A logic circuit corresponding to at least a part of the plurality of tasks is configured, and the configured logic circuit executes a process of the task.
In response to the processing request of the task, the processing request is made based on the total processing end time of the first logic circuit configured or reserved in the programmable logic circuit and the area of the first logic circuit. The configurable time until each of a plurality of types of second logic circuits corresponding to each task becomes configurable,
A plurality of total processing times obtained by adding the configurable time to the configuration time required for the configuration of each of the plurality of types of second logic circuits and the processing time required for each processing;
Select a second logic circuit with a shorter total processing time;
A method for controlling an arithmetic processing unit, wherein the selected second logic circuit is configured in the programmable logic circuit.

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