JP2016195179A - Switching element unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching element unit capable of facilitating formation of a gate signal line while reducing inductance.SOLUTION: A switching element unit comprises: a first insulation substrate; a first chip that is mounted on a first surface of the first insulation substrate and that includes a first switching element for forming an upper arm of a power conversion device; a second chip that is mounted on a second surface at an opposite side to the first surface of the first insulation substrate and that includes a second switching element for forming a lower arm of the power conversion device; a first conductor part that is formed on the first insulation substrate and electrically connected with a gate electrode of the second switching element; and a second conductor part that is formed on the first insulation substrate and electrically connected with an output electrode of the power conversion device and that includes a first through conductor part penetrating through the first insulation substrate and electrically connecting between the first chip and the second chip.SELECTED DRAWING: Figure 12

Description

  The present disclosure relates to a switching element unit.

  2. Description of the Related Art A semiconductor power conversion device including a power semiconductor chip, a semiconductor chip structure including a P bus bar and an N bus bar provided so as to sandwich the power semiconductor chip from both sides, and a capacitor is known (for example, Patent Document 1). reference). In this semiconductor power conversion device, the capacitor is supported so as to be sandwiched between the P bus bar and the N bus bar, and the semiconductor chip structure and the capacitor are arranged close to each other in parallel.

JP 2007-215396 A

  In the structure described in Patent Document 1, two power semiconductor chips are arranged above and below the AC bus bar, so that inductance can be reduced, but electrical connection to the gate electrode of the power semiconductor chip is difficult. It is. Specifically, in the structure described in Patent Document 1, the gate signal line is formed (for example, formed by bonding a copper wire to the gate electrode by wire bonding) due to the presence of upper and lower bus bars such as an AC bus bar. It is very difficult.

  Therefore, an object of the present disclosure is to provide a switching element unit that can easily form a gate signal line while reducing inductance.

According to one aspect of the present disclosure, an insulating first insulating substrate;
A first chip including a first switching element mounted on a first surface of the first insulating substrate and forming one of upper and lower arms of a power converter;
A second chip including a second switching element mounted on the second surface opposite to the first surface of the first insulating substrate and forming the other of the upper and lower arms of the power converter;
A first conductor formed on the first insulating substrate and electrically connected to a gate electrode of the second switching element;
A second conductor portion formed on the first insulating substrate and electrically connected to an output electrode of the power converter, and penetrating the first insulating substrate between the first chip and the second chip; There is provided a switching element unit including a second conductor portion including a first through conductor portion that is electrically connected.

  According to the present disclosure, it is possible to obtain a switching element unit that facilitates formation of a gate signal line while reducing inductance.

It is sectional drawing which shows an example of a switching element unit. It is sectional drawing along line AA of FIG. It is sectional drawing along line BB of FIG. It is sectional drawing along line CC of FIG. It is sectional drawing along line DD of FIG. It is sectional drawing along line EE of FIG. It is sectional drawing along line FF of FIG. It is sectional drawing along line GG of FIG. It is sectional drawing along line HH of FIG. It is sectional drawing along line II of FIG. It is a top view of the switching element unit of FIG. It is sectional drawing along line XX of FIG. It is sectional drawing along line YY of FIG. It is sectional drawing along line ZZ of FIG. 1 is a diagram illustrating an example of an overall configuration of an electric vehicle motor drive system 100. FIG. It is sectional drawing of the switching element unit by a modification.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a side view schematically showing an example of a switching element unit. In FIG. 1, the inside is shown in a transparent manner so that the position of each cross section in FIGS. 2 to 10 can be seen. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a cross-sectional view taken along line BB in FIG. FIG. 4 is a cross-sectional view taken along line CC in FIG. FIG. 5 is a cross-sectional view taken along line DD in FIG. FIG. 6 is a cross-sectional view taken along line EE of FIG. FIG. 7 is a cross-sectional view taken along line FF in FIG. FIG. 8 is a cross-sectional view taken along line GG in FIG. FIG. 9 is a cross-sectional view taken along line HH in FIG. FIG. 10 is a cross-sectional view taken along line II in FIG. FIG. 11 is a schematic plan view of the switching element unit of FIG. In FIG. 11, the inside is shown in a transparent manner so that the position of each cross section in FIGS. 12 to 14 can be seen. FIG. 12 is a cross-sectional view taken along line XX in FIG. 13 is a cross-sectional view taken along line YY in FIG. 14 is a cross-sectional view taken along line ZZ in FIG. The first chip 21 and the like are shown in a schematic cross section in the cross-sectional view.

  In the following, as shown in FIG. 1, upper and lower sides, left side and right side are defined. The upper side and the lower side do not necessarily correspond to the upper side and the lower side in the vertical direction at the time of mounting. The same applies to the left and right sides, and the orientation of the switching element unit 1 at the time of mounting is arbitrary. In the following description, the “lower surface” refers to a surface facing downward and does not necessarily have to be a flat surface. The same applies to the “upper surface”.

  The switching element unit 1 forms an inverter 103 (an example of a power converter, see FIG. 15) that drives a traveling motor 104 (see FIG. 15) used in a hybrid vehicle or an electric vehicle. Inverter 103 includes a three-phase upper and lower arm, and each upper and lower arm includes two sets of switching elements and FWD (Free Wheeling Diode). The switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor). The IGBT may be formed of, for example, GaN (gallium nitride) or SiC (silicon carbide). Hereinafter, as an example, a structure in which the switching element unit 1 includes an arbitrary upper and lower arm will be described.

  The switching element unit 1 includes a first insulating substrate 10, a first chip 21, a second chip 22, a first conductor portion 31, and a second conductor portion 32.

  The first insulating substrate 10 is a substrate having an insulating property. In the illustrated example, the first insulating substrate 10 is formed of a ceramic substrate having insulation and heat resistance as an example.

  The first chip 21 is mounted on the upper surface of the first insulating substrate 10. The first chip 21 includes an IGBT that forms an upper arm. The first chip 21 may be a reverse conducting IGBT (RC (Reverse Conducting) -IGBT) chip having a built-in FWD. Hereinafter, as an example, it is assumed that the first chip 21 is a chip of reverse conducting IGBT. The IGBT of the first chip 21 includes a first surface electrode on the first surface and a second surface electrode on the second surface. The first surface electrode corresponds to the collector electrode and the cathode electrode, and is simply referred to as “collector electrode” hereinafter. The second surface electrode corresponds to the emitter electrode and the anode electrode, and is hereinafter simply referred to as “emitter electrode”. The first chip 21 includes a gate electrode 211 (see FIG. 11) at the end of the first surface. The first chip 21 is mounted on the upper surface of the first insulating substrate 10 with the second surface facing the upper surface of the first insulating substrate 10.

  As shown in FIG. 12, the first chip 21 is preferably bonded to the upper surface of the first insulating substrate 10 via a first bonding layer 51 having conductivity. The first bonding layer 51 is formed of, for example, solder or silver paste. As the silver paste, for example, a silver nanopaste including nanoparticles having a particle size of nano units may be used. By bonding the first chip 21 to the first insulating substrate 10 via the first bonding layer 51, the first chip 21 is electrically connected to the upper surface of the first insulating substrate 10 by a spring. It becomes the structure which is easy to implement | achieve high electrical conductivity and high thermal conductivity efficiently (for example, it is not necessary to arrange | position a some spring in order to implement | achieve high electrical conductivity and high thermal conductivity).

  The second chip 22 is mounted on the lower surface of the first insulating substrate 10. The second chip 22 includes an IGBT that forms a lower arm. The second chip 22 may have the same chip structure as that of the first chip 21. Hereinafter, as an example, the second chip 22 is assumed to be a chip of reverse conducting IGBT. The IGBT of the second chip 22 includes a first surface electrode on the first surface and a second surface electrode on the second surface. Similarly, the first surface electrode corresponds to the collector electrode and the cathode electrode, and is simply referred to as “collector electrode” hereinafter. The second surface electrode corresponds to the emitter electrode and the anode electrode, and is hereinafter simply referred to as “emitter electrode”. The second chip 22 includes a gate electrode 221 (see FIG. 11) at the end of the first surface. The second chip 22 is mounted on the lower surface of the first insulating substrate 10 with the first surface facing the lower surface of the first insulating substrate 10.

  As shown in FIG. 12, the second chip 22 is preferably bonded to the lower surface of the first insulating substrate 10 via a second bonding layer 52 having conductivity. The second bonding layer 52 is formed of, for example, solder or silver paste. Thereby, compared with the structure which the 2nd chip | tip 22 is electrically connected to the lower surface of the 1st insulating substrate 10 with a spring, it becomes a structure which is easy to implement | achieve high electrical conductivity and high thermal conductivity efficiently.

  The first conductor portion 31 is formed on the first insulating substrate 10. The first conductor portion 31 is electrically connected to the IGBT gate electrode 221 of the second chip 22. In the illustrated example, the first conductor portion 31 includes a conductor pattern 310 and a via 312 extending vertically from the upper surface of the first insulating substrate 10 as shown in FIGS. 5, 6, 7, and 12. Including. As shown in FIG. 12, the conductor pattern 310 has an inner layer of the first insulating substrate 10 and a lower surface of the first insulating substrate 10 (thickness equivalent to the thickness of the bonding layer 52a + corresponding to the thickness of the conductor pattern 310). Formed on the lower surface). The via 312 is formed to be offset (on the left side in the illustrated example) with respect to the bonding range (first bonding layer 51) of the first chip 21 in plan view. That is, the via 312 is formed to be offset from the gate electrode 221 in plan view. In the illustrated example, as shown in FIG. 12, the conductor pattern 310 has one end electrically connected to the IGBT gate electrode 221 of the second chip 22 through the bonding layer 52a and the other end electrically connected to the via 312. Connected to. In the illustrated example, two sets of conductor patterns 310 and vias 312 are formed, but the number of sets is arbitrary.

  The second conductor portion 32 is formed on the first insulating substrate 10. As shown in FIG. 6, the second conductor portion 32 includes a via (an example of a first through conductor portion) 324. The via 324 electrically connects the IGBT emitter electrode of the first chip 21 and the IGBT collector electrode of the second chip 22. The second conductor portion 32 is electrically connected to the output electrode 80 of the inverter 103. Incidentally, a traveling motor 104 (see FIG. 15) is electrically connected to the output electrode 80 of the inverter 103.

  In the illustrated example, the second conductor portion 32 includes a conductor pattern in addition to the via 324 as illustrated in FIGS. 5, 7, and 13. The conductor pattern includes a first pattern portion 321, a second pattern portion 322, and a third pattern portion 323. As shown in FIG. 5, the first pattern portion 321 is formed on the upper surface of the first insulating substrate 10 in a formation range corresponding to the bonding range (first bonding layer 51) of the first chip 21. As shown in FIGS. 7 and 13, the second pattern portion 322 has a formation range corresponding to the bonding range (second bonding layer 52) of the second chip 22, and the lower surface (second bonding layer) of the first insulating substrate 10. 52 + the thickness corresponding to the thickness of the second pattern portion 322, and the lower surface offset to the upper side in a concave shape. The second pattern portion 322 is opposed to the first pattern portion 321 in the up-down direction (overlapping in a top view). As shown in FIG. 5, the third pattern portion 323 is formed from the first pattern portion 321 and extends to the left outside the bonding range of the first chip 21. The via 324 penetrates the first insulating substrate 10 in the vertical direction. As shown in FIG. 6, a plurality of vias 324 are formed within the formation range of the first pattern portion 321 (= the formation range of the second pattern portion 322). In the example shown in the drawing, the plurality of vias 324 are arranged in a grid pattern in a top view, but may be arranged in other arrangement patterns (for example, in a staggered pattern).

  According to the present embodiment, since the first chip 21 and the second chip 22 are arranged above and below the first insulating substrate 10, the first chip 21 and the second chip 22 are electrically connected via the via 324. It becomes possible to connect, and the inductance between the first chip 21 and the second chip 22 can be reduced as compared with the case where the first chip 21 and the second chip 22 are arranged side by side in the left-right direction. Further, since the first conductor portion 31 electrically connected to the IGBT gate electrode 221 of the second chip 22 is formed on the first insulating substrate 10, it is easy to form the gate signal line from the gate electrode 221. . That is, since the first conductor portion 31 (element of the gate signal line) can be formed by forming a via or a wiring pattern on the first insulating substrate 10, a copper wire is bonded to the gate electrode 221 of the second chip 22 by wire bonding. As compared with the case where the gate signal line is formed, the formation of the gate signal line is facilitated. Further, since the second conductor portion 32 is formed on the first insulating substrate 10, it is easy to form a wiring for electrically connecting the first chip 21 and the second chip 22 to the output electrode 80 of the inverter 103. .

  Next, referring to FIGS. 1 to 14 again, further preferred features of the switching element unit 1 according to the illustrated example will be described.

  In the illustrated example, as shown in FIG. 12 and the like, the switching element unit 1 further includes a second insulating substrate 12, a third insulating substrate 13, an upper cover substrate 14, a lower cover substrate 15, a capacitor (smoothing capacitor). ) 40, a positive side bus bar (an example of a first bus bar) 60, and a negative side bus bar (an example of a second bus bar) 62.

  The second insulating substrate 12 is a substrate having an insulating property. In the illustrated example, the second insulating substrate 12 is formed of a ceramic substrate as an example. The second insulating substrate 12 is disposed on the upper side of the first insulating substrate 10. In the illustrated example, the lower surface of the second insulating substrate 12 is bonded to the upper surface of the first insulating substrate 10 via the first bonding layer 51 and the like.

  The second insulating substrate 12 has a cavity that accommodates the first chip 21. As shown in FIG. 3, the second insulating substrate 12 has a conductor layer (conductor pattern) that forms the positive-side bus bar 60. Further, as shown in FIG. 4 and the like, the second insulating substrate 12 has a space in which the capacitor 40 is mounted on the right side of the first chip 21.

  As shown in FIGS. 2 and 11, the second insulating substrate 12 has an output electrode 80, a first gate external electrode 91, and a second gate external electrode 92 formed on the upper surface. The output electrode 80, the first gate external electrode 91, and the second gate external electrode 92 may each be formed as a conductor pattern. The output electrode 80, the first gate external electrode 91, and the second gate external electrode 92 are formed in a region on the left side of the first chip 21 in plan view. In the illustrated example, the output electrode 80 is formed between the first gate external electrode 91 and the second gate external electrode 92 in the depth direction (a direction perpendicular to the vertical direction and the horizontal direction).

  As shown in FIGS. 3, 4, and 12, the second insulating substrate 12 is formed with a via 314 that penetrates the second insulating substrate 12. The via 314 is formed at a position corresponding to the via 312 of the first insulating substrate 10 in plan view. As shown in FIG. 12, the via 314 has a lower end electrically connected to the via 312 via the bonding layer 51a and an upper end electrically connected to the second gate external electrode 92. Thus, the gate electrode 221 of the second chip 22 is connected to the outside of the second gate on the upper surface of the second insulating substrate 12 via the bonding layer 52a, the conductor pattern 310, the via 312, the bonding layer 51a, and the via 314. It is electrically connected to the electrode 92. Since the second gate external electrode 92 is formed on the upper surface of the second insulating substrate 12, electrical connection with the outside (control device) is easy.

  As shown in FIGS. 3, 4, and 13, the second insulating substrate 12 is formed with a via (an example of a second through conductor) 802 that penetrates the second insulating substrate 12. The via 802 is formed at a position corresponding to the third pattern portion 323 of the first insulating substrate 10 in plan view. As shown in FIG. 13, the lower end of the via 802 is electrically connected to the third pattern portion 323 via the bonding layer 51 b, and the upper end is electrically connected to the output electrode 80. In this way, the IGBT emitter electrode of the first chip 21 (and the IGBT collector electrode of the second chip 22) is the second conductor portion 32 (the third pattern portion 323, etc.), the bonding layer 51b, and the via 802. Is electrically connected to the output electrode 80 on the upper surface of the second insulating substrate 12. Since the output electrode 80 is formed on the upper surface of the second insulating substrate 12, electrical connection with the outside (the traveling motor 104) is easy.

  As shown in FIGS. 3 and 14, the second insulating substrate 12 is formed with a via 318. The via 318 is formed at a position corresponding to the gate electrode 211 of the first chip 21 in plan view. As shown in FIG. 14, the via 318 has a lower end electrically connected to the gate electrode 211 via the bonding layer 54a and an upper end electrically connected to the first gate external electrode 91. In this way, the gate electrode 211 of the first chip 21 is electrically connected to the first gate external electrode 91 on the upper surface of the second insulating substrate 12 through the bonding layer 54a and the via 318. Since the first gate external electrode 91 is formed on the upper surface of the second insulating substrate 12, electrical connection with the outside (control device) is easy.

  The third insulating substrate 13 is a substrate having an insulating property. In the illustrated example, the third insulating substrate 13 is formed of a ceramic substrate as an example. The third insulating substrate 13 is disposed below the first insulating substrate 10. In the illustrated example, the upper surface of the third insulating substrate 13 is bonded to the lower surface of the first insulating substrate 10 via the second bonding layer 52 and the like.

  The third insulating substrate 13 has a cavity that accommodates the second chip 22. As shown in FIG. 9, the third insulating substrate 13 has a conductor layer (conductor pattern) that forms the negative-side bus bar 62. Further, in the third insulating substrate 13, as shown in FIG. 8 and the like, a space for mounting the capacitor 40 is formed on the right side of the second chip 22.

  The upper cover substrate 14 is an insulating substrate. In the illustrated example, the upper cover substrate 14 is formed of a ceramic substrate as an example. The upper cover substrate 14 is disposed on the upper side of the second insulating substrate 12. A conductor pattern 14a is formed on the upper cover substrate 14 as shown in FIG. The upper cover substrate 14 is bonded to the second insulating substrate 12 by bonding the conductor pattern 14 a to the positive bus bar 60 via the bonding layer 56. A cooling device (for example, a cooling device in which cooling water is circulated) may be thermally connected to the upper side of the upper cover substrate 14.

  The lower cover substrate 15 is an insulating substrate. In the illustrated example, the lower cover substrate 15 is formed of a ceramic substrate as an example. The lower cover substrate 15 is disposed below the third insulating substrate 13. A conductor pattern 15a is formed on the lower cover substrate 15 as shown in FIG. The lower cover substrate 15 is bonded to the third insulating substrate 13 by bonding the conductor pattern 15a to the negative electrode bus bar 62 via the bonding layer 57 (see FIG. 10). A cooling device (for example, a cooling device in which cooling water is circulated) may be thermally connected to the lower side of the lower cover substrate 15.

  Capacitor 40 is electrically connected between the positive electrode side (positive electrode side bus bar 60) and negative electrode side (negative electrode side bus bar 62) of inverter 103. The capacitor 40 is, for example, a ceramic capacitor. In the illustrated example, the capacitor 40 includes a dielectric part 41, a positive electrode (an example of a first electrode) 42, and a negative electrode (an example of a second electrode) 44, as shown in FIG. . The positive electrode 42 and the negative electrode 44 sandwich the dielectric part 41 from above and below. The positive electrode side electrode 42 is electrically connected to the positive electrode side bus bar 60 via the upper bonding layer 54 as shown in FIG. The negative electrode 44 is electrically connected to the negative bus bar 62 through the lower bonding layer 55 as shown in FIG.

  The capacitor 40 is disposed adjacent to the right side with respect to the first chip 21 and the second chip 22 as shown in FIG. For example, as shown in FIG. 12 and the like, the capacitor 40 is arranged away from the first chip 21 and the second chip 22 by a necessary insulation distance in the left-right direction. Thereby, the inductance between the capacitor 40 and the first chip 21 and the second chip 22 can be reduced.

  As illustrated in FIG. 12 and the like, the positive electrode side bus bar 60 is bonded to the collector electrode (surface electrode) of the first chip 21 and the upper surface of the positive electrode side electrode 42 of the capacitor 40 via the upper bonding layer 54. That is, the positive electrode bus bar 60 and the upper bonding layer 54 are provided in common to the collector electrode of the first chip 21 and the positive electrode 42 of the capacitor 40. Thereby, the inductance between the capacitor 40 and the first chip 21 can be efficiently reduced.

  As illustrated in FIG. 12 and the like, the negative electrode side bus bar 62 is bonded to the emitter electrode (surface electrode) of the second chip 22 and the lower surface of the negative electrode side electrode 44 of the capacitor 40 via the lower bonding layer 55. That is, the negative electrode side bus bar 62 and the lower bonding layer 55 are provided in common to the emitter electrode of the second chip 22 and the negative electrode side electrode 44 of the capacitor 40. The inductance between the capacitor 40 and the second chip 22 can be efficiently reduced.

  According to the further preferable feature of the switching element unit 1 according to the illustrated example as described above, the following effects can be achieved.

  According to the switching element unit 1 according to the illustrated example, the first chip 21 and the second chip 22 are bonded to the first insulating substrate 10 via the first bonding layer 51 and the second bonding layer 52, respectively. Thereby, for example, the dimensional tolerance in the vertical direction of the second insulating substrate 12 or the third insulating substrate 13 can be absorbed by the first bonding layer 51 and the second bonding layer 52, and the mountability is improved. Further, as described above, by using the first bonding layer 51 and the second bonding layer 52, compared to the configuration in which the first chip 21 and the second chip 22 are electrically connected to the first insulating substrate 10 by a spring, It becomes the structure which is easy to implement | achieve high electrical conductivity and high heat conductivity efficiently.

  According to the switching element unit 1 according to the illustrated example, the first chip 21 and the second chip 22 are electrically connected via the first bonding layer 51, the via 324 and the second bonding layer 52 of the first insulating substrate 10. Is done. Thereby, compared with the case where a single metal plate is used instead of the via 324 of the first insulating substrate 10, the difference in thermal expansion coefficient between the first chip 21 and the second chip 22 and the first insulating substrate 10. The thermal stress in the 1st joining layer 51 and the 2nd joining layer 52 resulting from this can be reduced. In particular, when a plurality of vias 324 are provided in a discrete manner as in the illustrated example, thermal stress can be reduced compared to the case where a single relatively large via is provided. Specifically, since the via 324 of the first insulating substrate 10 is a conductor, the thermal expansion coefficient is significantly higher than that of the first chip 21 and the second chip 22. However, since the size of each via 324 is not large, the individual expansion amount itself is relatively small. For this reason, the thermal stress in the 1st joining layer 51 and the 2nd joining layer 52 resulting from the difference of the thermal expansion coefficient between each via | veer 324 and the 1st chip | tip 21 and the 2nd chip | tip 22 can be reduced.

  According to the switching element unit 1 according to the illustrated example, the capacitor 40 is adjacent to the first insulating substrate 10 in the left-right direction (on the right side in the illustrated example). Thereby, since the inductance between the positive electrode 42 of the capacitor 40 and the first chip 21 is mainly only the inductance of the positive bus bar 60, the inductance can be reduced. Similarly, since the inductance between the negative electrode 44 of the capacitor 40 and the second chip 22 is mainly only the inductance of the negative bus bar 62, the inductance can be reduced.

  According to the illustrated switching element unit 1, the output electrode 80, the first gate external electrode 91, and the second gate external electrode 92 are provided on one end side (left end portion in the illustrated example) of the upper surface of the third insulating substrate 13. Are aggregated. This facilitates electrical connection between the output electrode 80, the first gate external electrode 91, and the second gate external electrode 92, and the outside. For example, the electrical connection between the first gate external electrode 91 and the second gate external electrode 92 and the outside (control device) is performed by using a control substrate formed of a flexible substrate as an upper surface of the third insulating substrate 13. It can be easily realized by disposing it at one end.

  Next, with reference to FIG. 15, an example of a motor drive system for an electric vehicle suitable for applying the switching element unit 1 will be described.

  FIG. 15 is a diagram illustrating an example of the overall configuration of the electric vehicle motor drive system 100.

  As shown in FIG. 15, the motor drive system 100 includes a battery 101, a DC-DC converter 102, an inverter 103, and a traveling motor 104.

  The switching element unit 1 can form any one of the three upper and lower arms of the inverter 103. Further, the capacitor 40 of the switching element unit 1 forms a smoothing capacitor C of the motor drive system 100. For example, the switching element unit 1 can form upper and lower arms related to the U phase of the inverter 103. In this case, the first chip 21 includes a switching element Q1 and a diode D1, and the second chip 22 includes a switching element Q2 and a diode D2. At this time, the output electrode 80 corresponds to the midpoint M1.

  Although each embodiment has been described in detail above, it is not limited to a specific embodiment, and various modifications and changes can be made within the scope described in the claims. It is also possible to combine all or a plurality of the components of the above-described embodiments.

For example, in the example shown,
In the illustrated example, a plurality of vias 324 are formed, but only one may be provided. In this case, the via 324 may be formed to have a volume (or a cross-sectional area) corresponding to the magnitude of the current to be handled. In this case, for example, the entire bonding range of the first chip 21 is covered by making the formation range (cross section) of the via 324 smaller than the bonding range of the first chip 21 (= the bonding range of the second chip 22). Compared with the case where it does, reduction of the thermal stress in the 1st joining layer 51 and the 2nd joining layer 52 is still possible. In this case, the via 324 may be replaced with a conductor material (for example, a metal piece) inserted in a manner penetrating the first insulating substrate 10.

  In the illustrated example, the switching element is an IGBT, but it may be another switching element such as a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).

  In the illustrated example, the switching element unit 1 includes one upper and lower arm of the inverter 103, but includes another upper and lower arm of another power conversion device (for example, the DC-DC converter 102 illustrated in FIG. 15). May be. For example, when the switching element unit 1 is applied to the upper and lower arms of the DC-DC converter 102, the output electrode 80 corresponds to the middle point M4 in FIG. 15 and the battery 101 is electrically connected via the inductance L. .

  In the illustrated example, the switching element unit 1 forms any one of the three upper and lower arms of the inverter 103. However, as described above, the switching element unit 1 allows all of the three upper and lower arms of the inverter 103 to be connected. It can also be included. In this case, for example, the switching element unit 1 may have a structure in which three structures shown in FIGS. 1 to 14 are arranged in parallel in the depth direction. In this case, only one capacitor 40 may be provided. In this case, the positive bus bar 60 and the negative bus bar 62 may be common to the upper and lower arms.

  In the illustrated example, two sets of the gate electrode 211 and the gate electrode 221 are illustrated, but only one set may be provided, or a larger number of sets may be provided. In addition, in parallel with the gate electrode 211 and the gate electrode 221, a signal terminal related to a sense emitter (for overcurrent detection) or a temperature sensor may be provided. In this case, the signal terminal can also be taken out in the same manner as the gate electrode 211 and the gate electrode 221.

  In the illustrated example, the switching element unit 1 includes the first insulating substrate 10, the second insulating substrate 12, and the third insulating substrate 13, but a part or all of the second insulating substrate 12 and / or the second insulating substrate 12. Part or all of the three insulating substrates 13 may be omitted. For example, when the second insulating substrate 12 and the third insulating substrate 13 are omitted, the output electrode 80, the first gate external electrode 91, and the second gate external electrode 92 are connected to one end side of the upper surface or the lower surface of the first insulating substrate 10 ( For example, it can be formed at the left end of the figure). Thereby, the electrical connection between the output electrode 80, the first gate external electrode 91, and the second gate external electrode 92 and the outside is still easy. In this case, the electrical connection between the first gate external electrode 91 and the gate electrode 211 can be realized by wire bonding or the like. In this case, a resin mold part may be formed by molding resin in the space formed by omitting the second insulating substrate 12 and the third insulating substrate 13.

  In the illustrated example, the output electrode 80, the first gate external electrode 91, and the second gate external electrode 92 are provided on the upper surface of the second insulating substrate 12, but the output electrode 80, the first gate external electrode 91, and the second gate external electrode 92 are provided. A part or all of the two-gate external electrode 92 may be provided elsewhere. For example, the output electrode 80, the first gate external electrode 91, and the second gate external electrode 92 may be provided on the lower surface of the third insulating substrate 13. The first gate external electrode 91 and the second gate external electrode 92 may be provided on the upper surface of the second insulating substrate 12, and the output electrode 80 may be provided on the lower surface of the third insulating substrate 13. Further, some or all of the output electrode 80, the first gate external electrode 91, and the second gate external electrode 92 may be provided at an end portion in the depth direction on the upper surface of the second insulating substrate 12 or the like.

  In the illustrated example, the second conductor portion 32 includes a first pattern portion 321, a second pattern portion 322, and a third pattern portion 323 in addition to the via 324, but is not limited thereto. When the via 324 is electrically connected to the third pattern portion 323 through the first bonding layer 51 in an appropriate manner, the first pattern portion 321 and the second pattern portion 322 may be omitted.

  In the illustrated example, the third pattern portion 323 is formed on the upper surface of the first insulating substrate 10 in a manner continuous with the first pattern portion 321, but is not limited thereto. For example, the third pattern portion 323 may be formed on the lower surface of the first insulating substrate 10 in a manner that is continuous with the second pattern portion 322. In this case, vias may be formed in the first insulating substrate 10, and the third pattern portion 323 may be electrically connected to the output electrode 80 via the vias and vias 802.

  In the illustrated example, each of the second insulating substrate 12 and the third insulating substrate 13 is an integrated multilayer substrate (a substrate formed by laminating layers of ceramic materials). The substrate 12 and / or the third insulating substrate 13 may be formed by a combination of a plurality of substrates. For example, the third insulating substrate 13 is formed by vertically bonding a first substrate having the negative-side bus bar 62 on the upper surface and a second substrate including the second chip 22 inside through the lower bonding layer 55. May be. The second insulating substrate 12 and / or the third insulating substrate 13 may be formed by bonding different substrates in the left-right direction. For example, the second insulating substrate 12 is formed by joining separate substrates in the left-right direction in a mode having a boundary between the capacitor 40 (for example, the left end of the capacitor 40) and the first chip 21 in the left-right direction. May be.

  In the example shown in the figure, the depth of the cavity for accommodating the first chip 21 in the second insulating substrate 12 is set so as to accommodate the first chip 21 and the first bonding layer 51. I can't. For example, FIG. 16 shows a cross-sectional view of a switching element unit 1B according to a modification. FIG. 16 shows a cross section of the switching element unit 1B corresponding to the cross section along the line XX in FIG. In the switching element unit 1B according to the modification shown in FIG. 16, the first bonding layer 51 forms a similar cavity (a cavity for the bonding agent that becomes the first bonding layer 51) on the first insulating substrate 10B side. , Formed on the first insulating substrate 10B side. That is, the vertical boundary between the first insulating substrate 10B and the second insulating substrate 12B may be moved upward. Alternatively, the first bonding layer 51 may be formed on both the first insulating substrate 10 and the second insulating substrate 12. Thus, the vertical boundary between the first insulating substrate 10B and the second insulating substrate 12B (the same applies to the vertical boundary between the first insulating substrate 10 and the third insulating substrate 13) is appropriately changed up and down. It may be further provided with unevenness (unevenness other than the illustrated unevenness) in the stacking direction.

In addition, the following is further disclosed regarding the above Example. The effects described below may not always be achieved. In addition, the effect related to the characteristic of the subordinate form is an effect related to the characteristic and an additional effect.
(1)
A first insulating substrate (10) having insulating properties;
A first chip (21) mounted on the first surface of the first insulating substrate (10) and including a first switching element forming an upper arm of the power converter;
A second chip (22) including a second switching element mounted on a second surface opposite to the first surface of the first insulating substrate (10) and forming a lower arm of the power converter;
A first conductor portion (31) formed on the first insulating substrate (10) and electrically connected to the gate electrode (221) of the second switching element;
A second conductor part (32) formed on the first insulating substrate (10) and electrically connected to the output electrode (80) of the power conversion device, the first conductor passing through the first insulating substrate (10) and first A switching element unit (1, 1B) including a second conductor part (32) including a first through conductor part (324) that electrically connects the chip (21) and the second chip (22).

According to the configuration described in (1), since the first chip (21) and the second chip (22) are disposed on the surfaces on both sides of the first insulating substrate (10), the first chip (21) and Compared with the case where the second chip (22) is arranged side by side on the same surface on one side of the first insulating substrate (10), the inductance between the first chip (21) and the second chip (22) is reduced. Reduction is possible. That is, the first chip (21) and the second chip (22) can be electrically connected by the first through conductor (324) at a distance substantially equal to the thickness of the first insulating substrate (10), and the inductance Can be reduced. Further, since the first conductor portion (31) is formed on the first insulating substrate (10), the gate signal line from the gate electrode (221) of the second switching element is formed using a copper wire. The gate signal line can be easily formed. As described above, according to the configuration described in (1), the formation of the gate signal line is facilitated while the inductance is reduced. Moreover, since the second conductor portion (32) is formed on the first insulating substrate (10), it is easy to form a wiring to the output electrode (80) of the power conversion device.
(2)
The first chip is formed between the first surface of the first insulating substrate (10) and the surface electrode on the side of the first chip (21) facing the first insulating substrate (10) and has conductivity. A first bonding layer (51) for bonding (21) to the first insulating substrate (10);
The second chip is formed between the second surface of the first insulating substrate (10) and the surface electrode on the side of the second chip (22) facing the first insulating substrate (10), having conductivity. The switching element unit (1, 1B) according to (1), further including a second bonding layer (52) for bonding (22) to the first insulating substrate (10).

According to the configuration described in (2), the first chip (21) and the second chip (22) are respectively connected to the first insulating layer (10) by the first bonding layer (51) and the second bonding layer (52). ), The dimensional tolerance in the stacking direction of the first chip (21), the second chip (22), and the first insulating substrate (10) as a whole is set as the first bonding layer (51) and the second chip (22). Absorption is possible by the bonding layer (52). Further, by using the first bonding layer (51) and the second bonding layer (52), the bonding area can be efficiently increased compared with the case of using a spring, and high electrical conductivity and high thermal conductivity can be efficiently achieved. Can be realized.
(3)
The switching element unit (1, 1B) according to (1) or (2), wherein a plurality of first through conductor portions (324) are formed discretely.

According to the configuration described in (3), by forming a plurality of the first through conductor portions (324), it is possible to handle a relatively large current that can be handled when driving the vehicle travel motor. Due to the difference in thermal expansion coefficient between the material of the first chip (21) and the second chip (22) and the first through conductor portion (324), the first bonding layer (51) and the second bonding layer (52 ) Can be efficiently reduced.
(4)
A capacitor (40) adjacent to the first insulating substrate (10) in a direction perpendicular to the perpendicular direction of the first insulating substrate (10);
A first bus bar (40) electrically connected to the first electrode (42) of the capacitor (40) and the surface electrode on the opposite side of the first chip (21) opposite to the first insulating substrate (10). 60)
The second bus bar (40) electrically connected to the second electrode (44) of the capacitor (40) and the surface electrode on the opposite side of the second chip (22) facing the first insulating substrate (10). 62) The switching element unit (1, 1B) according to any one of (1) to (3).

According to the configuration described in (4), the first bus bar (60) and the second bus bar (62) are shared by the capacitor (40), the first chip (21), and the second chip (22). It can be formed with a short distance, and the inductance between the capacitor (40) and the first chip (21) and the second chip (22) can be efficiently reduced.
(5)
A first conductor portion (31) and a first switching element are provided on the first surface side of the first insulating substrate (10), have insulating properties, and have a surface opposite to the first insulating substrate (10) side. The semiconductor device according to any one of (1) to (4), further including a second insulating substrate (12) having a gate external electrode (91.92) electrically connected to the gate electrode (211). Switching element unit (1, 1B).

According to the configuration described in (5), the gate signal lines from the gate electrode of the first chip (21) and the gate electrode of the second chip (22) are connected to the outside of the gate on the surface of the second insulating substrate (12). It can be easily taken out through the electrode (91.92). That is, since the gate external electrode (91.92) is provided on the surface of the second insulating substrate (12) (surface opposite to the first insulating substrate (10) side), the gate external electrode (91.92) and Electrical connection with the outside (for example, a control board) becomes easy.
(6)
The output electrode (80) is provided on the surface of the second insulating substrate (12) opposite to the first insulating substrate (10) side,
A second through conductor portion (802) that penetrates the second insulating substrate (12) and is electrically connected to the output electrode (80);
The second conductor portion (32) is formed on the first surface of the first insulating substrate (10) and electrically connects the second through conductor portion (12) and the first through conductor portion (10). The switching element unit (1, 1B) according to claim 5, comprising (323).

According to the configuration described in (6), since the output electrode (80) is provided on the surface of the second insulating substrate (12) (surface opposite to the first insulating substrate (10) side), the output electrode ( 80) can be easily electrically connected to the outside (for example, a traveling motor). In addition, since the wiring from the first chip (21) and the second chip (22) to the output electrode (80) can be formed on the first insulating substrate (10) and the second insulating substrate (12), the formation of the same wiring is possible. It becomes easy.
(7)
The power converter is an inverter (103) for driving the vehicle travel motor (104),
The switching element unit (1, 1B) according to any one of (1) to (6), wherein the output electrode (80) is electrically connected to the vehicle travel motor (104).

  According to the switching element unit (1, 1B) described in any one of (1) to (6), the inductance can be reduced as described above. Even when used in the inverter (103) for driving the vehicle travel motor (104), the surge voltage is likely to be relatively high, the surge voltage can be suppressed.

1 switching element unit 10 first insulating substrate
12 Second insulating substrate
13 Third insulating substrate
14 Top cover board
15 Lower cover board
21 First chip
22 Second chip
31 1st conductor part
32 2nd conductor part
40 capacitors
41 Dielectric part 42 Positive electrode side electrode 44 Negative electrode side electrode 51 1st joining layer
52 Second bonding layer
60 Positive side bus bar
62 Negative side bus bar
80 output electrode
91 1st gate external electrode
92 Second gate external electrode
211 Gate electrode
221 Gate electrode
312 Via
321 First pattern part
322 Second pattern part
323 Third pattern part

Claims (7)

A first insulating substrate having insulating properties;
A first chip including a first switching element mounted on a first surface of the first insulating substrate and forming one of upper and lower arms of a power converter;
A second chip including a second switching element mounted on the second surface opposite to the first surface of the first insulating substrate and forming the other of the upper and lower arms of the power converter;
A first conductor formed on the first insulating substrate and electrically connected to a gate electrode of the second switching element;
A second conductor portion formed on the first insulating substrate and electrically connected to an output electrode of the power converter, and penetrating the first insulating substrate between the first chip and the second chip; And a second conductor portion including a first through conductor portion that is electrically connected. The first insulating substrate is formed between the first surface of the first insulating substrate and a surface electrode on the first insulating substrate side of the first chip, and has conductivity, and the first chip is used as the first insulating substrate. A first bonding layer to be bonded;
The first insulating substrate is formed between the second surface of the first insulating substrate and a surface electrode on the first insulating substrate side of the second chip, and has conductivity, and the second chip is used as the first insulating substrate. The switching element unit according to claim 1, further comprising a second bonding layer to be bonded.   The switching element unit according to claim 1, wherein a plurality of the first through conductor portions are discretely formed. A capacitor adjacent to the first insulating substrate in a direction perpendicular to the direction perpendicular to the surface of the first insulating substrate;
A first bus bar electrically connected to a first electrode of the capacitor and a surface electrode of the first chip opposite to the first insulating substrate;
4. The device according to claim 1, further comprising: a second bus bar electrically connected to a second electrode of the capacitor and a surface electrode of the second chip opposite to the first insulating substrate side. The switching element unit according to any one of claims.   Provided on the first surface side of the first insulating substrate, has an insulating property, on the surface opposite to the first insulating substrate side, on the first conductor portion and the gate electrode of the first switching element The switching element unit according to claim 1, further comprising a second insulating substrate having an external electrode that is electrically connected. The output electrode is provided on a surface of the second insulating substrate opposite to the first insulating substrate;
A second through conductor portion that penetrates the second insulating substrate and is electrically connected to the output electrode;
The said 2nd conductor part is formed in the said 1st surface of the said 1st insulated substrate, The conductor pattern which electrically connects the said 2nd through-conductor part and the said 1st through-conductor part is included in Claim 5. The switching element unit described. The power converter is an inverter for driving a vehicle travel motor,
The switching element unit according to claim 1, wherein the output electrode is electrically connected to the vehicle travel motor.

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