JP2016167916A - Parallel inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve exact detection of erroneous wiring.SOLUTION: A parallel inverter device 4 includes: a current polarity determination part 45a for determining a polarity of an output current Iof at least one phase in at least one inverter device 41a of a plurality of inverter devices 41a, 41b; a control part 48a for detecting erroneous wiring involved in wiring to a load device on the basis of a polarity determined by the current polarity determination part 45a; and an output part 49a for outputting information indicating the erroneous wiring detected by the control part 48a.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a parallel inverter device in which a plurality of inverter devices that output AC power to a load device are connected in parallel.

  Conventionally, it is known that a plurality of inverter devices are connected in parallel and used for an inverter device that converts DC power supplied from a power generation device, a storage battery, or the like into AC power and supplies it to a load device such as a motor. .

  When using a plurality of inverter devices connected in parallel, a three-phase output from one inverter of the plurality of inverter devices and a three-phase output from another inverter are connected in phase order using a cable. . At this time, each cable is routed through wiring connection parts such as terminal blocks of each inverter device. However, when these cables are wired, incorrect wiring such as incorrect phase sequence or unconnected is left. May occur. If the inverter is operated in a state where such erroneous wiring has occurred, an excessive current may flow through the load device, causing the load device to fail or be destroyed.

  As described above, in order to prevent the load device from being damaged due to an excessive current flowing in the load device due to the incorrect wiring, the cable wiring for connecting the plurality of inverter devices in parallel is erroneous. A technique for detecting wiring is known.

  For example, in Patent Document 1, as shown in FIG. 3, in a plurality of inverter devices 100 connected in parallel (hereinafter referred to as “parallel inverter device 100”), an error from the load device 320 to the terminal blocks 800a and 800b is disclosed. The parallel inverter device 100 is connected to a DC power source 310 and a load device 320. The parallel inverter device 100 includes two inverter devices 200, each of which is connected to a DC power source 310 and a load device 320. The first inverter device 200a and the second inverter device 200b are referred to.

The first inverter device 200a includes a smoothing capacitor 400a, a voltage detection unit 500a, a current detection unit 600a, a control unit 700a, a terminal block 800a, a transmission unit 900a, semiconductor switching elements Q ′ _{1a to} Q ′ _6a , and a rectifying element D ′ _1a. ˜D ′ _6a , and a gate drive circuit (not shown). Smoothing capacitor 400a is connected to DC power supply 310 in parallel. Further, the semiconductor switching elements Q ′ _1a and Q ′ _2a are connected in series with each other and in parallel with the capacitor 400a. Similarly, the semiconductor switching elements Q ′ _3a and Q ′ _4a are connected in series with each other and in parallel with the capacitor 400a. The semiconductor switching elements Q ′ _5a and Q ′ _6a are connected in series with each other and in parallel with the capacitor 400a.

The second inverter device 200b has the same electrical configuration as that of the first inverter device 200a. That is, the second inverter device 200b includes a smoothing capacitor 400b, a voltage detection unit 500b, a current detection unit 600b, a control unit 700b, a terminal block 800b, a transmission unit 900b, semiconductor switching elements Q ′ _{1b to} Q ′ _6b , and a rectifying element D. ' _{1b to} D' _6b and a gate driving circuit (not shown). Smoothing capacitor 400b is connected to DC power supply 310 in parallel. The semiconductor switching elements Q ′ _{1b to} Q ′ _6b are connected in parallel to the capacitor 400b in the same manner as the semiconductor switching elements Q ′ _{1a to} Q ′ _6a .

  The voltage detection units 500a and 500b detect the output voltages of the first inverter device 200a and the second inverter device 200b, respectively. The current detection units 600a and 600b detect output currents of the first inverter device 200a and the second inverter device 200b, respectively.

The controllers 700a and 700b generate gate signals of the semiconductor switching elements Q ′ _{1a to} Q ′ _6a and Q ′ _{1b to} Q ′ _6b based on the information representing the detected output voltage and output current. By this gate signal, AC power is output from the first inverter device 200a and the second inverter device 200b, and supplied to the load device 320 via the terminal blocks 800a and 800b, respectively.

  In the parallel inverter device 100 configured as described above, the transmission units 900a and 900b are detected by the voltage detection unit 500b and information indicating the output voltage of each phase of the first inverter device 200a detected by the voltage detection unit 500a. Information indicating the output voltage of each phase of the second inverter device 200b is mutually transmitted and received, and the control units 700a and 700b detect them by comparing them.

JP 2013-113695 A

  However, when detecting an incorrect wiring in the parallel inverter device 100 described in Patent Document 1, if the wiring connecting the first inverter device 200a and the second inverter device 200b and the load device 320 is long, leakage occurs. There is a problem that noise due to current occurs and the output voltage of each of the first inverter device 200a and the second inverter device 200b cannot be measured accurately, and therefore, incorrect wiring cannot be detected based on the output voltage. Has occurred.

  Therefore, an object of the present invention made in view of such a point is to detect an incorrect wiring accurately even if the wiring connecting the first inverter device and the second inverter device and the load device is long. An object of the present invention is to provide a parallel inverter device that enables this.

  In order to solve the above-mentioned problem, a parallel inverter device according to the present invention is a parallel inverter device in which a plurality of inverter devices that output AC power to a load device are connected in parallel, and among the plurality of inverter devices A current polarity discriminating unit for discriminating the polarity of the output current of at least one phase of the at least one inverter device, and miswiring related to wiring to the load device based on the polarity discriminated by the current polarity discriminating unit And a control unit for detecting the wiring and an output unit for outputting information representing an erroneous wiring detected by the control unit.

  In the parallel inverter device according to the present invention, each of the plurality of inverter devices includes the current polarity determination unit, and the current polarity determination unit of the first inverter device and the current polarity determination unit of the second inverter device; Discriminates the polarity of the output current for the same phase, and the control unit discriminates the polarity discriminated by the current polarity discriminating unit of the first inverter device and the current polarity discriminating unit of the second inverter device. The miswiring is detected based on the detected polarity.

  Further, in the parallel inverter device according to the present invention, the first inverter device includes the control unit, and the second inverter device receives information indicating a polarity of an output current of the second inverter device as a first information. A second transmission unit configured to transmit to the inverter device, wherein the first inverter device receives information indicating a polarity of an output current of the second inverter device from the second transmission unit; A transmission unit, wherein the control unit is different from the polarity according to the information transmitted by the second transmission unit and the polarity determined by the current polarity determination unit of the first inverter device, It is characterized by detecting erroneous wiring.

  In the parallel inverter device according to the present invention, the control unit detects an incorrect wiring when the polarity does not change for a predetermined period.

  According to the present invention, even if the wiring connecting the first inverter device, the second inverter device, and the load device is long, it is possible to accurately detect erroneous wiring.

It is a circuit diagram which shows the electrical constitution of a parallel inverter system provided with the parallel inverter apparatus which concerns on one Embodiment of this invention. It is a circuit diagram which shows the electrical constitution of the current polarity discrimination | determination part of the parallel inverter apparatus shown in FIG. It is a circuit diagram which shows the electric constitution of the conventional parallel inverter system.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

<Configuration of parallel inverter system>
First, the structure of the parallel inverter system 1 of this embodiment is demonstrated using FIG.

  The parallel inverter system 1 includes a load device 2, a DC power source 3, and a parallel inverter device 4 as shown in FIG.

  The load device 2 is connected to each of the first inverter device 41a and the second inverter device 41b included in the parallel inverter device 4, and receives AC power output from each. An example of the load device 2 is a three-phase AC motor.

  The parallel inverter device 4 includes a first inverter device 41a and a second inverter device 41b, which are a plurality of inverter devices, and the first inverter device 41a and the second inverter device 41b are connected in parallel to each other. An example of the first inverter device 41a and the second inverter device 41b is a three-phase PWM voltage type inverter circuit.

The first inverter 41a, the semiconductor switching element _Q 1a _{to Q 6a,} rectifier element _(diode) D 1a _{to D 6a,} a smoothing capacitor 42a, a shunt resistor 43a, the current detecting circuit 44a, a current polarity determination portion 45a, the terminal block 46a The 1st transmission part 47a and the control part 48a are provided.

The semiconductor switching elements Q _{1a to} Q _6a are realized by an IGBT or the like, and when turned on, current flows or when turned off, current does not flow.

The rectifier elements D _{1a to} D _6a are connected in antiparallel to the semiconductor switching elements Q _{1a to} Q _6a , respectively, and control the direction in which current flows.

Smoothing capacitor 42a smoothes the control input current by the rectifying element _D 1a _{to D 6a.}

  The shunt resistor 43 a is a resistor connected in series with the DC power supply 3.

  The current detection circuit 44a measures an input current input from the DC power source 3 to the first inverter device 41a. Specifically, the current detection circuit 44a measures the voltage across the shunt resistor 43a, and detects the input current based on the measured voltage and the resistance value of the shunt resistor 43a.

  The current polarity determination unit 45a determines the polarity of the output current of at least one phase of the first inverter device 41a. The polarity of the output current is information indicating whether the output current flows from the output side or from the output side. In the following description, the output current flowing to the output side is referred to as “polarity is positive”, and the output current flowing from the output side is referred to as “polarity is negative”.

  As illustrated in FIG. 2, the current polarity determination unit 45a includes a rectifying element 51a, a transistor 52a, a capacitor 53a, and a resistor 54a.

Rectifying element 51a is connected in parallel to the rectifying element _{D 2a} via the transistor 52a. Specifically, the cathode of the rectifying element 51a is connected to the cathode of the rectifying element D _2a.

The emitter of the transistor 52a is connected to the anode of the rectifying element 51a, the base of the transistor 52a is connected to the anode of the rectifying element _{D 2a.}

  Capacitor 53a is connected between power supply Vcc and the collector of transistor 52a.

  The resistor 54a is connected in parallel with the capacitor 53a between the power supply Vcc and the collector of the transistor 52a.

Here, a method by which the current polarity determination unit 45a determines the polarity of the output current I _ua will be described.

When the polarity of the output current I _ua is positive, a current flows from the anode side to the cathode side in the rectifying element D _2a regardless of whether the semiconductor switching element Q _2a is ON or OFF.

Therefore, a forward voltage is generated at both ends of the rectifying element _D2a shown in FIG. 2, and a base current flows through the transistor 52a. The transistor 52a is turned on by this base current, and a current flows from the power supply Vcc through the resistor 54a. That is, the potential at the output point 55a is lower than the power supply Vcc (hereinafter referred to as “L level potential”), for example, 0V.

When the polarity of the output current I _ua is negative and the semiconductor switching element Q _2a is on, a current in the direction opposite to that of the rectifying element D _2a flows through the semiconductor switching element Q _2a . Thus, reverse voltage is generated in the rectifying element D _2a, no current flows through the rectifying element D _2a.

In addition, when the polarity of the output current I _ua is negative and the semiconductor switching element Q _2a is off, a current flows through the rectifying element D _1a and no current flows through the rectifying element D _2a .

That is, when the polarity of the output current I _ua is negative, no current flows through the rectifying element D _2a regardless of whether the semiconductor switching element Q _2a is on or off. Therefore, no base current flows through the transistor 52a of the current polarity discriminating unit 45a, and the transistor 52a is turned off. Therefore, no current flows from the power source Vcc through the resistor 54a. That is, the potential at the output point 55a is the same as the power supply Vcc (hereinafter referred to as “H level potential”).

As described above, when the polarity of the output current I _ua is positive, the output point 55a is at the L level, and when the polarity of the output current I _ua is negative, the output point 55a is at the H level. For this reason, the current polarity discriminating unit 45a can discriminate the polarity of the output current _Iua by measuring the potential level of the output point 55a.

As described in FIG. 1, the terminal block 46 a is a wiring connection part that receives a cable for supplying output power from the first inverter device 41 a to the load device 2. A wiring for supplying the output current I _ua converted by the first inverter device 41a is connected to the inside of the terminal block 46a, and a cable for connecting to the load device 2 is received on the outside of the terminal block 46a.

The 1st transmission part 47a is transmitted from the 2nd transmission part 47b with which the 2nd inverter apparatus 41b is similarly provided with the information which shows the polarity of the output current _Iub of the 2nd inverter apparatus 41b.

The control unit 48a is realized by an arithmetic processing device such as a CPU and various electric circuits. Further, the control unit 48a detects an incorrect wiring related to the wiring to the load device 2 based on the polarity determined by the current polarity determination unit 45a. Thereafter, the presence / absence of erroneous wiring is determined based on the polarity of the U-phase output current I _ua determined by the current polarity determination unit 45a and the change thereof, and the semiconductor switching elements Q _{1a to} Q _6a are controlled based on the determination. An example will be described in detail.

Control unit 48a is realized by a wiring judgment circuit 481a, an information representative of the polarity of the output current _{I ua} of U-phase is determined by the current polarity determination portion 45a, the first transmission section 47a from the second transmission unit 47b Based on the transmitted information indicating the polarity of the U-phase output current I _ub of the second inverter device 41b, the miswiring associated with the U-phase is detected. Specifically, the controller 48a changes the polarity of the U-phase output current I _ua of the first inverter device 41a or the polarity of the U-phase output current I _ub of the second inverter device 41b for a predetermined period. If there is no error, an incorrect wiring is detected.

In addition, the control unit 48a detects a miswiring when the polarity of the U-phase output current I _ua of the first inverter device 41a is different from the polarity of the U-phase output current I _ub of the second inverter device 41b. To do. In addition, the control unit 48a determines that the U phase output current I _ua of the first inverter device 41a is the same as the U phase output current I _ub of the second inverter device 41b. The cable for supplying the output current I _ua to the load device 2 and the cable for supplying the output current I _ub to the load device 2 are determined to be correctly wired, and no miswiring is detected.

The control unit 48a, when faulty wiring is detected, stops the output of the gate signal to turn off all the semiconductor switching elements _Q 1a _{to Q 6a} and _Q 1b _{to Q 6b.}

  When an erroneous wiring is detected by the control unit 48a, the output unit 49a outputs information representing the detected erroneous wiring. Specifically, the output unit 49a displays information indicating that there is a miswiring detected by the control unit 48a on a display unit (not shown) or an external display device, or to other devices via a communication network or cable. Or send.

The second inverter 41b, a semiconductor switching element _Q 1b _{to Q 6b,} the rectifying element _D 1b _{to D 6b,} a smoothing capacitor 42b, the shunt resistor 43 b, a current detecting circuit 44b, a current polarity determination unit 45b, the terminal block 46b, second Transmission section 47b, control section 48b, and output section 49b. These are the semiconductor switching elements Q _{1a to} Q _6a , the rectifying elements D _{1a to} D _6a , the smoothing capacitor 42a, the shunt resistor 43a, the current detection circuit 44a, the current polarity determination unit 45a, and the terminal block 46a, respectively, of the first inverter device 41a. The same as the first transmission unit 47a, the control unit 48a, and the output unit 49a.

The current polarity determination unit 45a of the first inverter device 41a and the current polarity determination unit 45b of the second inverter device 41b determine the polarity of the output current for the same phase. That is, when the current polarity determination unit 45a determines the polarity of the U-phase output current _Iua of the first inverter device 41a as described above, the current polarity determination unit 45b outputs the U-phase output of the second inverter device 41b. The polarity of the current I _ub is determined.

The second transmission unit 47b transmits information representing the polarity of the output current _Iub determined by the current polarity determination unit 45b to the first inverter device 41a.

As described above, in the parallel inverter unit 4 described in this embodiment, without using a current detector for detecting an output current I _ua, for determining the presence or absence of faulty wiring on the basis of the polarity of the output current I _ua Even if the wiring connecting the first inverter device 41a and the second inverter device 41b and the load device 2 is long, it is possible to accurately detect the incorrect wiring.

Further, in the parallel inverter device 4 described in the present embodiment, in order to detect the output current I _ua , a rectifying element 51a, a transistor 52a, a capacitor 53a, and a resistor 54a are used instead of a current detection unit that detects a current value. The provided current polarity discrimination unit 45a is used. Since these circuit elements included in the current polarity determination unit 45a are smaller than the current detection unit, it is possible to prevent the parallel inverter device 4 from becoming large.

In the present embodiment, the polarity of the U-phase output current I _ua of the first inverter device 41a and the U-phase output current I _ub of the second inverter device 41b are discriminated to detect erroneous wiring. The polarity of the V-phase output current _IVa of the first inverter device 41a and the polarity of the V-phase output current _IVb of the second inverter device 41b may be determined to detect miswiring. Similarly, the polarity of the W-phase output current _Iwa of the first inverter device 41a and the W-phase output current _Iwb of the second inverter device 41b may be determined to detect miswiring.

  Also, the wiring may be detected by determining the polarity of the output power of two or more phases of the output currents of the U phase, V phase, and W phase.

  Further, in the present embodiment, the process in which the control unit 48a of the first inverter device 41a detects erroneous wiring has been described. However, the control unit 48b of the second inverter device 41b similarly detects erroneous wiring. Also good. Note that either the control unit 48a or the control unit 48b may detect an incorrect wiring, or one of them may detect an incorrect wiring.

  Further, in the present embodiment, the output unit 49a of the first inverter device 41a has been described with respect to the process of outputting information representing the incorrect wiring detected by the control unit 48a. However, the output unit 49b of the second inverter device 41b is described. Similarly, information representing an erroneous wiring detected by the control unit 48b may be output. Note that either the output unit 49a or the output unit 49b may output, or either one may output.

  Moreover, although this embodiment demonstrated the parallel inverter apparatus 4 provided with two inverter apparatuses, the parallel inverter apparatus 4 may be provided with three or more inverter apparatuses. In this case, the control unit of at least one or more inverter devices detects miswiring based on the polarity of the current of the same phase for each inverter device.

  Although the above embodiment has been described as a representative example, it will be apparent to those skilled in the art that many changes and substitutions can be made within the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited by the above-described embodiments, and various modifications and changes can be made without departing from the scope of the claims.

DESCRIPTION OF SYMBOLS 1 Parallel inverter system 2 Load apparatus 3 DC power supply 4 Parallel inverter apparatus 41a 1st inverter apparatus 41b 2nd inverter apparatus 42a, 42b Smoothing capacitor 43a, 43b Shunt resistance 44a, 44b Current detection circuit 45a, 45b Current polarity discrimination | determination part 46a , 46b Terminal block 47a First transmission unit 47b Second transmission unit 48a, 48b Control unit 49a, 49b Output unit 51a Rectifier element 52a Transistor 53a Capacitor 54a Resistance 55a Output points 481a, 481b Wiring determination circuit

Claims (4)

A parallel inverter device in which a plurality of inverter devices that output AC power to a load device are connected in parallel,
A current polarity determination unit for determining the polarity of the output current of at least one phase of at least one of the plurality of inverter devices;
Based on the polarity determined by the current polarity determination unit, a control unit for detecting an incorrect wiring related to the wiring to the load device;
An output unit that outputs information representing the erroneous wiring detected by the control unit;
A parallel inverter device comprising: The parallel inverter device according to claim 1,
Each of the plurality of inverter devices includes the current polarity determination unit,
The current polarity determination unit of the first inverter device and the current polarity determination unit of the second inverter device determine the polarity of the output current for the same phase,
The control unit detects the miswiring based on the polarity determined by the current polarity determination unit of the first inverter device and the polarity determined by the current polarity determination unit of the second inverter device. A parallel inverter device characterized by that. The parallel inverter device according to claim 2,
The first inverter device includes the control unit;
The second inverter device includes a second transmission unit that transmits information representing the polarity of the output current of the second inverter device to the first inverter device,
The first inverter device includes a first transmission unit that transmits information indicating a polarity of an output current of the second inverter device from the second transmission unit,
The control unit detects the miswiring when the polarity according to the information transmitted by the second transmission unit is different from the polarity determined by the current polarity determination unit of the first inverter device. A parallel inverter device characterized by that. In the parallel inverter apparatus as described in any one of Claims 1-3,
The parallel inverter apparatus, wherein the control unit detects an incorrect wiring when the polarity does not change for a predetermined period.

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