JP2016103723A - Interface device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device that allows a microcomputer and an audio apparatus which can cope with bit slots different from each other to communicate with each other.SOLUTION: An interface device 1 comprises: DFF 2 that reverses an LR clock signal output by a microcomputer 101 and outputs a reversed LR clock signal; DFF 3 that divides the reversed LR clock signal output by the DFF 2 and outputs a division LR clock signal; a division LR clock line LRCK' that connects the DFF 3 and a MEMS microphone 102; and a data line DATA that connects the microcomputer 101 and the MEMS microphone 102, and the MEMS microphone 102 serially outputs audio data.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an interface device that connects a microcomputer and an audio device that serially outputs audio data to the microcomputer.

  In some cases, the microcomputer and the audio device communicate with each other in accordance with a communication method called I2S (see, for example, Patent Document 1). 10 and 11 are diagrams for explaining communication according to I2S. Here, a MEMS (Micro Electro Mechanical Systems) microphone 202 is illustrated as an audio device. The microcomputer 201 outputs an LR clock signal having a desired sampling frequency to the LR clock line LRCK, and gives the LR clock signal to the MEMS microphone 202. Further, the microcomputer 201 outputs, for example, a 64-bit bit clock signal to the bit clock line BCLK for one cycle of the LR clock signal, and gives the MEMS microphone 202 a bit clock signal. The number of bit clock signals per cycle of the LR clock signal is referred to as “bit slot”.

  When the MEMS microphone 202 is the stereo microphone shown in FIG. 10A, as shown in FIG. 10B, in communication according to I2S, the L channel audio is synchronized with the low level of the LR clock signal. Data is output to the data line DATA. The MEMS microphone 202 outputs R channel audio data to the data line DATA in synchronization with the high level of the LR clock signal. When outputting the audio data of the L channel 24 bits (valid data) and the R channel 24 bits (valid data), the MEMS microphone 202 outputs the 24-bit audio data, and then outputs the data line DATA to the high impedance (Hi-Z). ) And release. The audio data is shifted by 1 bit from the edge of the LR clock signal.

  When the MEMS microphone 202 is the monaural microphone shown in FIG. 11A, as shown in FIG. 11B, in communication according to I2S, the L channel audio is synchronized with the low level of the LR clock signal. Data is output to the data line DATA. Thereafter, the MEMS microphone 202 opens the data line DATA with high impedance (Hi-Z).

JP 2013-026295 A

  Here, the microcomputer may support a 32-bit slot, but may be an inexpensive one that cannot support a 64-bit slot. Such a microcomputer cannot communicate with an audio device compatible with a 64-bit slot. However, in order to reduce costs, it is desirable that such a microcomputer can communicate with audio equipment.

  An object of the present invention is to provide an apparatus that enables communication between a microcomputer and an audio device having different compatible bit slots.

  An interface apparatus according to a first aspect of the present invention is an interface apparatus for connecting a microcomputer and an audio device that serially outputs audio data to the microcomputer and that is compatible with the microcomputer and having different bit slots. A frequency dividing circuit that divides an LR clock signal output from a computer and outputs a frequency-divided LR clock signal, a frequency-divided LR clock line that connects the frequency-dividing circuit and the audio device, the microcomputer, and the audio A data clock for connecting the device, a bit clock line for the microcomputer to output a bit clock signal, the microcomputer and the audio device, and the audio device for serially outputting the audio data. Characterized in that it comprises a down, a.

  For example, assume that the microcomputer is compatible with a 32-bit slot. Also, for example, assume that an audio device is compatible with a 64-bit slot. In the present invention, the frequency dividing circuit divides the LR clock signal output from the microcomputer and outputs the divided LR clock signal. Here, it is assumed that the microcomputer outputs an LR clock signal having a sampling frequency twice as high as desired. Further, it is assumed that the microcomputer outputs a bit clock signal of a 32-bit slot having a sampling frequency twice as high as desired.

  The LR clock signal having a double sampling frequency is divided by a frequency dividing circuit. For this reason, the LR clock signal (frequency-divided LR clock signal) divided by the frequency dividing circuit is input to the audio device as the LR clock signal that can be handled by the audio device. Here, a bit clock signal of 32 bits per cycle of the LR clock signal is input to the audio device. Therefore, a 64-bit bit clock signal is input to the audio device in one cycle of the divided LR clock signal. Therefore, the audio device can output audio data to the microcomputer corresponding to the LR clock signal and the bit clock signal output from the microcomputer via the interface device.

  As described above, according to the present invention, communication can be performed between a microcomputer and an audio device having different bit slots that can be handled.

  An interface device according to a second aspect of the present invention is the interface device according to the first aspect, further comprising a resistor connecting the frequency-divided LR clock line and the data line.

  As described above, the microcomputer outputs an LR clock signal having a desired double sampling frequency. For this reason, the L-channel audio data is input to the microcomputer in synchronization with the outputted one-cycle LR clock signal. The R channel audio data is input to the microcomputer in synchronization with the output LR clock signal of one cycle. Therefore, there is a problem that the microcomputer cannot discriminate between the L channel and R channel audio data. Therefore, in the present invention, the frequency-divided LR clock line that connects the frequency-dividing circuit and the audio device and the data line are connected by a resistor.

  Assume that the audio device outputs audio data of L channel 24 bits (valid data) and R channel 24 bits (valid data). After outputting 24-bit audio data, the audio device opens the data line with high impedance. Here, the frequency-divided LR clock line and the data line are connected by a resistor. For this reason, for example, in the left-justified format, after the L-channel 24-bit audio data is output, the divided frequency output to the divided LR clock line until the R-channel audio data is output. “11111111b” is output by the LR clock signal. All 8 bits are set to “1” by the high-level divided LR clock signal.

  Further, for example, in the left-justified format, the divided LR output to the divided LR clock line until the L channel audio data is output after the R channel 24-bit audio data is output to the data line. “00000000b” is output by the clock signal. All 8 bits are set to “0” by the low-level divided LR clock signal.

  As described above, after the L-channel 24-bit audio data is output to the data line, until the R-channel audio data is output, the frequency-divided LR clock signal is output to the frequency-divided LR clock line. “11111111b” is output. Accordingly, the microcomputer takes in the L channel audio data (effective data 24 bits) + “11111111b” (8 bits). In addition, after the R channel 24-bit audio data is output to the data line, until the L channel audio data is output, “00000000b” is output by the frequency-divided LR clock signal output to the frequency-divided LR clock line. Is output. Therefore, the microcomputer captures R channel audio data (valid data 24 bits) + “00000000b” (8 bits). In the captured 32-bit data, the microcomputer can determine whether the audio data is L channel or R channel from the 8-bit pattern (“11111111b”, “00000000b”) from the LSB of the audio data. . Further, the microcomputer can acquire audio data of L channel or R channel of 24 bits as effective data by shifting the captured data by 8 bits to the right.

  Audio data is output to the data line in the order of L channel and R channel. Therefore, if the microcomputer determines whether the audio data is the L channel or the R channel, it can determine whether the continuous data is the audio data of the L channel or the R channel.

  An interface device according to a third aspect of the present invention is the interface device according to the first or second aspect, further comprising an inverting circuit that inverts the LR clock signal output from the microcomputer and outputs an inverted LR clock signal. The circuit divides the inverted LR clock signal output from the inversion circuit and outputs the divided LR clock signal instead of the LR clock signal output from the microcomputer.

  In communication according to I2S, the audio device outputs L-channel audio data to the microcomputer in synchronization with the low level of the LR clock signal. The audio device outputs R channel audio data to the microcomputer in synchronization with the high level of the LR clock signal. A microcomputer normally captures audio data in pairs of L channel and R channel in the order of L channel and R channel. The frequency divider using the D-type flip-flop takes in the logic of the inverting output terminal at the rising edge of the signal and inverts the logic of the output terminal and the inverting output terminal. The period corresponding to the L channel and R channel of the LR clock signal corresponds to the period of the high level and low level of the LR clock signal, and the timing at which the logic of the LR clock signal is inverted is 32 bits of the microcomputer. It occurs in the middle of the slot. When the audio device outputs audio data in the order of the R channel and the L channel in synchronization with this, the microcomputer receives 24-bit data starting from the latter half of the 32-bit slot. That is, since the first 16 bits are received as the R channel and the latter 8 bits are received as the L channel of the next sample, the program becomes complicated and may cause a bug.

  Therefore, in the present invention, the LR clock signal is inverted by the inverting circuit, and the inverted LR clock signal is divided by the frequency dividing circuit. As a result, the logic of the frequency-divided LR clock signal output from the frequency divider circuit changes when the LR clock signal falls, and both the low-level period and the high-level period correspond to the 32-bit slot period of the microcomputer. To do. Accordingly, when the audio device outputs the audio data, the microcomputer receives the audio data extending over the L channel and the R channel. However, since the audio device does not receive one audio data across the sample period, the program becomes complicated. Never become.

  An interface device according to a fourth aspect is the interface device according to the third aspect, wherein the inverting circuit is a first D-type flip-flop, the LR clock signal is input to a clear terminal, and a preset terminal is connected to a ground potential. The inverting output terminal is an output of the inverting circuit.

  In the present invention, the LR clock signal is input to the clear terminal in the first D-type flip-flop that is an inverting circuit. The preset terminal is connected to the ground potential. The inverting output terminal is the output of the inverting circuit. Therefore, when the LR clock signal is at a low level, the preset terminal is connected to the ground potential, and therefore, a high level signal is output from the inverted output terminal. When the LR clock signal is at a high level, since the preset terminal is connected to the ground potential, a low level signal is output from the inverting output terminal. Thus, in the present invention, the inverted LR clock signal obtained by inverting the LR clock signal is output from the inverted output terminal.

  An interface device according to a fifth aspect is the interface device according to the third aspect, wherein the inverting circuit is a first D-type flip-flop, a clear terminal is connected to a ground potential, and the LR clock signal is input to a preset terminal. The output terminal is an output of the inverting circuit.

  In the present invention, in the first D-type flip-flop that is an inverting circuit, the clear terminal is connected to the ground potential. Further, the LR clock signal is input to the clear terminal. The output terminal is the output of the inverting circuit. Accordingly, when the LR clock signal is at a low level, the clear terminal is connected to the ground potential, and thus a high level signal is output from the output terminal. Further, when the LR clock signal is at a high level, since the clear terminal is connected to the ground potential, a low level signal is output from the output terminal. Thus, in the present invention, the inverted LR clock signal obtained by inverting the LR clock signal is output from the output terminal.

  The interface device according to a sixth aspect of the present invention is the interface device according to any of the third to fifth aspects of the present invention, wherein the frequency dividing circuit is a second D-type flip-flop, the inverted LR clock signal is input to a clock terminal, and the input terminal is A signal from the inverting output terminal is input, and the output terminal is an output of the frequency dividing circuit.

  In the present invention, the inverted LR clock signal is input to the clock terminal in the second D-type flip-flop which is a frequency dividing circuit. The signal from the inverting output terminal is input to the input terminal. The output terminal is the output of the frequency dividing circuit. Accordingly, when the signal from the inverting output terminal is at the low level at the rising edge of the inverted LR clock signal, the next time until the inverted LR clock signal rises, that is, one cycle of the inverted LR clock signal, the signal from the output terminal is at the low level. Is output. Similarly, if the signal from the inverting output terminal is at the high level at the rising edge of the inverted LR clock signal, the next time the inverted LR clock signal rises, that is, one cycle of the inverted LR clock signal, the output terminal is high. A level signal is output. Thus, in the present invention, the divided LR clock signal obtained by dividing the inverted LR clock signal is output from the output terminal.

  An interface device according to a seventh aspect is the interface device according to the third aspect, wherein the inverting circuit is a first D-type flip-flop, the LR clock signal is input to a clear terminal, and a preset terminal is connected to a ground potential. The inverting output terminal is the output of the inverting circuit, the frequency dividing circuit is a second D-type flip-flop, the LR clock signal is input to the clock terminal, and the signal from the inverting output terminal is input to the input terminal The output terminal is an output of the frequency dividing circuit, and the first D-type flip-flop and the second D-type flip-flop are one logic IC.

  In the present invention, the first D flip-flop that is an inverting circuit and the second D flip-flop that is a frequency dividing circuit are one logic IC. For example, a logic IC called 7474 type has two D-type flip-flops. Therefore, since the inverting circuit and the frequency dividing circuit can be realized with one logic IC, the cost can be reduced.

  An interface device according to an eighth aspect is the interface device according to the third aspect, wherein the inverting circuit is a first D-type flip-flop, a clear terminal is connected to a ground potential, and the LR clock signal is input to a preset terminal. The output terminal is the output of the inverting circuit, the frequency dividing circuit is a second D flip-flop, the inverted LR clock signal is input to the clock terminal, and the signal from the inverted output terminal is input to the input terminal The output terminal is an output of the frequency dividing circuit, and the first D-type flip-flop and the second D-type flip-flop are one logic IC.

  In the present invention, the first D flip-flop that is an inverting circuit and the second D flip-flop that is a frequency dividing circuit are one logic IC. For example, a logic IC called 7474 type has two D-type flip-flops. Therefore, since the inverting circuit and the frequency dividing circuit can be realized with one logic IC, the cost can be reduced.

  ADVANTAGE OF THE INVENTION According to this invention, communication can be performed between the microcomputer and audio equipment with which bit slots which can respond | correspond are different.

It is a figure which shows the structure of the interface apparatus which concerns on embodiment of this invention. It is a truth table of a D-type flip-flop. It is a figure for demonstrating operation | movement of a D type flip-flop. It is a figure for demonstrating operation | movement of a D type flip-flop. It is a logic diagram of a logic IC. It is a figure for demonstrating operation | movement in case a microcomputer acquires audio data from a MEMS microphone via an interface apparatus. It is a figure for demonstrating operation | movement in case a microcomputer acquires audio data from a MEMS microphone via an interface apparatus. It is the figure which showed the audio data input into the bit clock signal, LR clock signal, and microcomputer which are input into a MEMS microphone. It is a figure which shows the structure of the interface apparatus which concerns on a modification. It is a figure for demonstrating the communication according to I2S. It is a figure for demonstrating the communication according to I2S.

  Hereinafter, embodiments of the present invention will be described. FIG. 1 is a diagram illustrating a basic configuration of an interface apparatus according to the present embodiment. The interface device 1 connects a microcomputer 101 and a MEMES microphone 102 (audio device) that serially outputs audio data to the microcomputer 101 and has different bit slots that can be used with the microcomputer 101. The microcomputer 101 and the MEMS microphone 102 perform communication according to I2S.

  The interface device 1 includes D-type flip-flops (hereinafter referred to as “DFF”) 2 and 3, an LR clock line LRCK, a frequency-divided LR clock line LRCK ′, a bit clock line BCLK, a data line DATA, and a resistor R.

  DFF2 (first D-type flip-flop) is an inverting circuit that inverts the LR clock signal output from the microcomputer 101 and outputs an inverted LR clock signal. In DFF2, the LR clock signal from the microcomputer 101 is input to the clear terminal / CLR. The DFF2 has a preset terminal / PR connected to the ground potential. Further, the DFF2 has an inverting output terminal / Q connected to the output, that is, the clock terminal CK of the DFF3. In DFF2, the input terminal D and the clock terminal CK are connected to the ground potential. Note that the input terminal D and the clock terminal CK may be connected to the power supply potential instead of the ground potential.

  The operation of DFF2 will be described. FIG. 2 is a truth table of DFF. FIG. 3 is a diagram for explaining the operation of the DFF. When the LR clock signal is at a low level, since the preset terminal / PR is connected to the ground potential, a high level signal is output from the inverted output terminal / Q. When the LR clock signal is at a high level, since the preset terminal / PR is connected to the ground potential, a low level signal is output from the inverting output terminal / Q. In this way, the DFF 2 inverts the LR clock signal and outputs an inverted LR clock signal.

  The DFF 3 (second D-type flip-flop) is a frequency dividing circuit that divides the inverted LR clock signal output from the DFF 2 and outputs a divided LR clock signal. In DFF3, the inverted LR clock signal is input to the clock terminal CK. In DFF3, a signal from the inverted output terminal / Q is input to the input terminal D. Further, the output terminal Q of the DFF 3 is connected to the output, that is, the MEMS microphone 102. The DFF 3 has a clear terminal / CLR and a preset terminal / PR connected to the power supply potential.

  The operation of DFF3 will be described. FIG. 2 is a truth table of DFF. FIG. 4 is a diagram for explaining the operation of the DFF. In DFF3, the inverted LR clock signal is input to the clock terminal CK. A signal from the inverted output terminal / Q is input to the input terminal D. The output terminal Q is an output. Accordingly, if the signal from the inverted output terminal / Q is at the low level at the rising edge of the inverted LR clock signal, the next time until the inverted LR clock signal rises, that is, one cycle of the inverted LR clock signal, from the output terminal Q. Outputs a low level signal. Similarly, when the signal from the inverted output terminal / Q is at the high level at the rising edge of the inverted LR clock signal, the next time until the inverted LR clock signal rises, that is, one cycle of the inverted LR clock signal, the output terminal Q Outputs a high level signal. In this way, the DFF 3 divides the inverted LR clock signal and outputs a divided LR clock signal.

  In the present embodiment, one logic IC is used as the DFFs 2 and 3. For example, since Fairchild Semiconductor's 74VHC74 has two DFFs, it can be used as DFFs 2 and 3. FIG. 5 shows a logic diagram of the logic IC.

  The LR clock line LRCK connects the microcomputer 101 and the DFF 2. The frequency-divided LR clock line LRCK ′ connects the DFF 3 and the MEMS microphone 102. The microcomputer 101 outputs an LR clock signal to the LR clock line LRCK.

  The bit clock line BCLK connects the microcomputer 101 and the MEMS microphone 102. The microcomputer 101 outputs a bit clock signal to the bit clock line BCLK. The data line DATA connects the microcomputer 101 and the MEMS microphone 102. The MEMS microphone 102 serially outputs audio data to the data line DATA. The resistor R connects the frequency-divided LR clock line LRCK ′ that connects the DFF 3 and the MEMS microphone 102 and the data line DATA.

  Hereinafter, an operation when the microcomputer 101 acquires audio data from the MEMS microphone 102 via the interface device 1 will be described with reference to FIG. The microcomputer 101 is compatible with a 32-bit slot. The MEMS microphone 102 is compatible with a 64-bit slot. The microcomputer 101 generates an LR clock signal (2 × LR clock signal) having a desired double sampling frequency and outputs it to the LR clock line LRCK. In addition, the microcomputer 101 generates a bit clock signal (2 × bit clock signal: 32 bits) of a 32-bit slot having a desired double sampling frequency and outputs it to the bit clock line BCLK.

  The LR clock signal (2 × LR clock signal) having a double sampling frequency is divided by the DFF 3. Therefore, the LR clock signal (frequency-divided LR clock signal) divided by the DFF 3 is input to the MEMS microphone 102 as an LR clock signal that can be handled by the MEMS microphone 102. Here, a bit clock signal of a 32-bit slot corresponding to a desired double sampling frequency is input to the MEMS microphone 102. Therefore, a 64-bit bit clock signal is input to the MEMS microphone 102 in one cycle of the divided LR clock signal. Therefore, the MEMS microphone 102 can output audio data to the microcomputer 101 corresponding to the LR clock signal and the bit clock signal output from the microcomputer 101 via the interface device 1.

  In communication according to I2S, the MEMS microphone 102 outputs L-channel audio data to the microcomputer 101 in synchronization with the low level of the divided LR clock signal. The MEMS microphone 102 outputs R channel audio data to the microcomputer 101 in synchronization with the high level of the divided LR clock signal. The microcomputer 101 normally captures audio data in pairs of L channel and R channel in the order of L channel and R channel. When the clock terminal CK rises, the DFF3 takes in the logic of the inverted output terminal / Q and inverts the logic of the output terminal Q and the inverted output terminal / Q. The periods corresponding to the L channel and R channel of the LR clock signal correspond to the periods of the LR clock signal in the order of high level and low level, respectively, and the timing at which the logic of the LR clock signal is inverted is the microcomputer 101. Occurs in the middle of the 32-bit slot. When the MEMS microphone 102 outputs audio data in synchronization with the LR clock signal, the microcomputer 101 receives 24-bit data starting from the second half of the 32-bit slot. That is, since the first 16 bits are received as the R channel and the latter 8 bits are received as the L channel of the next sample, the program becomes complicated and may cause a bug.

  Therefore, in this embodiment, as shown in FIG. 7, the LR clock signal is inverted by DFF2, and the inverted LR clock signal is divided by DFF3. As a result, the logic of the frequency-divided LR clock signal output from the output terminal Q of the DFF 3 changes when the LR clock signal falls, and both the low level period and the high level period of the 32-bit slot of the microcomputer 101 It corresponds to a period. Accordingly, when the MEMS microphone 102 outputs the audio data, the microcomputer 101 receives the audio data across the L channel and the R channel, but does not receive one audio data across the sample period. There is no complication.

  The microcomputer 101 outputs an LR clock signal having a desired double sampling frequency. Therefore, the L channel audio data is input to the microcomputer 101 in synchronization with the output LR clock signal of one cycle. Further, the R channel audio data is input to the microcomputer 101 in synchronization with the output LR clock signal of one cycle. Accordingly, there is a problem that the microcomputer 101 cannot discriminate between the L channel and R channel audio data. Therefore, in the present embodiment, the frequency-divided LR clock line LRCK ′ that connects the DFF 3 and the MEMS microphone 102 and the data line DATA are connected by a resistor R.

  FIG. 8 is a diagram showing a bit clock signal, an LR clock signal input to the MEMS microphone, and audio data input to the microcomputer. The MEMS microphone 102 outputs audio data of L channel 24 bits (valid data) and R channel 24 bits (valid data). Then, after outputting 24-bit audio data, the MEMS microphone 102 opens the data line DATA with high impedance. Here, the frequency-divided LR clock line LRCK ′ and the data line DATA are connected by a resistor R. Therefore, the data line DATA is output by the divided LR clock signal output to the divided LR clock line LRCK ′ until the R channel audio data is output after the L channel 24-bit audio data is output. , “00000001b” is output. The first 7 bits are set to “0” by the low-frequency divided LR clock signal. The last 1 bit becomes “1” by the high-frequency divided LR clock signal. The last 1 bit is “1” because the audio data is shifted by 1 bit from the edge of the LR clock signal in communication according to I2S.

  Further, after the R channel 24-bit audio data is output to the data line DATA, the divided LR clock signal output to the divided LR clock line LRCK ′ until the L channel audio data is output, “11111110b” is output. The first 7 bits are set to “1” by the high-level divided LR clock signal. The last 1 bit becomes “0” by the low-frequency divided LR clock signal. The last 1 bit is “1” because the audio data is shifted by 1 bit from the edge of the LR clock signal in communication according to I2S.

  As described above, the divided LR clock output to the divided LR clock line LRCK ′ until the R channel audio data is output after the L channel 24-bit audio data is output to the data line DATA. “00000001b” is output in response to the signal. Accordingly, the microcomputer 101 takes in the L channel audio data (valid data 24 bits) + “00000001b” (8 bits). Further, after the R channel 24-bit audio data is output to the data line DATA, the divided LR clock signal output to the divided LR clock line LRCK ′ until the L channel audio data is output, “11111110b” is output. Therefore, the microcomputer 101 captures R channel audio data (valid data 24 bits) + “1111110b” (8 bits). In the captured 32-bit data, the microcomputer 101 can determine whether the audio data is L channel or R channel from the 8-bit pattern (“00000001b”, “11111110b”) from the LSB of the audio data. it can. In addition, the microcomputer 101 can acquire L-channel or R-channel 24-bit audio data as valid data by performing 8-bit right bit shift from the captured data.

  Audio data is output to the data line DATA in the order of L channel and R channel. Therefore, if the microcomputer 101 determines which audio data is the L channel or the R channel, it can determine whether the continuous data is the audio data of the L channel or the R channel.

  The resistance value of the resistor R is set to a value that can be read by the microcomputer 101 when the MEMS microphone 102 opens the data line DATA with high impedance. In addition, the period during which the MEMS microphone 102 outputs valid data is set to a sufficiently large value so that the waveforms of the data line DATA and the frequency-divided LR clock line LRCK 'are not significantly disturbed.

  As described above, according to the present embodiment, communication can be performed between the microcomputer 101 and the MEMS microphone 102 having different compatible bit slots.

  In the present embodiment, the LR clock signal is inverted by DFF2 constituting one logic IC, and the inverted LR clock signal is divided by DFF3. Accordingly, since the signal is inverted and divided by one logic IC, the cost can be reduced.

  As mentioned above, although embodiment of this invention was described, the form which can apply this invention is not restricted to the above-mentioned embodiment, As suitably illustrated in the range which does not deviate from the meaning of this invention so that it may illustrate below. It is possible to make changes.

  FIG. 9 is a diagram illustrating a configuration of an interface device according to a modification. The configuration of the above-described embodiment and the DFF 2 is different. In DFF2, the clear terminal / CLR is connected to the ground potential. Further, the DFF 2 receives the LR clock signal at the preset terminal / PR. Further, the output terminal Q of the DFF2 is connected to the output, that is, the clock terminal CK of the DFF3. In DFF2, the input terminal D and the clock terminal CK are connected to the ground potential. Note that the input terminal D and the clock terminal CK may be connected to the power supply potential instead of the ground potential.

  The operation of DFF2 will be described. When the LR clock signal is at a low level, a high level signal is output from the output terminal Q because the clear terminal / CLR is connected to the ground potential. When the LR clock signal is at a high level, the clear terminal / CLR is connected to the ground potential, so that a low level signal is output from the output terminal Q. In this way, the DFF 2 inverts the LR clock signal and outputs an inverted LR clock signal.

  In the above-described embodiment, the resistor R connects the frequency-divided LR clock line LRCK ′ and the data line DATA. Not limited to this, the resistor R may not be provided. In this case, the determination of the L channel and the R channel of the audio data is executed by software processing.

  In the above-described embodiment, the DLR 2 inverts the LR clock signal output from the microcomputer 101 and the DFF 3 divides the inverted LR clock signal. Not limited to this, for example, the microcomputer 101 and the MEMS microphone 102 (audio device) communicate not in I2S but in a left justified or right justified format (the logic is opposite to that of I2S). When performing communication), the interface apparatus 1 may not include the DFF 2 (inversion circuit). In this case, the DLR 3 may divide the LR clock signal output from the microcomputer 101 and output the divided LR clock signal to the MEMS microphone 102. In this case, “11111111b” is output to the data line DATA by the frequency-divided LR clock signal output to the frequency-divided LR clock line LRCK ′ during a high-impedance period when the L-channel 24-bit audio data is not output. The All 8 bits are set to “1” by the high-level divided LR clock signal.

  In addition, “00000000b” is output to the data line DATA by the frequency-divided LR clock signal output to the frequency-divided LR clock line LRCK ′ during a high-impedance period during which no R-channel 24-bit audio data is output. . All 8 bits are set to “0” by the low-level divided LR clock signal. Note that since there is no deviation between the edge of the LR clock signal and the audio data as in communication according to I2S, all the 8 bits have the same logical value.

  Similar to the above-described embodiment, the microcomputer 101 reads the 8-bit pattern ("11111111b", "" from the LSB when the audio data is left-justified and from the MSB when it is right-justified. 00000000b "), it can be determined whether the audio data is L channel or R channel.

  In the above-described embodiment, the MEMS microphone 102 is exemplified as the audio device. For example, an A / D converter or the like may be used.

  In the above-described embodiment, the divided LR clock signal is extracted from the output terminal Q of the DFF 3. Not limited to this, the frequency-divided LR clock signal may be taken out from the inverting output terminal / Q of the DFF 3. In this case, the inverting output terminal / Q of the DFF 3 and the MEMS microphone 102 are connected by the divided LR clock line LRCK ′.

  In the above-described embodiment, the case where the DFFs 2 and 3 are one logic IC has been described. Not only this but DFF2, 3 may be a separate circuit.

  In the above-described embodiment, the case where the frequency dividing circuit is a D-type flip-flop has been described. Not limited to this, another frequency dividing circuit such as a frequency dividing circuit using a JK type flip-flop may be used. If the operation of the frequency divider used is a falling edge, an inverting circuit is not necessary for I2S, and an inverting circuit is prepared for right-justified and left-justified.

  In the above-described embodiment, the case where the inverting circuit is a D-type flip-flop has been described. Not only this but another inverting circuit, such as an inverter, may be used.

1 Interface device 2 DFF (first D-type flip-flop, inverting circuit)
3 DFF (second D-type flip-flop, frequency divider)
R resistor LRCK LR clock line LRCK 'divided LR clock line BCLK bit clock line DATA data line 101 microcomputer 102 MEMS microphone (audio equipment)

Claims (8)

An interface device that connects a microcomputer and an audio device that serially outputs audio data to the microcomputer and that has different bit slots compatible with the microcomputer,
A frequency dividing circuit that divides the LR clock signal output from the microcomputer and outputs a divided LR clock signal;
A frequency dividing LR clock line connecting the frequency dividing circuit and the audio device;
A bit clock line for connecting the microcomputer and the audio device, the microcomputer outputting a bit clock signal;
A data line for connecting the microcomputer and the audio device, and the audio device serially outputs the audio data;
An interface device comprising:   The interface apparatus according to claim 1, further comprising a resistor connecting the frequency-divided LR clock line and the data line. An inverting circuit that inverts the LR clock signal output from the microcomputer and outputs an inverted LR clock signal;
The frequency dividing circuit divides the inverted LR clock signal output from the inverting circuit and outputs the divided LR clock signal instead of the LR clock signal output from the microcomputer. The interface device according to claim 1 or 2. The inverting circuit is
A first D-type flip-flop;
4. The interface device according to claim 3, wherein the LR clock signal is input to a clear terminal, a preset terminal is connected to a ground potential, and an inverting output terminal is an output of the inverting circuit. The inverting circuit is
A first D-type flip-flop;
4. The interface device according to claim 3, wherein a clear terminal is connected to a ground potential, the LR clock signal is input to a preset terminal, and an output terminal is an output of the inverting circuit. The divider circuit is
A second D-type flip-flop;
6. The clock signal according to claim 3, wherein the inverted LR clock signal is input to the clock terminal, the signal from the inverted output terminal is input to the input terminal, and the output terminal is the output of the frequency divider circuit. The interface device according to item. The inverting circuit is
A first D-type flip-flop;
The LR clock signal is input to the clear terminal, the preset terminal is connected to the ground potential, the inverting output terminal is the output of the inverting circuit,
The divider circuit is
A second D-type flip-flop;
The inverted LR clock signal is input to the clock terminal, the signal from the inverted output terminal is input to the input terminal, and the output terminal is the output of the divider circuit;
4. The interface apparatus according to claim 3, wherein the first D-type flip-flop and the second D-type flip-flop are one logic IC. The inverting circuit is
A first D-type flip-flop;
The clear terminal is connected to the ground potential, the LR clock signal is input to the preset terminal, the output terminal is the output of the inverting circuit,
The divider circuit is
A second D-type flip-flop;
The inverted LR clock signal is input to the clock terminal, the signal from the inverted output terminal is input to the input terminal, and the output terminal is the output of the divider circuit;
4. The interface apparatus according to claim 3, wherein the first D-type flip-flop and the second D-type flip-flop are one logic IC.

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