JP2015198212A - glass interposer - Google Patents

glass interposer Download PDF

Info

Publication number
JP2015198212A
JP2015198212A JP2014076818A JP2014076818A JP2015198212A JP 2015198212 A JP2015198212 A JP 2015198212A JP 2014076818 A JP2014076818 A JP 2014076818A JP 2014076818 A JP2014076818 A JP 2014076818A JP 2015198212 A JP2015198212 A JP 2015198212A
Authority
JP
Japan
Prior art keywords
glass
interposer
electrode
glass interposer
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2014076818A
Other languages
Japanese (ja)
Inventor
真司 太田
Shinji Ota
真司 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP2014076818A priority Critical patent/JP2015198212A/en
Publication of JP2015198212A publication Critical patent/JP2015198212A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a glass interposer 1 improved in a heat dissipation effect in order to solve such a problem that a glass interposer is deteriorated in thermal conductivity while a base material itself is an insulation layer material and an interposer excellent in electrical characteristics is expected.SOLUTION: A glass interposer 1 includes a glass base material 4 including a plurality of through electrodes 5 provided therein and a plurality of insulation layers 2 and wiring layers 3 laminated on an upper part 6 and a lower part 7 of the glass base material 4. A through electrode diameter of the through electrodes 5 on a chip connection side is made larger than a through electrode diameter on a substrate connection side.

Description

本発明は、貫通電極付きのガラスインターポーザに関する発明で、特に放熱性能を改善するガラスインターポーザに関する。   The present invention relates to a glass interposer with a through electrode, and more particularly to a glass interposer that improves heat dissipation performance.

半導体素子を実装するインターポーザとしては、従来の有機インターポーザの他に、基材にシリコンを用いるインターポーザがハイエンド向けに世の中に出ている。   As an interposer for mounting a semiconductor element, in addition to a conventional organic interposer, an interposer using silicon as a base material has appeared in the world for the high end.

基材としてシリコンを用いたシリコンインターポーザは、微細な配線を形成することが出来る。また、シリコンは熱伝導率が高く、放熱性能に優れたインターポーザである。   A silicon interposer using silicon as a base material can form fine wiring. Silicon is an interposer with high thermal conductivity and excellent heat dissipation performance.

しかしながら、シリコンは材料が樹脂やガラスと比べるとコストが高く、また、シリコンは半導体で導電性の為、貫通電極とシリコン基板間に絶縁層を介在させる必要があり、高速伝送では信号波形の劣化が起きてしまう。   However, silicon is expensive compared to resin and glass, and silicon is a semiconductor and conductive, so an insulating layer must be interposed between the through electrode and the silicon substrate. Will happen.

特開2013−207006号公報JP2013-207006A

一方、ガラスを基材としたガラスインターポーザでは、基材自体が絶縁層物質であり、前述のような問題は起きず、電気特性の優れたインターポーザが期待されている。しかしながら、基材の熱伝導性がシリコンより劣るという問題がある。   On the other hand, in a glass interposer using glass as a base material, the base material itself is an insulating layer material, and the above-described problems do not occur, and an interposer having excellent electrical characteristics is expected. However, there is a problem that the thermal conductivity of the substrate is inferior to that of silicon.

本発明は、上記課題を解決する為に、放熱効果を改善したガラスインターポーザを提供することを目的とした。   An object of the present invention is to provide a glass interposer with an improved heat dissipation effect in order to solve the above problems.

本発明は、かかる課題に鑑みなされたもので、請求項1に記載の発明は、
複数の貫通電極を設けたガラス基材と、ガラス基材上下に積層された複数の絶縁層と配線層と、を備えるガラスインターポーザであって、
貫通電極のチップ接続側の貫通電極径を基板接続側の貫通電極径より大きくしたことを特徴とするガラスインターポーザである。
This invention is made | formed in view of this subject, The invention of Claim 1 is
A glass interposer comprising a glass substrate provided with a plurality of through electrodes, and a plurality of insulating layers and wiring layers laminated on the top and bottom of the glass substrate,
The glass interposer is characterized in that the through electrode diameter on the chip connection side of the through electrode is larger than the through electrode diameter on the substrate connection side.

前期貫通電極は、Cu、Ag、Au、Ni、Pt、Pd、Ru、Fe、およびこれらの金属の少なくとも1つを含む化合物の、いずれかで形成されても良い。   The first through electrode may be formed of any one of Cu, Ag, Au, Ni, Pt, Pd, Ru, Fe, and a compound containing at least one of these metals.

本発明の傾斜した貫通電極付きのガラスインターポーザによれば、チップ接続側の貫通電極径を大きくすることで放熱性能を向上することが出来る。   According to the glass interposer with an inclined through electrode of the present invention, the heat dissipation performance can be improved by increasing the diameter of the through electrode on the chip connection side.

一般的に、ガラス基材に比べて、貫通電極の熱伝導率は高い(たとえば、Cuの熱伝導率は398(W/mK)、ガラスの熱伝導率は1(W/mK))。チップ接続側の貫通電極径を大きく取ることによって、熱伝導率の高い領域が広がり、熱伝導率が高くなる。チップの発熱が主な熱源のため、チップ接続側の層の熱伝導率が高いと、チップの熱が拡散しやすくなり、放熱性能を向上することができる。   Generally, the thermal conductivity of the through electrode is higher than that of the glass substrate (for example, the thermal conductivity of Cu is 398 (W / mK), and the thermal conductivity of glass is 1 (W / mK)). By taking a large through-electrode diameter on the chip connection side, a region with high thermal conductivity is expanded and the thermal conductivity is increased. Since the heat generated by the chip is the main heat source, if the thermal conductivity of the layer on the chip connection side is high, the heat of the chip is easily diffused, and the heat dissipation performance can be improved.

本発明のガラスインターポーザの一実施形態の構成を断面で示した説明図である。It is explanatory drawing which showed the structure of one Embodiment of the glass interposer of this invention in the cross section. 本発明のガラスインターポーザの他の実施形態の構成を断面で示した説明図である。It is explanatory drawing which showed the structure of other embodiment of the glass interposer of this invention in the cross section. 本発明のガラスインターポーザの実施例の構成を斜視で示した説明図である。It is explanatory drawing which showed the structure of the Example of the glass interposer of this invention by the perspective view. 本発明のガラスインターポーザの実施例の構成の一部を拡大して断面で示した説明図である。It is explanatory drawing which expanded and showed a part of structure of the Example of the glass interposer of this invention in the cross section.

本発明の一実施形態について、図1から図2を参照して説明する。
図1は本発明のガラスインターポーザ1の一実施形態の構成を断面で示した説明図である。ガラス基材4の上下に絶縁層2と導体層3が積層されている。
An embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is an explanatory view showing the structure of an embodiment of the glass interposer 1 of the present invention in cross section. The insulating layer 2 and the conductor layer 3 are laminated on the upper and lower sides of the glass substrate 4.

図1では絶縁層2と導体層3が交互にかつ、上下共に3層で積層されているが、総数や上下で対称である必要性は無く、1実施例である。   In FIG. 1, the insulating layers 2 and the conductor layers 3 are alternately laminated in three layers on both the upper and lower sides. However, the total number and the upper and lower layers are not necessarily symmetrical, and this is an embodiment.

貫通電極5は、ガラス基材4を厚み方向に貫通するように形成されたスルーホールに導体性の物質からなる電極層が充填されて形成されている。
電極層の主材料としては、Cu、Ag、Au、Ni、Pt、Pd、Ru、Feまたはこれらの金属の少なくとも1つを含む化合物の、いずれかを用いることが好ましい。中でも特に電気特性やコストの両面で優れているのはCuである。
The through electrode 5 is formed by filling an electrode layer made of a conductive substance into a through hole formed so as to penetrate the glass substrate 4 in the thickness direction.
As a main material of the electrode layer, it is preferable to use any one of Cu, Ag, Au, Ni, Pt, Pd, Ru, Fe, or a compound containing at least one of these metals. Of these, Cu is particularly excellent in terms of both electrical characteristics and cost.

貫通電極5の径の大きさは、メモリーやロジックチップなどを積層する6側の方が、PCB基板と接触する7側に比べて大きくなるように設計される。6側の方が、7側に比べて1.5〜2.5倍の径の大きさであることが好ましい。   The diameter of the through electrode 5 is designed so that the side on which the memory, logic chip and the like are stacked is larger than the side on which the PCB is in contact with the PCB side. The 6 side is preferably 1.5 to 2.5 times as large as the 7 side.

図2は、本発明のガラスインターポーザの他の実施形態の構成を断面で示した説明図である。図1では貫通電極5は円錐台形状であるが、図2のように径の違う円柱を組み合わせた形状でもかまわない。ただし、チップ側6の径が基板側7の径より大きくする必要はある。   FIG. 2 is an explanatory view showing in cross section the configuration of another embodiment of the glass interposer of the present invention. In FIG. 1, the through electrode 5 has a truncated cone shape, but may have a shape in which cylinders having different diameters are combined as shown in FIG. 2. However, the diameter of the chip side 6 needs to be larger than the diameter of the substrate side 7.

貫通電極5のスルーホール作成方法としては、放電による絶縁破壊を用いた方法やレーザーによる穴あけなどがあり、特定の方法に限られるわけではない。   As a method for creating a through hole of the through electrode 5, there are a method using dielectric breakdown due to electric discharge and a hole drilling with a laser, and the like is not limited to a specific method.

スルーホールに電極層を作成する方法としては、メッキによる生成方法が有力な方法であるが、その方法に限られるわけではない。   As a method for creating an electrode layer in a through hole, a generation method by plating is a powerful method, but the method is not limited to that method.

ガラス基材4上下の絶縁層2に関してはメッキ法、熱酸化法、CVD法、ゾルゲル法などがあり、特に方法は限定されない。   The insulating layer 2 above and below the glass substrate 4 includes a plating method, a thermal oxidation method, a CVD method, a sol-gel method, and the like, and the method is not particularly limited.

導体層3の積層方法はセミアド法、気相法、浸漬法、塗工法などがあり、特に方法は限定されない。   The lamination method of the conductor layer 3 includes a semi-ad method, a gas phase method, a dipping method, a coating method, and the like, and the method is not particularly limited.

本発明の実施例を以下に示す。
図3は、本発明のガラスインターポーザの実施例の構成を斜視で示した説明図である。本発明の効果を検証するために、本発明のガラスインターポーザの一例をプリント配線版(図で、PCB8)に設定した構成を示しており、これをシミュレーションして放熱性を確
認する。JEDEC基準のPCB8上にガラスインターポーザ1を接続し、ガラスインターポーザ1上にメモリー9とロジックチップ10を載せる。各構成部品の寸法は以下の表1のようになる。また、メモリー9・ロジックチップ10とガラスインターポーザ1間ははんだで接続され、上接続の寸法になり、空間は樹脂で埋められている。PCB8とガラスインターポーザ1間もはんだで接続され、下接続の寸法となる。この空間は埋められていない。
Examples of the present invention are shown below.
FIG. 3 is an explanatory view showing a configuration of an embodiment of the glass interposer of the present invention in a perspective view. In order to verify the effect of the present invention, an example of a glass interposer according to the present invention is shown as a printed wiring board (PCB 8 in the figure), which is simulated to confirm heat dissipation. A glass interposer 1 is connected on a JEDEC standard PCB 8, and a memory 9 and a logic chip 10 are mounted on the glass interposer 1. The dimensions of each component are as shown in Table 1 below. In addition, the memory 9 / logic chip 10 and the glass interposer 1 are connected by solder, have the dimensions of the upper connection, and the space is filled with resin. The PCB 8 and the glass interposer 1 are also connected by soldering and have the dimensions of the bottom connection. This space is not filled.

図4は、本発明のガラスインターポーザの実施例の構成の一部を拡大して断面で示した説明図である。ガラス基材4は厚さ300μmになり、絶縁層2と導体層3はそれぞれ8μmとなっている。 FIG. 4 is an explanatory view showing a part of the configuration of the embodiment of the glass interposer of the present invention in an enlarged cross-sectional view. The glass substrate 4 has a thickness of 300 μm, and the insulating layer 2 and the conductor layer 3 each have a thickness of 8 μm.

各構成部品の熱物性は以下の表2のようになる。熱伝導率と比熱は温度依存を考慮した物性である。PCB8の熱伝導率は面内と厚み方向で異方性があり、表3の値となっている。   The thermophysical properties of each component are as shown in Table 2 below. Thermal conductivity and specific heat are physical properties considering temperature dependence. The thermal conductivity of PCB 8 has anisotropy in the plane and in the thickness direction, and has the values shown in Table 3.

熱源として、メモリー9とロジックチップ10を表4のように設定した。 As a heat source, the memory 9 and the logic chip 10 were set as shown in Table 4.

上記条件で、市販の熱流体解析ソフト(FloEFD)を用い、メモリーとロジックチップの温度を求め、放熱性を評価した。 Under the above conditions, using commercially available thermal fluid analysis software (FloEFD), the temperatures of the memory and the logic chip were obtained, and the heat dissipation was evaluated.

実施例として、貫通電極5を等間隔に3×3個設定し、チップ側6直径を4mm、基板側7の直径を3mmとした。   As an example, 3 × 3 penetration electrodes 5 were set at equal intervals, the diameter on the chip side 6 was 4 mm, and the diameter on the substrate side 7 was 3 mm.

この条件では、メモリーの平均温度は33.79℃、ロジックチップの平均温度は34.02℃となった。
<比較例1>
比較例1として、まずは貫通電極5無しの構成を検討した。
Under these conditions, the average temperature of the memory was 33.79 ° C., and the average temperature of the logic chip was 34.02 ° C.
<Comparative Example 1>
As Comparative Example 1, first, a configuration without the through electrode 5 was examined.

この条件では、メモリーの平均温度は33.84℃、ロジックチップの平均温度は34.08℃となった。実施例のほうが、温度が下がっている為、放熱性の改善が見られる。<比較例2>
比較例2として、スルーホールのみの構成を検討した。
Under these conditions, the average temperature of the memory was 33.84 ° C., and the average temperature of the logic chip was 34.08 ° C. In the example, since the temperature is lowered, the heat dissipation is improved. <Comparative Example 2>
As Comparative Example 2, the configuration of only through holes was examined.

この条件では、メモリーの平均温度は34.00℃、ロジックチップの平均温度は34.24℃となった。実施例のほうが、温度が下がっている為、放熱性の改善が見られる。<比較例3>
比較例3として、直径3mmの円柱の貫通電極5の構成を検討した。
Under these conditions, the average temperature of the memory was 34.00 ° C., and the average temperature of the logic chip was 34.24 ° C. In the example, since the temperature is lowered, the heat dissipation is improved. <Comparative Example 3>
As Comparative Example 3, the configuration of a cylindrical through electrode 5 having a diameter of 3 mm was examined.

この条件では、メモリーの平均温度は33.80℃、ロジックチップの平均温度は34.03℃となった。実施例のほうが、温度が下がっている為、放熱性の改善が見られる。<比較例4>
比較例4として、7側の直径4mm、6側の直径3mmの貫通電極5の構成を検討した。
Under these conditions, the average temperature of the memory was 33.80 ° C., and the average temperature of the logic chip was 34.03 ° C. In the example, since the temperature is lowered, the heat dissipation is improved. <Comparative Example 4>
As Comparative Example 4, the configuration of the through electrode 5 having a diameter of 7 mm on the 7 side and a diameter of 3 mm on the 6 side was examined.

この条件では、メモリーの平均温度は33.82℃、ロジックチップの平均温度は34
.05℃となった。実施例のほうが、温度が下がっている為、放熱性の改善が見られる。
Under this condition, the average temperature of the memory is 33.82 ° C. and the average temperature of the logic chip is 34
. It became 05 degreeC. In the example, since the temperature is lowered, the heat dissipation is improved.

全検討条件でのメモリー温度、ロジックチップ温度をまとめたのが表5である。この結果、6側の径が大きくなるように傾斜する本発明で放熱性が改善することがわかる。   Table 5 summarizes the memory temperature and logic chip temperature under all study conditions. As a result, it can be seen that the heat dissipation is improved by the present invention inclined so that the diameter on the 6 side increases.

上述の発明は、3次元実装などの高機能電子機器向けのインターポーザに利用できる。   The above-described invention can be used for an interposer for high-functional electronic devices such as three-dimensional mounting.

1…ガラスインターポーザ
2…絶縁層
3…導体層
4…ガラス基板
5…貫通電極
6…チップ側
7…(PCB)基板側
8…PCB
9…メモリー
10…ロジックチップ
DESCRIPTION OF SYMBOLS 1 ... Glass interposer 2 ... Insulating layer 3 ... Conductor layer 4 ... Glass substrate 5 ... Through electrode 6 ... Chip side 7 ... (PCB) Substrate side 8 ... PCB
9 ... Memory 10 ... Logic chip

Claims (1)

複数の貫通電極を設けたガラス基材と、ガラス基材上下に積層された複数の絶縁層と配線層と、を備えるガラスインターポーザであって、
貫通電極のチップ接続側の貫通電極径を基板接続側の貫通電極径より大きくしたことを特徴とするガラスインターポーザ。
A glass interposer comprising a glass substrate provided with a plurality of through electrodes, and a plurality of insulating layers and wiring layers laminated on the top and bottom of the glass substrate,
A glass interposer characterized in that the through electrode diameter on the chip connection side of the through electrode is larger than the through electrode diameter on the substrate connection side.
JP2014076818A 2014-04-03 2014-04-03 glass interposer Pending JP2015198212A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014076818A JP2015198212A (en) 2014-04-03 2014-04-03 glass interposer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014076818A JP2015198212A (en) 2014-04-03 2014-04-03 glass interposer

Publications (1)

Publication Number Publication Date
JP2015198212A true JP2015198212A (en) 2015-11-09

Family

ID=54547731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014076818A Pending JP2015198212A (en) 2014-04-03 2014-04-03 glass interposer

Country Status (1)

Country Link
JP (1) JP2015198212A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180068871A (en) 2016-12-14 2018-06-22 가부시기가이샤 디스코 Method for manufacturing an interposer
KR20180068862A (en) 2016-12-14 2018-06-22 가부시기가이샤 디스코 Method of manufacturing a interposer
KR20190008103A (en) 2017-07-14 2019-01-23 가부시기가이샤 디스코 Method for manufacturing a glass interposer
JP2019096676A (en) * 2017-11-20 2019-06-20 Tdk株式会社 Electronic component built-in structure and manufacturing method of electronic component built-in structure
CN110877485A (en) * 2018-09-05 2020-03-13 佳能株式会社 Liquid ejection head

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180068871A (en) 2016-12-14 2018-06-22 가부시기가이샤 디스코 Method for manufacturing an interposer
KR20180068862A (en) 2016-12-14 2018-06-22 가부시기가이샤 디스코 Method of manufacturing a interposer
US10115644B2 (en) 2016-12-14 2018-10-30 Disco Corporation Interposer manufacturing method
KR20190008103A (en) 2017-07-14 2019-01-23 가부시기가이샤 디스코 Method for manufacturing a glass interposer
US10796926B2 (en) 2017-07-14 2020-10-06 Disco Corporation Method of manufacturing glass interposer
JP2019096676A (en) * 2017-11-20 2019-06-20 Tdk株式会社 Electronic component built-in structure and manufacturing method of electronic component built-in structure
CN110877485A (en) * 2018-09-05 2020-03-13 佳能株式会社 Liquid ejection head
CN110877485B (en) * 2018-09-05 2021-09-17 佳能株式会社 Liquid ejection head

Similar Documents

Publication Publication Date Title
JP2015198212A (en) glass interposer
US9203008B2 (en) Multilayered LED printed circuit board
JP2015195368A (en) semiconductor package
US9781821B2 (en) Thermoelectric cooling module
JP2013219614A5 (en)
JP2012009828A (en) Multilayer circuit board
JP2017005131A5 (en)
JP5963732B2 (en) Method for setting surface area of radiator installation on back surface of wiring part of chip support substrate, chip support substrate, and chip mounting structure
JP2015012013A (en) Multilayer wiring board and probe card including the same
US9089072B2 (en) Heat radiating substrate and method for manufacturing the same
JP5902557B2 (en) Multilayer wiring board and electronic device
JP2013229490A (en) Wiring board and electronic apparatus
CN103779290B (en) Connect substrate and package-on-package structure
JP2019140321A (en) Electronic component mounting substrate and electronic device
JP2016046361A (en) Glass interposer
CN202736613U (en) Wafer resistor
JP3818310B2 (en) Multilayer board
JP2009129960A (en) Semiconductor device and its manufacturing method
JP2011166029A5 (en)
JP2015141952A (en) semiconductor power module
JP6533089B2 (en) Wiring board
US20080212287A1 (en) Semiconductor package structure with buried electronic device and manufacturing method therof
JP2015076564A (en) Ceramic wiring board
JP2014175642A5 (en)
JP2016012657A (en) Wiring board